1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the Conditional Moves implementation.
12 //===----------------------------------------------------------------------===//
15 // These instructions are expanded in
16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17 // conditional move instructions.
19 class CMov_I_I_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
20 InstrItinClass Itin> :
21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
23 let Constraints = "$F = $rd";
26 // cond:int, data:float
27 class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
28 InstrItinClass Itin> :
29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
31 let Constraints = "$F = $fd";
34 // cond:float, data:int
35 class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
36 SDPatternOperator OpNode = null_frag> :
37 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
38 !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
39 [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
41 let Constraints = "$F = $rd";
44 // cond:float, data:float
45 class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
46 SDPatternOperator OpNode = null_frag> :
47 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
48 !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
49 [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
51 let Constraints = "$F = $fd";
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
56 Instruction MOVZInst, Instruction SLTOp,
57 Instruction SLTuOp, Instruction SLTiOp,
58 Instruction SLTiuOp> {
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
62 (select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
63 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
65 (select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
66 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
68 (select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
69 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
71 (select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
72 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
74 (select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
75 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
78 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
79 Instruction MOVZInst, Instruction XOROp> {
80 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
81 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
82 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
83 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
86 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
87 Instruction MOVZInst, Instruction XORiOp> {
89 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
90 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
93 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
95 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
96 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
97 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
98 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
99 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
100 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
103 // Instantiation of instructions.
104 def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegs, CPURegs, NoItinerary>,
106 let Predicates = [HasStdEnc],
107 DecoderNamespace = "Mips64" in {
108 def MOVZ_I_I64 : CMov_I_I_FT<"movz", CPURegs, CPU64Regs, NoItinerary>,
110 def MOVZ_I64_I : CMov_I_I_FT<"movz", CPU64Regs, CPURegs, NoItinerary>,
112 let isCodeGenOnly = 1;
114 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64Regs, CPU64Regs, NoItinerary>,
116 let isCodeGenOnly = 1;
120 def MOVN_I_I : CMov_I_I_FT<"movn", CPURegs, CPURegs, NoItinerary>,
122 let Predicates = [HasStdEnc],
123 DecoderNamespace = "Mips64" in {
124 def MOVN_I_I64 : CMov_I_I_FT<"movn", CPURegs, CPU64Regs, NoItinerary>,
126 def MOVN_I64_I : CMov_I_I_FT<"movn", CPU64Regs, CPURegs, NoItinerary>,
128 let isCodeGenOnly = 1;
130 def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64Regs, CPU64Regs, NoItinerary>,
132 let isCodeGenOnly = 1;
136 def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
138 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
139 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
140 let DecoderNamespace = "Mips64";
143 def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
145 def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
146 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
147 let DecoderNamespace = "Mips64";
150 let Predicates = [NotFP64bit, HasStdEnc] in {
151 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
153 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
156 let Predicates = [IsFP64bit, HasStdEnc],
157 DecoderNamespace = "Mips64" in {
158 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
160 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
161 CMov_I_F_FM<18, 17> {
162 let isCodeGenOnly = 1;
164 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
166 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
167 CMov_I_F_FM<19, 17> {
168 let isCodeGenOnly = 1;
172 def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
173 def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
174 CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
175 let DecoderNamespace = "Mips64";
178 def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
179 def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
180 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
181 let DecoderNamespace = "Mips64";
184 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
186 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
189 let Predicates = [NotFP64bit, HasStdEnc] in {
190 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
192 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
195 let Predicates = [IsFP64bit, HasStdEnc],
196 DecoderNamespace = "Mips64" in {
197 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
199 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
203 // Instantiation of conditional move patterns.
204 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
205 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
206 defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
207 let Predicates = [HasMips64, HasStdEnc] in {
208 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
209 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
211 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
213 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
214 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
215 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
216 defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
217 defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
218 defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
221 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
222 let Predicates = [HasMips64, HasStdEnc] in {
223 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
224 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
225 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
228 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
229 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
230 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
231 let Predicates = [HasMips64, HasStdEnc] in {
232 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
234 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
235 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
238 let Predicates = [NotFP64bit, HasStdEnc] in {
239 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
240 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
241 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
243 let Predicates = [IsFP64bit, HasStdEnc] in {
244 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
245 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
247 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
248 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
249 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
250 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;