1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the Conditional Moves implementation.
12 //===----------------------------------------------------------------------===//
15 // These instructions are expanded in
16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17 // conditional move instructions.
19 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
21 FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
24 let Constraints = "$F = $rd";
27 // cond:int, data:float
28 class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
29 InstrItinClass Itin> :
30 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
31 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
32 let Constraints = "$F = $fd";
35 // cond:float, data:int
36 class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
37 SDPatternOperator OpNode = null_frag> :
38 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
39 !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
40 [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
42 let Constraints = "$F = $rd";
45 // cond:float, data:float
46 class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
47 SDPatternOperator OpNode = null_frag> :
48 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
49 !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
50 [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
52 let Constraints = "$F = $fd";
56 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
57 Instruction MOVZInst, Instruction SLTOp,
58 Instruction SLTuOp, Instruction SLTiOp,
59 Instruction SLTiuOp> {
60 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
61 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 (select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
64 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
66 (select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
67 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
69 (select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
70 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
72 (select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
73 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
75 (select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
76 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
79 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
80 Instruction MOVZInst, Instruction XOROp> {
81 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
82 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
83 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
84 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
87 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
88 Instruction MOVZInst, Instruction XORiOp> {
90 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
91 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
94 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
96 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
97 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
98 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
99 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
100 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
101 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
104 // Instantiation of instructions.
105 def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
106 let Predicates = [HasStdEnc],
107 DecoderNamespace = "Mips64" in {
108 def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
109 def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
110 let isCodeGenOnly = 1;
112 def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz"> {
113 let isCodeGenOnly = 1;
117 def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
118 let Predicates = [HasStdEnc],
119 DecoderNamespace = "Mips64" in {
120 def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
121 def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
122 let isCodeGenOnly = 1;
124 def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn"> {
125 let isCodeGenOnly = 1;
129 def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
131 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
132 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
133 let DecoderNamespace = "Mips64";
136 def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
138 def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
139 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
140 let DecoderNamespace = "Mips64";
143 let Predicates = [NotFP64bit, HasStdEnc] in {
144 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
146 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
149 let Predicates = [IsFP64bit, HasStdEnc],
150 DecoderNamespace = "Mips64" in {
151 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
153 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
154 CMov_I_F_FM<18, 17> {
155 let isCodeGenOnly = 1;
157 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
159 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
160 CMov_I_F_FM<19, 17> {
161 let isCodeGenOnly = 1;
165 def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
166 def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
167 CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
168 let DecoderNamespace = "Mips64";
171 def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
172 def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
173 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
174 let DecoderNamespace = "Mips64";
177 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
179 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
182 let Predicates = [NotFP64bit, HasStdEnc] in {
183 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
185 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
188 let Predicates = [IsFP64bit, HasStdEnc],
189 DecoderNamespace = "Mips64" in {
190 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
192 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
196 // Instantiation of conditional move patterns.
197 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
198 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
199 defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
200 let Predicates = [HasMips64, HasStdEnc] in {
201 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
202 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
204 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
206 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
207 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
208 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
209 defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
210 defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
211 defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
214 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
215 let Predicates = [HasMips64, HasStdEnc] in {
216 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
217 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
218 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
221 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
222 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
223 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
224 let Predicates = [HasMips64, HasStdEnc] in {
225 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
227 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
228 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
231 let Predicates = [NotFP64bit, HasStdEnc] in {
232 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
233 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
234 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
236 let Predicates = [IsFP64bit, HasStdEnc] in {
237 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
238 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
240 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
241 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
242 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
243 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;