1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the Conditional Moves implementation.
12 //===----------------------------------------------------------------------===//
15 // These instructions are expanded in
16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17 // conditional move instructions.
19 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
21 FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
24 let Constraints = "$F = $rd";
27 // cond:int, data:float
28 class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
29 bits<6> func, string instr_asm> :
30 FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
31 !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
34 let Constraints = "$F = $fd";
37 // cond:float, data:int
38 class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
40 FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
41 !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
42 [(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
45 let Constraints = "$F = $rd";
48 // cond:float, data:float
49 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
51 FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
52 !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
53 [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
56 let Constraints = "$F = $fd";
60 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
61 Instruction MOVZInst, Instruction SLTOp,
62 Instruction SLTuOp, Instruction SLTiOp,
63 Instruction SLTiuOp> {
64 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
65 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
67 (select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
68 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
70 (select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
71 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
73 (select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
74 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
76 (select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
77 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
79 (select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
80 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
83 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
84 Instruction MOVZInst, Instruction XOROp> {
85 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
86 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
87 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
88 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
91 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
92 Instruction MOVZInst, Instruction XORiOp> {
94 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
95 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
98 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
100 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
101 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
102 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
103 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
104 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
105 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
108 // Instantiation of instructions.
109 def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
110 let Predicates = [HasMips64, HasStandardEncoding],
111 DecoderNamespace = "Mips64" in {
112 def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
113 def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
114 let isCodeGenOnly = 1;
116 def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz"> {
117 let isCodeGenOnly = 1;
121 def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
122 let Predicates = [HasMips64, HasStandardEncoding],
123 DecoderNamespace = "Mips64" in {
124 def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
125 def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
126 let isCodeGenOnly = 1;
128 def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn"> {
129 let isCodeGenOnly = 1;
133 def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
134 def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
135 Requires<[HasMips64, HasStandardEncoding]> {
136 let DecoderNamespace = "Mips64";
139 def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
140 def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
141 Requires<[HasMips64, HasStandardEncoding]> {
142 let DecoderNamespace = "Mips64";
145 let Predicates = [NotFP64bit, HasStandardEncoding] in {
146 def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
147 def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
149 let Predicates = [IsFP64bit, HasStandardEncoding],
150 DecoderNamespace = "Mips64" in {
151 def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
152 def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d"> {
153 let isCodeGenOnly = 1;
155 def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
156 def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d"> {
157 let isCodeGenOnly = 1;
161 def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
162 def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
163 Requires<[HasMips64, HasStandardEncoding]> {
164 let DecoderNamespace = "Mips64";
167 def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
168 def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
169 Requires<[HasMips64, HasStandardEncoding]> {
170 let DecoderNamespace = "Mips64";
173 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
174 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
176 let Predicates = [NotFP64bit, HasStandardEncoding] in {
177 def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
178 def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
180 let Predicates = [IsFP64bit, HasStandardEncoding],
181 DecoderNamespace = "Mips64" in {
182 def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
183 def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
186 // Instantiation of conditional move patterns.
187 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
188 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
189 defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
190 let Predicates = [HasMips64, HasStandardEncoding] in {
191 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
192 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
194 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
196 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
197 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
198 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
199 defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
200 defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
201 defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
204 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
205 let Predicates = [HasMips64, HasStandardEncoding] in {
206 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
207 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
208 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
211 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
212 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
213 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
214 let Predicates = [HasMips64, HasStandardEncoding] in {
215 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
217 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
218 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
221 let Predicates = [NotFP64bit, HasStandardEncoding] in {
222 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
223 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
224 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
226 let Predicates = [IsFP64bit, HasStandardEncoding] in {
227 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
228 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
230 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
231 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
232 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
233 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;