2 // These instructions are expanded in
3 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
4 // conditional move instructions.
6 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
8 FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
9 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
11 let Constraints = "$F = $rd";
14 // cond:int, data:float
15 class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
16 bits<6> func, string instr_asm> :
17 FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
18 !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
19 let Constraints = "$F = $fd";
22 // cond:float, data:int
23 class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
25 FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
26 !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
27 [(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
30 let Constraints = "$F = $rd";
33 // cond:float, data:float
34 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
36 FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
37 !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
38 [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
41 let Constraints = "$F = $fd";
45 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
46 Instruction MOVZInst, Instruction SLTOp,
47 Instruction SLTuOp, Instruction SLTiOp,
48 Instruction SLTiuOp> {
49 def : Pat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
50 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
51 def : Pat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
52 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
53 def : Pat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
54 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
55 def : Pat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
56 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
57 def : Pat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
58 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
59 def : Pat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
63 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
64 Instruction MOVZInst, Instruction XOROp> {
65 def : Pat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
66 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
67 def : Pat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
68 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
71 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
73 def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
74 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
75 def : Pat<(select CRC:$cond, DRC:$T, DRC:$F),
76 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
77 def : Pat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
78 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
81 // Instantiation of instructions.
82 def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
83 let Predicates = [HasMips64] in {
84 def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
85 def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz">;
86 def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz">;
89 def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
90 let Predicates = [HasMips64] in {
91 def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
92 def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn">;
93 def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn">;
96 def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
97 def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
98 Requires<[HasMips64]>;
100 def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
101 def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
102 Requires<[HasMips64]>;
104 let Predicates = [NotFP64bit] in {
105 def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
106 def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
108 let Predicates = [IsFP64bit] in {
109 def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
110 def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d">;
111 def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
112 def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d">;
115 def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
116 def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
117 Requires<[HasMips64]>;
119 def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 1, "movf">;
120 def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 1, "movf">,
121 Requires<[HasMips64]>;
123 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
124 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
126 let Predicates = [NotFP64bit] in {
127 def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
128 def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
130 let Predicates = [IsFP64bit] in {
131 def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
132 def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
135 // Instantiation of conditional move patterns.
136 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
137 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
138 let Predicates = [HasMips64] in {
139 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
140 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
142 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
144 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
145 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
146 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
149 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
150 let Predicates = [HasMips64] in {
151 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
152 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
153 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
156 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
157 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
158 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
159 let Predicates = [HasMips64] in {
160 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
162 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
163 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
166 let Predicates = [NotFP64bit] in {
167 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
168 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
169 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
171 let Predicates = [IsFP64bit] in {
172 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
173 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
175 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
176 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
177 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
178 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;