2 // These instructions are expanded in
3 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
4 // conditional move instructions.
6 class CondMovIntInt<bits<6> funct, string instr_asm> :
7 FR<0, funct, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
8 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
10 let usesCustomInserter = 1;
11 let Constraints = "$F = $rd";
14 // cond:int, data:float
15 class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
17 FFR<0x11, func, fmt, (outs RC:$fd), (ins RC:$fs, CPURegs:$rt, RC:$F),
18 !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
19 let usesCustomInserter = 1;
20 let Constraints = "$F = $fd";
23 // cond:float, data:int
24 class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
25 FCMOV<tf, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$F),
26 !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
27 [(set CPURegs:$rd, (cmov CPURegs:$rs, CPURegs:$F))]> {
29 let usesCustomInserter = 1;
31 let Constraints = "$F = $rd";
34 // cond:float, data:float
35 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
37 FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
38 !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
39 [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
41 let usesCustomInserter = 1;
43 let Constraints = "$F = $fd";
47 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
48 def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
49 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
50 def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
51 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
52 def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
53 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
54 def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
55 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
56 def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
57 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
58 def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
59 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
60 def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
61 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
62 def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
63 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
66 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
67 def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
68 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
69 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
70 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
71 def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
72 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
75 // Instantiation of instructions.
76 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
77 def MOVN_I : CondMovIntInt<0x0b, "movn">;
79 def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
80 def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
81 let Predicates = [NotFP64bit] in {
82 def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
83 def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
86 def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
87 def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
89 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
90 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
91 let Predicates = [NotFP64bit] in {
92 def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
93 def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
96 // Instantiation of conditional move patterns.
97 defm : MovzPats<CPURegs, MOVZ_I>;
98 defm : MovnPats<CPURegs, MOVN_I>;
100 defm : MovzPats<FGR32, MOVZ_S>;
101 defm : MovnPats<FGR32, MOVN_S>;
103 let Predicates = [NotFP64bit] in {
104 defm : MovzPats<AFGR64, MOVZ_D>;
105 defm : MovnPats<AFGR64, MOVN_D>;