1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 def Dsp2MicroMips : InstrMapping {
13 let FilterClass = "DspMMRel";
14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
16 // Instructions with the same predicate sense form a column.
17 let ColFields = ["Arch"];
18 // The key column is the unpredicated instructions.
20 // Value columns are PredSense=true and PredSense=false
21 let ValueCols = [["dsp"], ["mmdsp"]];
24 def HasDSP : Predicate<"Subtarget->hasDSP()">,
25 AssemblerPredicate<"FeatureDSP">;
26 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27 AssemblerPredicate<"FeatureDSPR2">;
28 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
29 AssemblerPredicate<"FeatureDSPR3">;
32 list<Predicate> InsnPredicates = [HasDSPR2];
36 class Field6<bits<6> val> {
40 def SPECIAL3_OPCODE : Field6<0b011111>;
41 def REGIMM_OPCODE : Field6<0b000001>;
43 class DSPInst<string opstr = "">
44 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
45 let Predicates = [HasDSP];
46 string BaseOpcode = opstr;
50 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
51 InstrItinClass itin = IIPseudo>:
52 MipsPseudo<outs, ins, pattern, itin> {
53 let Predicates = [HasDSP];
56 // ADDU.QB sub-class format.
57 class ADDU_QB_FMT<bits<5> op> : DSPInst {
62 let Opcode = SPECIAL3_OPCODE.V;
68 let Inst{5-0} = 0b010000;
71 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
75 let Opcode = SPECIAL3_OPCODE.V;
81 let Inst{5-0} = 0b010000;
84 // CMPU.EQ.QB sub-class format.
85 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
89 let Opcode = SPECIAL3_OPCODE.V;
95 let Inst{5-0} = 0b010001;
98 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
103 let Opcode = SPECIAL3_OPCODE.V;
105 let Inst{25-21} = rs;
106 let Inst{20-16} = rt;
107 let Inst{15-11} = rd;
109 let Inst{5-0} = 0b010001;
112 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
117 let Opcode = SPECIAL3_OPCODE.V;
119 let Inst{25-21} = rs;
120 let Inst{20-16} = rt;
121 let Inst{15-11} = sa;
123 let Inst{5-0} = 0b010001;
126 // ABSQ_S.PH sub-class format.
127 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
131 let Opcode = SPECIAL3_OPCODE.V;
134 let Inst{20-16} = rt;
135 let Inst{15-11} = rd;
137 let Inst{5-0} = 0b010010;
141 class REPL_FMT<bits<5> op> : DSPInst {
145 let Opcode = SPECIAL3_OPCODE.V;
147 let Inst{25-16} = imm;
148 let Inst{15-11} = rd;
150 let Inst{5-0} = 0b010010;
153 // SHLL.QB sub-class format.
154 class SHLL_QB_FMT<bits<5> op> : DSPInst {
159 let Opcode = SPECIAL3_OPCODE.V;
161 let Inst{25-21} = rs_sa;
162 let Inst{20-16} = rt;
163 let Inst{15-11} = rd;
165 let Inst{5-0} = 0b010011;
168 // LX sub-class format.
169 class LX_FMT<bits<5> op> : DSPInst {
174 let Opcode = SPECIAL3_OPCODE.V;
176 let Inst{25-21} = base;
177 let Inst{20-16} = index;
178 let Inst{15-11} = rd;
180 let Inst{5-0} = 0b001010;
183 // ADDUH.QB sub-class format.
184 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
189 let Opcode = SPECIAL3_OPCODE.V;
191 let Inst{25-21} = rs;
192 let Inst{20-16} = rt;
193 let Inst{15-11} = rd;
195 let Inst{5-0} = 0b011000;
198 // APPEND sub-class format.
199 class APPEND_FMT<bits<5> op> : DSPInst {
204 let Opcode = SPECIAL3_OPCODE.V;
206 let Inst{25-21} = rs;
207 let Inst{20-16} = rt;
208 let Inst{15-11} = sa;
210 let Inst{5-0} = 0b110001;
213 // DPA.W.PH sub-class format.
214 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
219 let Opcode = SPECIAL3_OPCODE.V;
221 let Inst{25-21} = rs;
222 let Inst{20-16} = rt;
224 let Inst{12-11} = ac;
226 let Inst{5-0} = 0b110000;
229 // MULT sub-class format.
230 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
237 let Inst{25-21} = rs;
238 let Inst{20-16} = rt;
240 let Inst{12-11} = ac;
242 let Inst{5-0} = funct;
245 // MFHI sub-class format.
246 class MFHI_FMT<bits<6> funct> : DSPInst {
252 let Inst{22-21} = ac;
254 let Inst{15-11} = rd;
256 let Inst{5-0} = funct;
259 // MTHI sub-class format.
260 class MTHI_FMT<bits<6> funct> : DSPInst {
265 let Inst{25-21} = rs;
267 let Inst{12-11} = ac;
269 let Inst{5-0} = funct;
272 // EXTR.W sub-class format (type 1).
273 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
278 let Opcode = SPECIAL3_OPCODE.V;
280 let Inst{25-21} = shift_rs;
281 let Inst{20-16} = rt;
283 let Inst{12-11} = ac;
285 let Inst{5-0} = 0b111000;
288 // SHILO sub-class format.
289 class SHILO_R1_FMT<bits<5> op> : DSPInst {
293 let Opcode = SPECIAL3_OPCODE.V;
295 let Inst{25-20} = shift;
297 let Inst{12-11} = ac;
299 let Inst{5-0} = 0b111000;
302 class SHILO_R2_FMT<bits<5> op> : DSPInst {
306 let Opcode = SPECIAL3_OPCODE.V;
308 let Inst{25-21} = rs;
310 let Inst{12-11} = ac;
312 let Inst{5-0} = 0b111000;
315 class RDDSP_FMT<bits<5> op> : DSPInst {
319 let Opcode = SPECIAL3_OPCODE.V;
321 let Inst{25-16} = mask;
322 let Inst{15-11} = rd;
324 let Inst{5-0} = 0b111000;
327 class WRDSP_FMT<bits<5> op> : DSPInst {
331 let Opcode = SPECIAL3_OPCODE.V;
333 let Inst{25-21} = rs;
334 let Inst{20-11} = mask;
336 let Inst{5-0} = 0b111000;
339 class BPOSGE32_FMT<bits<5> op> : DSPInst {
342 let Opcode = REGIMM_OPCODE.V;
345 let Inst{20-16} = op;
346 let Inst{15-0} = offset;
349 // INSV sub-class format.
350 class INSV_FMT<bits<6> op> : DSPInst {
354 let Opcode = SPECIAL3_OPCODE.V;
356 let Inst{25-21} = rs;
357 let Inst{20-16} = rt;