1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasDSP : Predicate<"Subtarget.hasDSP()">,
11 AssemblerPredicate<"FeatureDSP">;
12 def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
13 AssemblerPredicate<"FeatureDSPR2">;
16 class Field6<bits<6> val> {
20 def SPECIAL3_OPCODE : Field6<0b011111>;
21 def REGIMM_OPCODE : Field6<0b000001>;
23 class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24 let Predicates = [HasDSP];
27 class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
28 MipsPseudo<outs, ins, "", pattern> {
29 let Predicates = [HasDSP];
32 // ADDU.QB sub-class format.
33 class ADDU_QB_FMT<bits<5> op> : DSPInst {
38 let Opcode = SPECIAL3_OPCODE.V;
44 let Inst{5-0} = 0b010000;
47 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
51 let Opcode = SPECIAL3_OPCODE.V;
57 let Inst{5-0} = 0b010000;
60 // CMPU.EQ.QB sub-class format.
61 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
65 let Opcode = SPECIAL3_OPCODE.V;
71 let Inst{5-0} = 0b010001;
74 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
79 let Opcode = SPECIAL3_OPCODE.V;
85 let Inst{5-0} = 0b010001;
88 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
93 let Opcode = SPECIAL3_OPCODE.V;
99 let Inst{5-0} = 0b010001;
102 // ABSQ_S.PH sub-class format.
103 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
107 let Opcode = SPECIAL3_OPCODE.V;
110 let Inst{20-16} = rt;
111 let Inst{15-11} = rd;
113 let Inst{5-0} = 0b010010;
117 class REPL_FMT<bits<5> op> : DSPInst {
121 let Opcode = SPECIAL3_OPCODE.V;
123 let Inst{25-16} = imm;
124 let Inst{15-11} = rd;
126 let Inst{5-0} = 0b010010;
129 // SHLL.QB sub-class format.
130 class SHLL_QB_FMT<bits<5> op> : DSPInst {
135 let Opcode = SPECIAL3_OPCODE.V;
137 let Inst{25-21} = rs_sa;
138 let Inst{20-16} = rt;
139 let Inst{15-11} = rd;
141 let Inst{5-0} = 0b010011;
144 // LX sub-class format.
145 class LX_FMT<bits<5> op> : DSPInst {
150 let Opcode = SPECIAL3_OPCODE.V;
152 let Inst{25-21} = base;
153 let Inst{20-16} = index;
154 let Inst{15-11} = rd;
156 let Inst{5-0} = 0b001010;
159 // ADDUH.QB sub-class format.
160 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
165 let Opcode = SPECIAL3_OPCODE.V;
167 let Inst{25-21} = rs;
168 let Inst{20-16} = rt;
169 let Inst{15-11} = rd;
171 let Inst{5-0} = 0b011000;
174 // APPEND sub-class format.
175 class APPEND_FMT<bits<5> op> : DSPInst {
180 let Opcode = SPECIAL3_OPCODE.V;
182 let Inst{25-21} = rs;
183 let Inst{20-16} = rt;
184 let Inst{15-11} = sa;
186 let Inst{5-0} = 0b110001;
189 // DPA.W.PH sub-class format.
190 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
195 let Opcode = SPECIAL3_OPCODE.V;
197 let Inst{25-21} = rs;
198 let Inst{20-16} = rt;
200 let Inst{12-11} = ac;
202 let Inst{5-0} = 0b110000;
205 // MULT sub-class format.
206 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
213 let Inst{25-21} = rs;
214 let Inst{20-16} = rt;
216 let Inst{12-11} = ac;
218 let Inst{5-0} = funct;
221 // EXTR.W sub-class format (type 1).
222 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
227 let Opcode = SPECIAL3_OPCODE.V;
229 let Inst{25-21} = shift_rs;
230 let Inst{20-16} = rt;
232 let Inst{12-11} = ac;
234 let Inst{5-0} = 0b111000;
237 // SHILO sub-class format.
238 class SHILO_R1_FMT<bits<5> op> : DSPInst {
242 let Opcode = SPECIAL3_OPCODE.V;
244 let Inst{25-20} = shift;
246 let Inst{12-11} = ac;
248 let Inst{5-0} = 0b111000;
251 class SHILO_R2_FMT<bits<5> op> : DSPInst {
255 let Opcode = SPECIAL3_OPCODE.V;
257 let Inst{25-21} = rs;
259 let Inst{12-11} = ac;
261 let Inst{5-0} = 0b111000;
264 class RDDSP_FMT<bits<5> op> : DSPInst {
268 let Opcode = SPECIAL3_OPCODE.V;
270 let Inst{25-16} = mask;
271 let Inst{15-11} = rd;
273 let Inst{5-0} = 0b111000;
276 class WRDSP_FMT<bits<5> op> : DSPInst {
280 let Opcode = SPECIAL3_OPCODE.V;
282 let Inst{25-21} = rs;
283 let Inst{20-11} = mask;
285 let Inst{5-0} = 0b111000;
288 class BPOSGE32_FMT<bits<5> op> : DSPInst {
291 let Opcode = REGIMM_OPCODE.V;
294 let Inst{20-16} = op;
295 let Inst{15-0} = offset;
298 // INSV sub-class format.
299 class INSV_FMT<bits<6> op> : DSPInst {
303 let Opcode = SPECIAL3_OPCODE.V;
305 let Inst{25-21} = rs;
306 let Inst{20-16} = rt;