1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasDSP : Predicate<"Subtarget->hasDSP()">,
11 AssemblerPredicate<"FeatureDSP">;
12 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
13 AssemblerPredicate<"FeatureDSPR2">;
16 class Field6<bits<6> val> {
20 def SPECIAL3_OPCODE : Field6<0b011111>;
21 def REGIMM_OPCODE : Field6<0b000001>;
23 class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24 let Predicates = [HasDSP];
27 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
28 InstrItinClass itin = IIPseudo>:
29 MipsPseudo<outs, ins, pattern, itin> {
30 let Predicates = [HasDSP];
33 // ADDU.QB sub-class format.
34 class ADDU_QB_FMT<bits<5> op> : DSPInst {
39 let Opcode = SPECIAL3_OPCODE.V;
45 let Inst{5-0} = 0b010000;
48 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
52 let Opcode = SPECIAL3_OPCODE.V;
58 let Inst{5-0} = 0b010000;
61 // CMPU.EQ.QB sub-class format.
62 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
66 let Opcode = SPECIAL3_OPCODE.V;
72 let Inst{5-0} = 0b010001;
75 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
80 let Opcode = SPECIAL3_OPCODE.V;
86 let Inst{5-0} = 0b010001;
89 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
94 let Opcode = SPECIAL3_OPCODE.V;
100 let Inst{5-0} = 0b010001;
103 // ABSQ_S.PH sub-class format.
104 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
108 let Opcode = SPECIAL3_OPCODE.V;
111 let Inst{20-16} = rt;
112 let Inst{15-11} = rd;
114 let Inst{5-0} = 0b010010;
118 class REPL_FMT<bits<5> op> : DSPInst {
122 let Opcode = SPECIAL3_OPCODE.V;
124 let Inst{25-16} = imm;
125 let Inst{15-11} = rd;
127 let Inst{5-0} = 0b010010;
130 // SHLL.QB sub-class format.
131 class SHLL_QB_FMT<bits<5> op> : DSPInst {
136 let Opcode = SPECIAL3_OPCODE.V;
138 let Inst{25-21} = rs_sa;
139 let Inst{20-16} = rt;
140 let Inst{15-11} = rd;
142 let Inst{5-0} = 0b010011;
145 // LX sub-class format.
146 class LX_FMT<bits<5> op> : DSPInst {
151 let Opcode = SPECIAL3_OPCODE.V;
153 let Inst{25-21} = base;
154 let Inst{20-16} = index;
155 let Inst{15-11} = rd;
157 let Inst{5-0} = 0b001010;
160 // ADDUH.QB sub-class format.
161 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
166 let Opcode = SPECIAL3_OPCODE.V;
168 let Inst{25-21} = rs;
169 let Inst{20-16} = rt;
170 let Inst{15-11} = rd;
172 let Inst{5-0} = 0b011000;
175 // APPEND sub-class format.
176 class APPEND_FMT<bits<5> op> : DSPInst {
181 let Opcode = SPECIAL3_OPCODE.V;
183 let Inst{25-21} = rs;
184 let Inst{20-16} = rt;
185 let Inst{15-11} = sa;
187 let Inst{5-0} = 0b110001;
190 // DPA.W.PH sub-class format.
191 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
196 let Opcode = SPECIAL3_OPCODE.V;
198 let Inst{25-21} = rs;
199 let Inst{20-16} = rt;
201 let Inst{12-11} = ac;
203 let Inst{5-0} = 0b110000;
206 // MULT sub-class format.
207 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
214 let Inst{25-21} = rs;
215 let Inst{20-16} = rt;
217 let Inst{12-11} = ac;
219 let Inst{5-0} = funct;
222 // MFHI sub-class format.
223 class MFHI_FMT<bits<6> funct> : DSPInst {
229 let Inst{22-21} = ac;
231 let Inst{15-11} = rd;
233 let Inst{5-0} = funct;
236 // MTHI sub-class format.
237 class MTHI_FMT<bits<6> funct> : DSPInst {
242 let Inst{25-21} = rs;
244 let Inst{12-11} = ac;
246 let Inst{5-0} = funct;
249 // EXTR.W sub-class format (type 1).
250 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
255 let Opcode = SPECIAL3_OPCODE.V;
257 let Inst{25-21} = shift_rs;
258 let Inst{20-16} = rt;
260 let Inst{12-11} = ac;
262 let Inst{5-0} = 0b111000;
265 // SHILO sub-class format.
266 class SHILO_R1_FMT<bits<5> op> : DSPInst {
270 let Opcode = SPECIAL3_OPCODE.V;
272 let Inst{25-20} = shift;
274 let Inst{12-11} = ac;
276 let Inst{5-0} = 0b111000;
279 class SHILO_R2_FMT<bits<5> op> : DSPInst {
283 let Opcode = SPECIAL3_OPCODE.V;
285 let Inst{25-21} = rs;
287 let Inst{12-11} = ac;
289 let Inst{5-0} = 0b111000;
292 class RDDSP_FMT<bits<5> op> : DSPInst {
296 let Opcode = SPECIAL3_OPCODE.V;
298 let Inst{25-16} = mask;
299 let Inst{15-11} = rd;
301 let Inst{5-0} = 0b111000;
304 class WRDSP_FMT<bits<5> op> : DSPInst {
308 let Opcode = SPECIAL3_OPCODE.V;
310 let Inst{25-21} = rs;
311 let Inst{20-11} = mask;
313 let Inst{5-0} = 0b111000;
316 class BPOSGE32_FMT<bits<5> op> : DSPInst {
319 let Opcode = REGIMM_OPCODE.V;
322 let Inst{20-16} = op;
323 let Inst{15-0} = offset;
326 // INSV sub-class format.
327 class INSV_FMT<bits<6> op> : DSPInst {
331 let Opcode = SPECIAL3_OPCODE.V;
333 let Inst{25-21} = rs;
334 let Inst{20-16} = rt;