1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasDSP : Predicate<"Subtarget.hasDSP()">,
11 AssemblerPredicate<"FeatureDSP">;
12 def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
13 AssemblerPredicate<"FeatureDSPR2">;
16 class Field6<bits<6> val> {
20 def SPECIAL3_OPCODE : Field6<0b011111>;
21 def REGIMM_OPCODE : Field6<0b000001>;
23 class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24 let Predicates = [HasDSP];
27 class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
28 MipsPseudo<outs, ins, "", pattern> {
29 let Predicates = [HasDSP];
32 // DPA.W.PH sub-class format.
33 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
38 let Opcode = SPECIAL3_OPCODE.V;
45 let Inst{5-0} = 0b110000;
48 // MULT sub-class format.
49 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
61 let Inst{5-0} = funct;
64 // EXTR.W sub-class format (type 1).
65 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
70 let Opcode = SPECIAL3_OPCODE.V;
72 let Inst{25-21} = shift_rs;
77 let Inst{5-0} = 0b111000;
80 // SHILO sub-class format.
81 class SHILO_R1_FMT<bits<5> op> : DSPInst {
85 let Opcode = SPECIAL3_OPCODE.V;
87 let Inst{25-20} = shift;
91 let Inst{5-0} = 0b111000;
94 class SHILO_R2_FMT<bits<5> op> : DSPInst {
98 let Opcode = SPECIAL3_OPCODE.V;
100 let Inst{25-21} = rs;
102 let Inst{12-11} = ac;
104 let Inst{5-0} = 0b111000;