1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasDSP : Predicate<"Subtarget.hasDSP()">,
11 AssemblerPredicate<"FeatureDSP">;
12 def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
13 AssemblerPredicate<"FeatureDSPR2">;
16 class Field6<bits<6> val> {
20 def SPECIAL3_OPCODE : Field6<0b011111>;
21 def REGIMM_OPCODE : Field6<0b000001>;
23 class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24 let Predicates = [HasDSP];
27 class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
28 MipsPseudo<outs, ins, "", pattern> {
29 let Predicates = [HasDSP];
32 // ADDU.QB sub-class format.
33 class ADDU_QB_FMT<bits<5> op> : DSPInst {
38 let Opcode = SPECIAL3_OPCODE.V;
44 let Inst{5-0} = 0b010000;
47 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
51 let Opcode = SPECIAL3_OPCODE.V;
57 let Inst{5-0} = 0b010000;
60 // CMPU.EQ.QB sub-class format.
61 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
65 let Opcode = SPECIAL3_OPCODE.V;
71 let Inst{5-0} = 0b010001;
74 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
79 let Opcode = SPECIAL3_OPCODE.V;
85 let Inst{5-0} = 0b010001;
88 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
93 let Opcode = SPECIAL3_OPCODE.V;
99 let Inst{5-0} = 0b010001;
102 // DPA.W.PH sub-class format.
103 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
108 let Opcode = SPECIAL3_OPCODE.V;
110 let Inst{25-21} = rs;
111 let Inst{20-16} = rt;
113 let Inst{12-11} = ac;
115 let Inst{5-0} = 0b110000;
118 // MULT sub-class format.
119 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
126 let Inst{25-21} = rs;
127 let Inst{20-16} = rt;
129 let Inst{12-11} = ac;
131 let Inst{5-0} = funct;
134 // EXTR.W sub-class format (type 1).
135 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
140 let Opcode = SPECIAL3_OPCODE.V;
142 let Inst{25-21} = shift_rs;
143 let Inst{20-16} = rt;
145 let Inst{12-11} = ac;
147 let Inst{5-0} = 0b111000;
150 // SHILO sub-class format.
151 class SHILO_R1_FMT<bits<5> op> : DSPInst {
155 let Opcode = SPECIAL3_OPCODE.V;
157 let Inst{25-20} = shift;
159 let Inst{12-11} = ac;
161 let Inst{5-0} = 0b111000;
164 class SHILO_R2_FMT<bits<5> op> : DSPInst {
168 let Opcode = SPECIAL3_OPCODE.V;
170 let Inst{25-21} = rs;
172 let Inst{12-11} = ac;
174 let Inst{5-0} = 0b111000;
177 class RDDSP_FMT<bits<5> op> : DSPInst {
181 let Opcode = SPECIAL3_OPCODE.V;
183 let Inst{25-16} = mask;
184 let Inst{15-11} = rd;
186 let Inst{5-0} = 0b111000;
189 class BPOSGE32_FMT<bits<5> op> : DSPInst {
192 let Opcode = REGIMM_OPCODE.V;
195 let Inst{20-16} = op;
196 let Inst{15-0} = offset;