lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  24 def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
  25 def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  26
  27 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  28   SDNode<!strconcat("MipsISD::", Opc), Prof,
  29          [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
  30
  31 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  32   SDNode<!strconcat("MipsISD::", Opc), Prof,
  33          [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
  34
  35 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  36 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  37 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  38 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  39 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  40 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  41
  42 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  43 def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>;
  44
  45 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  46 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  47 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  48 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  49 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  50
  51 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  52 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  53 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  54 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  55 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  56 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  58 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  59
  60 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  61 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  62 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  63 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  64 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  65 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  66 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  69
  70 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  71 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  72 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  73 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  74 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  75 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  76
  77 // Flags.
  78 class UseAC {
  79   list<Register> Uses = [AC0];
  80 }
  81
  82 class UseDSPCtrl {
  83   list<Register> Uses = [DSPCtrl];
  84 }
  85
  86 class ClearDefs {
  87   list<Register> Defs = [];
  88 }
  89
  90 // Instruction encoding.
  91 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  92 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  93 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  94 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  95 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
  96 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
  97 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
  98 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
  99 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 100 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 101 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 102 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 103 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 104 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 105 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 106 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 107 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 108 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 109 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 110 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 111 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 112 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 113 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 114 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 115 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 116 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 117 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 118 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 119 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 120 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 121 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 122 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 123 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 124 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 125 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 126 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 127 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 128 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 129 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 130 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 131 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 132 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 133 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 134 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 135 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 136 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 137 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 138 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 139 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 140 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 141 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 142 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 143 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 144 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 145 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 146 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 147 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 148 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 149 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 150 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 151 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 152 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 153 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 154 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 155 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 156 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 157 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 158 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 159 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 160 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 161 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 162 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 163 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 164 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 165 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 166 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 167 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 168 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 169 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 170 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 171 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 172 class REPL_QB_ENC : REPL_FMT<0b00010>;
 173 class REPL_PH_ENC : REPL_FMT<0b01010>;
 174 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 175 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 176 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 177 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 178 class LWX_ENC : LX_FMT<0b00000>;
 179 class LHX_ENC : LX_FMT<0b00100>;
 180 class LBUX_ENC : LX_FMT<0b00110>;
 181 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 182 class INSV_ENC : INSV_FMT<0b001100>;
 183
 184 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 185 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 186 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 187 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 188 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 189 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 190 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 191 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 192 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 193 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 194 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 195 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 196 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 197 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 198 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 199
 200 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 201 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 202 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 203 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 204 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 205 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 206 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 207 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 208 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 209 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 210 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 211 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 212 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 213 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 214 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 215 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 216 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 217 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 218 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 219 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 220 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 221 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 222 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 223 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 224 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 225 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 226 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 227 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 228 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 229 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 230 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 231 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 232 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 233 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 234 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 235 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 236 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 237 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 238 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 239 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 240 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 241 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 242 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 243 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 244 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 245 class APPEND_ENC : APPEND_FMT<0b00000>;
 246 class BALIGN_ENC : APPEND_FMT<0b10000>;
 247 class PREPEND_ENC : APPEND_FMT<0b00001>;
 248
 249 // Instruction desc.
 250 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 251                         InstrItinClass itin, RegisterClass RCD,
 252                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 253   dag OutOperandList = (outs RCD:$rd);
 254   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 255   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 256   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 257   InstrItinClass Itinerary = itin;
 258   list<Register> Defs = [DSPCtrl];
 259 }
 260
 261 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 262                            InstrItinClass itin, RegisterClass RCD,
 263                            RegisterClass RCS = RCD> {
 264   dag OutOperandList = (outs RCD:$rd);
 265   dag InOperandList = (ins RCS:$rs);
 266   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 267   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 268   InstrItinClass Itinerary = itin;
 269   list<Register> Defs = [DSPCtrl];
 270 }
 271
 272 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 273                              InstrItinClass itin, RegisterClass RCS,
 274                              RegisterClass RCT = RCS> {
 275   dag OutOperandList = (outs);
 276   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 277   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 278   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 279   InstrItinClass Itinerary = itin;
 280   list<Register> Defs = [DSPCtrl];
 281 }
 282
 283 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 284                              InstrItinClass itin, RegisterClass RCD,
 285                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 286   dag OutOperandList = (outs RCD:$rd);
 287   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 288   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 289   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 290   InstrItinClass Itinerary = itin;
 291   list<Register> Defs = [DSPCtrl];
 292 }
 293
 294 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 295                                InstrItinClass itin, RegisterClass RCT,
 296                                RegisterClass RCS = RCT> {
 297   dag OutOperandList = (outs RCT:$rt);
 298   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 299   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 300   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 301   InstrItinClass Itinerary = itin;
 302   list<Register> Defs = [DSPCtrl];
 303   string Constraints = "$src = $rt";
 304 }
 305
 306 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 307                              InstrItinClass itin, RegisterClass RCD,
 308                              RegisterClass RCT = RCD> {
 309   dag OutOperandList = (outs RCD:$rd);
 310   dag InOperandList = (ins RCT:$rt);
 311   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 312   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 313   InstrItinClass Itinerary = itin;
 314   list<Register> Defs = [DSPCtrl];
 315 }
 316
 317 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 318                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 319   dag OutOperandList = (outs RC:$rd);
 320   dag InOperandList = (ins uimm16:$imm);
 321   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 322   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 323   InstrItinClass Itinerary = itin;
 324   list<Register> Defs = [DSPCtrl];
 325 }
 326
 327 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 328                            InstrItinClass itin, RegisterClass RC> {
 329   dag OutOperandList = (outs RC:$rd);
 330   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 331   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 332   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 333   InstrItinClass Itinerary = itin;
 334   list<Register> Defs = [DSPCtrl];
 335 }
 336
 337 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 338                            SDPatternOperator ImmPat, InstrItinClass itin,
 339                            RegisterClass RC> {
 340   dag OutOperandList = (outs RC:$rd);
 341   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 342   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 343   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 344   InstrItinClass Itinerary = itin;
 345   list<Register> Defs = [DSPCtrl];
 346 }
 347
 348 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 349                    InstrItinClass itin> {
 350   dag OutOperandList = (outs CPURegs:$rd);
 351   dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
 352   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 353   list<dag> Pattern = [(set CPURegs:$rd,
 354                        (OpNode CPURegs:$base, CPURegs:$index))];
 355   InstrItinClass Itinerary = itin;
 356   list<Register> Defs = [DSPCtrl];
 357   bit mayLoad = 1;
 358 }
 359
 360 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 361                          InstrItinClass itin, RegisterClass RCD,
 362                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 363   dag OutOperandList = (outs RCD:$rd);
 364   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 365   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 366   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 367   InstrItinClass Itinerary = itin;
 368   list<Register> Defs = [DSPCtrl];
 369 }
 370
 371 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 372                        SDPatternOperator ImmOp, InstrItinClass itin> {
 373   dag OutOperandList = (outs CPURegs:$rt);
 374   dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
 375   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 376   list<dag> Pattern =  [(set CPURegs:$rt,
 377                         (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
 378   InstrItinClass Itinerary = itin;
 379   list<Register> Defs = [DSPCtrl];
 380   string Constraints = "$src = $rt";
 381 }
 382
 383 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 384                               InstrItinClass itin> {
 385   dag OutOperandList = (outs CPURegs:$rt);
 386   dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
 387   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 388   InstrItinClass Itinerary = itin;
 389   list<Register> Defs = [DSPCtrl];
 390 }
 391
 392 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 393                               InstrItinClass itin> {
 394   dag OutOperandList = (outs CPURegs:$rt);
 395   dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
 396   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 397   InstrItinClass Itinerary = itin;
 398   list<Register> Defs = [DSPCtrl];
 399 }
 400
 401 class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 402                            Instruction realinst> :
 403   PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>,
 404   PseudoInstExpansion<(realinst AC0, simm16:$shift)> {
 405   list<Register> Defs = [DSPCtrl, AC0];
 406   list<Register> Uses = [AC0];
 407   InstrItinClass Itinerary = itin;
 408 }
 409
 410 class SHILO_R1_DESC_BASE<string instr_asm> {
 411   dag OutOperandList = (outs ACRegs:$ac);
 412   dag InOperandList = (ins simm16:$shift);
 413   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 414 }
 415
 416 class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 417                            Instruction realinst> :
 418   PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>,
 419   PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> {
 420   list<Register> Defs = [DSPCtrl, AC0];
 421   list<Register> Uses = [AC0];
 422   InstrItinClass Itinerary = itin;
 423 }
 424
 425 class SHILO_R2_DESC_BASE<string instr_asm> {
 426   dag OutOperandList = (outs ACRegs:$ac);
 427   dag InOperandList = (ins CPURegs:$rs);
 428   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 429 }
 430
 431 class MTHLIP_DESC_BASE<string instr_asm> {
 432   dag OutOperandList = (outs ACRegs:$ac);
 433   dag InOperandList = (ins CPURegs:$rs);
 434   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 435 }
 436
 437 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 438                       InstrItinClass itin> {
 439   dag OutOperandList = (outs CPURegs:$rd);
 440   dag InOperandList = (ins uimm16:$mask);
 441   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 442   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 443   InstrItinClass Itinerary = itin;
 444   list<Register> Uses = [DSPCtrl];
 445 }
 446
 447 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 448                       InstrItinClass itin> {
 449   dag OutOperandList = (outs);
 450   dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
 451   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 452   list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
 453   InstrItinClass Itinerary = itin;
 454   list<Register> Defs = [DSPCtrl];
 455 }
 456
 457 class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 458                            Instruction realinst> :
 459   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 460             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 461   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 462   list<Register> Defs = [DSPCtrl, AC0];
 463   list<Register> Uses = [AC0];
 464   InstrItinClass Itinerary = itin;
 465 }
 466
 467 class DPA_W_PH_DESC_BASE<string instr_asm> {
 468   dag OutOperandList = (outs ACRegs:$ac);
 469   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 470   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 471 }
 472
 473 class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 474                        Instruction realinst> :
 475   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 476             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 477   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 478   list<Register> Defs = [DSPCtrl, AC0];
 479   InstrItinClass Itinerary = itin;
 480 }
 481
 482 class MULT_DESC_BASE<string instr_asm> {
 483   dag OutOperandList = (outs ACRegs:$ac);
 484   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 485   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 486 }
 487
 488 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 489   MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> {
 490   list<Register> Uses = [DSPCtrl];
 491   bit usesCustomInserter = 1;
 492 }
 493
 494 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 495   dag OutOperandList = (outs);
 496   dag InOperandList = (ins brtarget:$offset);
 497   string AsmString = !strconcat(instr_asm, "\t$offset");
 498   InstrItinClass Itinerary = itin;
 499   list<Register> Uses = [DSPCtrl];
 500   bit isBranch = 1;
 501   bit isTerminator = 1;
 502   bit hasDelaySlot = 1;
 503 }
 504
 505 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 506                      InstrItinClass itin> {
 507   dag OutOperandList = (outs CPURegs:$rt);
 508   dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
 509   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 510   list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
 511   InstrItinClass Itinerary = itin;
 512   list<Register> Uses = [DSPCtrl];
 513   string Constraints = "$src = $rt";
 514 }
 515
 516 //===----------------------------------------------------------------------===//
 517 // MIPS DSP Rev 1
 518 //===----------------------------------------------------------------------===//
 519
 520 // Addition/subtraction
 521 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary,
 522                                        DSPRegs, DSPRegs>, IsCommutable;
 523
 524 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 525                                          NoItinerary, DSPRegs, DSPRegs>,
 526                        IsCommutable;
 527
 528 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary,
 529                                        DSPRegs, DSPRegs>;
 530
 531 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 532                                          NoItinerary, DSPRegs, DSPRegs>;
 533
 534 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary,
 535                                        DSPRegs, DSPRegs>, IsCommutable;
 536
 537 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 538                                          NoItinerary, DSPRegs, DSPRegs>,
 539                        IsCommutable;
 540
 541 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary,
 542                                        DSPRegs, DSPRegs>;
 543
 544 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 545                                          NoItinerary, DSPRegs, DSPRegs>;
 546
 547 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 548                                         NoItinerary, CPURegs, CPURegs>,
 549                       IsCommutable;
 550
 551 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 552                                         NoItinerary, CPURegs, CPURegs>;
 553
 554 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
 555                                      CPURegs, CPURegs>, IsCommutable;
 556
 557 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
 558                                      CPURegs, CPURegs>,
 559                    IsCommutable, UseDSPCtrl;
 560
 561 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 562                                       CPURegs, CPURegs>, ClearDefs;
 563
 564 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 565                                              NoItinerary, CPURegs, DSPRegs>,
 566                         ClearDefs;
 567
 568 // Absolute value
 569 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 570                                               NoItinerary, DSPRegs>;
 571
 572 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 573                                              NoItinerary, CPURegs>;
 574
 575 // Precision reduce/expand
 576 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 577                                                  int_mips_precrq_qb_ph,
 578                                                  NoItinerary, DSPRegs, DSPRegs>,
 579                           ClearDefs;
 580
 581 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 582                                                 int_mips_precrq_ph_w,
 583                                                 NoItinerary, DSPRegs, CPURegs>,
 584                          ClearDefs;
 585
 586 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 587                                                    int_mips_precrq_rs_ph_w,
 588                                                    NoItinerary, DSPRegs,
 589                                                    CPURegs>;
 590
 591 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 592                                                     int_mips_precrqu_s_qb_ph,
 593                                                     NoItinerary, DSPRegs,
 594                                                     DSPRegs>;
 595
 596 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 597                                                  int_mips_preceq_w_phl,
 598                                                  NoItinerary, CPURegs, DSPRegs>,
 599                           ClearDefs;
 600
 601 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 602                                                  int_mips_preceq_w_phr,
 603                                                  NoItinerary, CPURegs, DSPRegs>,
 604                           ClearDefs;
 605
 606 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 607                                                    int_mips_precequ_ph_qbl,
 608                                                    NoItinerary, DSPRegs>,
 609                             ClearDefs;
 610
 611 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 612                                                    int_mips_precequ_ph_qbr,
 613                                                    NoItinerary, DSPRegs>,
 614                             ClearDefs;
 615
 616 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 617                                                     int_mips_precequ_ph_qbla,
 618                                                     NoItinerary, DSPRegs>,
 619                              ClearDefs;
 620
 621 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 622                                                     int_mips_precequ_ph_qbra,
 623                                                     NoItinerary, DSPRegs>,
 624                              ClearDefs;
 625
 626 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 627                                                   int_mips_preceu_ph_qbl,
 628                                                   NoItinerary, DSPRegs>,
 629                            ClearDefs;
 630
 631 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 632                                                   int_mips_preceu_ph_qbr,
 633                                                   NoItinerary, DSPRegs>,
 634                            ClearDefs;
 635
 636 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 637                                                    int_mips_preceu_ph_qbla,
 638                                                    NoItinerary, DSPRegs>,
 639                             ClearDefs;
 640
 641 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 642                                                    int_mips_preceu_ph_qbra,
 643                                                    NoItinerary, DSPRegs>,
 644                             ClearDefs;
 645
 646 // Shift
 647 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
 648                                           NoItinerary, DSPRegs>;
 649
 650 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 651                                            NoItinerary, DSPRegs>;
 652
 653 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
 654                                           NoItinerary, DSPRegs>, ClearDefs;
 655
 656 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 657                                            NoItinerary, DSPRegs>, ClearDefs;
 658
 659 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
 660                                           NoItinerary, DSPRegs>;
 661
 662 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 663                                            NoItinerary, DSPRegs>;
 664
 665 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 666                                             immZExt4, NoItinerary, DSPRegs>;
 667
 668 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 669                                              NoItinerary, DSPRegs>;
 670
 671 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
 672                                           NoItinerary, DSPRegs>, ClearDefs;
 673
 674 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 675                                            NoItinerary, DSPRegs>, ClearDefs;
 676
 677 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 678                                             immZExt4, NoItinerary, DSPRegs>,
 679                        ClearDefs;
 680
 681 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 682                                              NoItinerary, DSPRegs>, ClearDefs;
 683
 684 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 685                                            immZExt5, NoItinerary, CPURegs>;
 686
 687 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 688                                             NoItinerary, CPURegs>;
 689
 690 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 691                                            immZExt5, NoItinerary, CPURegs>,
 692                       ClearDefs;
 693
 694 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 695                                             NoItinerary, CPURegs>;
 696
 697 // Multiplication
 698 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 699                                               int_mips_muleu_s_ph_qbl,
 700                                               NoItinerary, DSPRegs, DSPRegs>;
 701
 702 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 703                                               int_mips_muleu_s_ph_qbr,
 704                                               NoItinerary, DSPRegs, DSPRegs>;
 705
 706 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 707                                              int_mips_muleq_s_w_phl,
 708                                              NoItinerary, CPURegs, DSPRegs>,
 709                            IsCommutable;
 710
 711 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 712                                              int_mips_muleq_s_w_phr,
 713                                              NoItinerary, CPURegs, DSPRegs>,
 714                            IsCommutable;
 715
 716 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 717                                           NoItinerary, DSPRegs, DSPRegs>,
 718                         IsCommutable;
 719
 720 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
 721
 722 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
 723
 724 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">;
 725
 726 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">;
 727
 728 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">;
 729
 730 // Dot product with accumulate/subtract
 731 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">;
 732
 733 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">;
 734
 735 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">;
 736
 737 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">;
 738
 739 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">;
 740
 741 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">;
 742
 743 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">;
 744
 745 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">;
 746
 747 class MULT_DSP_DESC : MULT_DESC_BASE<"mult">;
 748
 749 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">;
 750
 751 class MADD_DSP_DESC : MULT_DESC_BASE<"madd">;
 752
 753 class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">;
 754
 755 class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
 756
 757 class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
 758
 759 // Comparison
 760 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 761                                                int_mips_cmpu_eq_qb, NoItinerary,
 762                                                DSPRegs>, IsCommutable;
 763
 764 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 765                                                int_mips_cmpu_lt_qb, NoItinerary,
 766                                                DSPRegs>, IsCommutable;
 767
 768 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 769                                                int_mips_cmpu_le_qb, NoItinerary,
 770                                                DSPRegs>, IsCommutable;
 771
 772 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 773                                                 int_mips_cmpgu_eq_qb,
 774                                                 NoItinerary, CPURegs, DSPRegs>,
 775                          IsCommutable;
 776
 777 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 778                                                 int_mips_cmpgu_lt_qb,
 779                                                 NoItinerary, CPURegs, DSPRegs>,
 780                          IsCommutable;
 781
 782 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 783                                                 int_mips_cmpgu_le_qb,
 784                                                 NoItinerary, CPURegs, DSPRegs>,
 785                          IsCommutable;
 786
 787 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 788                                               NoItinerary, DSPRegs>,
 789                        IsCommutable;
 790
 791 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 792                                               NoItinerary, DSPRegs>,
 793                        IsCommutable;
 794
 795 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 796                                               NoItinerary, DSPRegs>,
 797                        IsCommutable;
 798
 799 // Misc
 800 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 801                                            NoItinerary, CPURegs>, ClearDefs;
 802
 803 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 804                                               NoItinerary, DSPRegs, DSPRegs>,
 805                        ClearDefs;
 806
 807 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 808                                     NoItinerary, DSPRegs>, ClearDefs;
 809
 810 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 811                                     NoItinerary, DSPRegs>, ClearDefs;
 812
 813 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 814                                              NoItinerary, DSPRegs, CPURegs>,
 815                       ClearDefs;
 816
 817 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 818                                              NoItinerary, DSPRegs, CPURegs>,
 819                       ClearDefs;
 820
 821 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 822                                             NoItinerary, DSPRegs, DSPRegs>,
 823                      ClearDefs, UseDSPCtrl;
 824
 825 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 826                                             NoItinerary, DSPRegs, DSPRegs>,
 827                      ClearDefs, UseDSPCtrl;
 828
 829 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
 830
 831 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
 832
 833 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
 834
 835 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 836
 837 // Extr
 838 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 839
 840 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 841
 842 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 843
 844 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 845                                              NoItinerary>;
 846
 847 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 848
 849 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 850                                              NoItinerary>;
 851
 852 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 853                                               NoItinerary>;
 854
 855 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 856                                                NoItinerary>;
 857
 858 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 859                                                NoItinerary>;
 860
 861 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 862                                                 NoItinerary>;
 863
 864 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 865                                               NoItinerary>;
 866
 867 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 868                                                NoItinerary>;
 869
 870 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">;
 871
 872 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
 873
 874 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
 875
 876 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 877
 878 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 879
 880 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
 881
 882 //===----------------------------------------------------------------------===//
 883 // MIPS DSP Rev 2
 884 // Addition/subtraction
 885 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 886                                        DSPRegs, DSPRegs>, IsCommutable;
 887
 888 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 889                                          NoItinerary, DSPRegs, DSPRegs>,
 890                        IsCommutable;
 891
 892 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 893                                        DSPRegs, DSPRegs>;
 894
 895 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 896                                          NoItinerary, DSPRegs, DSPRegs>;
 897
 898 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 899                                          NoItinerary, DSPRegs>,
 900                       ClearDefs, IsCommutable;
 901
 902 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 903                                            NoItinerary, DSPRegs>,
 904                         ClearDefs, IsCommutable;
 905
 906 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 907                                          NoItinerary, DSPRegs>, ClearDefs;
 908
 909 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 910                                            NoItinerary, DSPRegs>, ClearDefs;
 911
 912 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 913                                          NoItinerary, DSPRegs>,
 914                       ClearDefs, IsCommutable;
 915
 916 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 917                                            NoItinerary, DSPRegs>,
 918                         ClearDefs, IsCommutable;
 919
 920 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 921                                          NoItinerary, DSPRegs>, ClearDefs;
 922
 923 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 924                                            NoItinerary, DSPRegs>, ClearDefs;
 925
 926 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 927                                         NoItinerary, CPURegs>,
 928                      ClearDefs, IsCommutable;
 929
 930 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 931                                           NoItinerary, CPURegs>,
 932                        ClearDefs, IsCommutable;
 933
 934 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 935                                         NoItinerary, CPURegs>, ClearDefs;
 936
 937 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 938                                           NoItinerary, CPURegs>, ClearDefs;
 939
 940 // Comparison
 941 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 942                                                  int_mips_cmpgdu_eq_qb,
 943                                                  NoItinerary, CPURegs, DSPRegs>,
 944                           IsCommutable;
 945
 946 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 947                                                  int_mips_cmpgdu_lt_qb,
 948                                                  NoItinerary, CPURegs, DSPRegs>,
 949                           IsCommutable;
 950
 951 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 952                                                  int_mips_cmpgdu_le_qb,
 953                                                  NoItinerary, CPURegs, DSPRegs>,
 954                           IsCommutable;
 955
 956 // Absolute
 957 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 958                                               NoItinerary, DSPRegs>;
 959
 960 // Multiplication
 961 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary,
 962                                        DSPRegs>, IsCommutable;
 963
 964 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 965                                          NoItinerary, DSPRegs>, IsCommutable;
 966
 967 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 968                                          NoItinerary, CPURegs>, IsCommutable;
 969
 970 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 971                                           NoItinerary, CPURegs>, IsCommutable;
 972
 973 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 974                                          NoItinerary, DSPRegs, DSPRegs>,
 975                        IsCommutable;
 976
 977 // Dot product with accumulate/subtract
 978 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
 979
 980 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">;
 981
 982 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">;
 983
 984 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">;
 985
 986 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">;
 987
 988 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">;
 989
 990 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">;
 991
 992 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
 993
 994 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
 995
 996 // Precision reduce/expand
 997 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
 998                                                 int_mips_precr_qb_ph,
 999                                                 NoItinerary, DSPRegs, DSPRegs>;
1000
1001 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1002                                                      int_mips_precr_sra_ph_w,
1003                                                      NoItinerary, DSPRegs,
1004                                                      CPURegs>, ClearDefs;
1005
1006 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1007                                                       int_mips_precr_sra_r_ph_w,
1008                                                        NoItinerary, DSPRegs,
1009                                                        CPURegs>, ClearDefs;
1010
1011 // Shift
1012 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
1013                                           NoItinerary, DSPRegs>, ClearDefs;
1014
1015 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1016                                            NoItinerary, DSPRegs>, ClearDefs;
1017
1018 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1019                                             immZExt3, NoItinerary, DSPRegs>,
1020                        ClearDefs;
1021
1022 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1023                                              NoItinerary, DSPRegs>, ClearDefs;
1024
1025 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
1026                                           NoItinerary, DSPRegs>, ClearDefs;
1027
1028 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1029                                            NoItinerary, DSPRegs>, ClearDefs;
1030
1031 // Misc
1032 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1033                                      NoItinerary>, ClearDefs;
1034
1035 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1036                                      NoItinerary>, ClearDefs;
1037
1038 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1039                                       NoItinerary>, ClearDefs;
1040
1041 // Pseudos.
1042 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
1043
1044 // Instruction defs.
1045 // MIPS DSP Rev 1
1046 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1047 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1048 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1049 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1050 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1051 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1052 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1053 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1054 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1055 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1056 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1057 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1058 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1059 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1060 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1061 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1062 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1063 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1064 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1065 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1066 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1067 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1068 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1069 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1070 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1071 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1072 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1073 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1074 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1075 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1076 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1077 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1078 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1079 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1080 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1081 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1082 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1083 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1084 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1085 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1086 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1087 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1088 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1089 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1090 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1091 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1092 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1093 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1094 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1095 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1096 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1097 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1098 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1099 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1100 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1101 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1102 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1103 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1104 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1105 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1106 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1107 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1108 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1109 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1110 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1111 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1112 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1113 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1114 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1115 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1116 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1117 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1118 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1119 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1120 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1121 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1122 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1123 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1124 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1125 def BITREV : BITREV_ENC, BITREV_DESC;
1126 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1127 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1128 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1129 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1130 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1131 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1132 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1133 def LWX : LWX_ENC, LWX_DESC;
1134 def LHX : LHX_ENC, LHX_DESC;
1135 def LBUX : LBUX_ENC, LBUX_DESC;
1136 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1137 def INSV : INSV_ENC, INSV_DESC;
1138 def EXTP : EXTP_ENC, EXTP_DESC;
1139 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1140 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1141 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1142 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1143 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1144 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1145 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1146 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1147 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1148 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1149 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1150 def SHILO : SHILO_ENC, SHILO_DESC;
1151 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1152 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1153 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1154 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1155
1156 // MIPS DSP Rev 2
1157 let Predicates = [HasDSPR2] in {
1158
1159 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1160 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1161 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1162 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1163 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1164 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1165 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1166 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1167 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1168 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1169 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1170 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1171 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1172 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1173 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1174 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1175 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1176 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1177 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1178 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1179 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1180 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1181 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1182 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1183 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1184 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1185 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1186 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1187 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1188 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1189 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1190 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1191 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1192 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1193 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1194 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1195 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1196 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1197 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1198 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1199 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1200 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1201 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1202 def APPEND : APPEND_ENC, APPEND_DESC;
1203 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1204 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1205
1206 }
1207
1208 // Pseudos.
1209 def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary,
1210                                                 MULSAQ_S_W_PH>;
1211 def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary,
1212                                               MAQ_S_W_PHL>;
1213 def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary,
1214                                               MAQ_S_W_PHR>;
1215 def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary,
1216                                                MAQ_SA_W_PHL>;
1217 def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary,
1218                                                MAQ_SA_W_PHR>;
1219 def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary,
1220                                              DPAU_H_QBL>;
1221 def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary,
1222                                              DPAU_H_QBR>;
1223 def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary,
1224                                              DPSU_H_QBL>;
1225 def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary,
1226                                              DPSU_H_QBR>;
1227 def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary,
1228                                               DPAQ_S_W_PH>;
1229 def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary,
1230                                               DPSQ_S_W_PH>;
1231 def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary,
1232                                               DPAQ_SA_L_W>;
1233 def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary,
1234                                               DPSQ_SA_L_W>;
1235
1236 def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>,
1237                       IsCommutable;
1238 def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>,
1239                        IsCommutable;
1240 def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>,
1241                       IsCommutable, UseAC;
1242 def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>,
1243                        IsCommutable, UseAC;
1244 def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>,
1245                       UseAC;
1246 def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>,
1247                        UseAC;
1248
1249 def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>;
1250 def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>;
1251 def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>;
1252
1253 let Predicates = [HasDSPR2] in {
1254
1255 def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>;
1256 def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>;
1257 def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary,
1258                                                DPAQX_S_W_PH>;
1259 def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary,
1260                                                 DPAQX_SA_W_PH>;
1261 def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary,
1262                                             DPAX_W_PH>;
1263 def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary,
1264                                             DPSX_W_PH>;
1265 def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary,
1266                                                DPSQX_S_W_PH>;
1267 def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary,
1268                                                 DPSQX_SA_W_PH>;
1269 def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
1270                                              MULSA_W_PH>;
1271
1272 }
1273
1274 // Patterns.
1275 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1276   Pat<pattern, result>, Requires<[pred]>;
1277
1278 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1279                     RegisterClass SrcRC> :
1280    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1281           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1282
1283 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1284 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1285 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1286 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1287
1288 def : DSPPat<(v2i16 (load addr:$a)),
1289              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1290 def : DSPPat<(v4i8 (load addr:$a)),
1291              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1292 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1293              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1294 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1295              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1296
1297 // Extr patterns.
1298 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1299   DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
1300
1301 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1302   DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
1303
1304 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1305 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1306 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1307 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1308 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1309 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1310 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1311 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1312 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1313 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1314 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1315 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;