1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips DSP ASE instructions.
12 //===----------------------------------------------------------------------===//
15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
22 // Mips-specific dsp nodes
23 def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
24 def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
25 def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
27 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
28 SDNode<!strconcat("MipsISD::", Opc), Prof,
29 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
31 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
32 SDNode<!strconcat("MipsISD::", Opc), Prof,
33 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
35 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
36 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
37 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
38 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
39 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
40 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
42 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
43 def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>;
45 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
46 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
47 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
48 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
49 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
51 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
52 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
53 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
54 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
55 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
56 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
57 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
58 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
60 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
61 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
62 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
63 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
64 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
65 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
66 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
67 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
68 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
70 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
71 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
72 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
73 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
74 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
75 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
83 list<Register> Uses = [AC0];
87 list<Register> Uses = [DSPCtrl];
91 list<Register> Defs = [];
94 // Instruction encoding.
95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
109 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
110 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
111 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
112 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
113 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
114 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
115 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
116 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
117 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
118 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
119 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
120 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
121 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
122 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
123 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
124 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
125 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
126 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
127 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
128 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
129 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
130 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
131 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
132 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
133 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
135 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
136 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
137 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
138 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
139 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
140 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
141 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
142 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
143 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
144 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
145 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
146 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
147 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
148 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
149 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
151 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
152 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
153 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
154 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
155 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
156 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
157 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
158 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
159 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
160 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
161 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
162 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
163 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
164 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
167 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
168 InstrItinClass itin, RegisterClass RCD,
169 RegisterClass RCS, RegisterClass RCT = RCS> {
170 dag OutOperandList = (outs RCD:$rd);
171 dag InOperandList = (ins RCS:$rs, RCT:$rt);
172 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
173 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
174 InstrItinClass Itinerary = itin;
175 list<Register> Defs = [DSPCtrl];
178 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
179 InstrItinClass itin, RegisterClass RCD,
180 RegisterClass RCS = RCD> {
181 dag OutOperandList = (outs RCD:$rd);
182 dag InOperandList = (ins RCS:$rs);
183 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
184 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
185 InstrItinClass Itinerary = itin;
186 list<Register> Defs = [DSPCtrl];
189 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
190 InstrItinClass itin> {
191 dag OutOperandList = (outs CPURegs:$rt);
192 dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
193 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
194 InstrItinClass Itinerary = itin;
195 list<Register> Defs = [DSPCtrl];
198 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
199 InstrItinClass itin> {
200 dag OutOperandList = (outs CPURegs:$rt);
201 dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
202 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
203 InstrItinClass Itinerary = itin;
204 list<Register> Defs = [DSPCtrl];
207 class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
208 Instruction realinst> :
209 PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>,
210 PseudoInstExpansion<(realinst AC0, simm16:$shift)> {
211 list<Register> Defs = [DSPCtrl, AC0];
212 list<Register> Uses = [AC0];
213 InstrItinClass Itinerary = itin;
216 class SHILO_R1_DESC_BASE<string instr_asm> {
217 dag OutOperandList = (outs ACRegs:$ac);
218 dag InOperandList = (ins simm16:$shift);
219 string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
222 class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
223 Instruction realinst> :
224 PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>,
225 PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> {
226 list<Register> Defs = [DSPCtrl, AC0];
227 list<Register> Uses = [AC0];
228 InstrItinClass Itinerary = itin;
231 class SHILO_R2_DESC_BASE<string instr_asm> {
232 dag OutOperandList = (outs ACRegs:$ac);
233 dag InOperandList = (ins CPURegs:$rs);
234 string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
237 class MTHLIP_DESC_BASE<string instr_asm> {
238 dag OutOperandList = (outs ACRegs:$ac);
239 dag InOperandList = (ins CPURegs:$rs);
240 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
243 class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
244 Instruction realinst> :
245 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
246 [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
247 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
248 list<Register> Defs = [DSPCtrl, AC0];
249 list<Register> Uses = [AC0];
250 InstrItinClass Itinerary = itin;
253 class DPA_W_PH_DESC_BASE<string instr_asm> {
254 dag OutOperandList = (outs ACRegs:$ac);
255 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
256 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
259 class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
260 Instruction realinst> :
261 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
262 [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
263 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
264 list<Register> Defs = [DSPCtrl, AC0];
265 InstrItinClass Itinerary = itin;
268 class MULT_DESC_BASE<string instr_asm> {
269 dag OutOperandList = (outs ACRegs:$ac);
270 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
271 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
274 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
275 MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> {
276 list<Register> Uses = [DSPCtrl];
277 bit usesCustomInserter = 1;
280 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
281 dag OutOperandList = (outs);
282 dag InOperandList = (ins brtarget:$offset);
283 string AsmString = !strconcat(instr_asm, "\t$offset");
284 InstrItinClass Itinerary = itin;
285 list<Register> Uses = [DSPCtrl];
287 bit isTerminator = 1;
288 bit hasDelaySlot = 1;
291 //===----------------------------------------------------------------------===//
293 //===----------------------------------------------------------------------===//
295 // Addition/subtraction
296 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary,
297 DSPRegs, DSPRegs>, IsCommutable;
299 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
300 NoItinerary, DSPRegs, DSPRegs>,
303 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary,
306 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
307 NoItinerary, DSPRegs, DSPRegs>;
309 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary,
310 DSPRegs, DSPRegs>, IsCommutable;
312 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
313 NoItinerary, DSPRegs, DSPRegs>,
316 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary,
319 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
320 NoItinerary, DSPRegs, DSPRegs>;
322 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
323 NoItinerary, CPURegs, CPURegs>,
326 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
327 NoItinerary, CPURegs, CPURegs>;
329 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
330 CPURegs, CPURegs>, IsCommutable;
332 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
334 IsCommutable, UseDSPCtrl;
336 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
337 CPURegs, CPURegs>, ClearDefs;
339 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
340 NoItinerary, CPURegs, DSPRegs>,
344 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
345 int_mips_muleu_s_ph_qbl,
346 NoItinerary, DSPRegs, DSPRegs>;
348 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
349 int_mips_muleu_s_ph_qbr,
350 NoItinerary, DSPRegs, DSPRegs>;
352 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
353 int_mips_muleq_s_w_phl,
354 NoItinerary, CPURegs, DSPRegs>,
357 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
358 int_mips_muleq_s_w_phr,
359 NoItinerary, CPURegs, DSPRegs>,
362 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
363 NoItinerary, DSPRegs, DSPRegs>,
366 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
368 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
370 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">;
372 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">;
374 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">;
376 // Dot product with accumulate/subtract
377 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">;
379 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">;
381 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">;
383 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">;
385 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">;
387 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">;
389 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">;
391 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">;
393 class MULT_DSP_DESC : MULT_DESC_BASE<"mult">;
395 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">;
397 class MADD_DSP_DESC : MULT_DESC_BASE<"madd">;
399 class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">;
401 class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
403 class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
406 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
409 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
411 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
413 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
415 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
418 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
420 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
423 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
426 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
429 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
432 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
435 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
438 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
441 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">;
443 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
445 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
447 //===----------------------------------------------------------------------===//
449 // Addition/subtraction
450 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
451 DSPRegs, DSPRegs>, IsCommutable;
453 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
454 NoItinerary, DSPRegs, DSPRegs>,
457 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
460 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
461 NoItinerary, DSPRegs, DSPRegs>;
464 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
465 NoItinerary, DSPRegs, DSPRegs>,
468 // Dot product with accumulate/subtract
469 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
471 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">;
473 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">;
475 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">;
477 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">;
479 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">;
481 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">;
483 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
485 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
488 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
492 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
493 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
494 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
495 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
496 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
497 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
498 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
499 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
500 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
501 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
502 def ADDSC : ADDSC_ENC, ADDSC_DESC;
503 def ADDWC : ADDWC_ENC, ADDWC_DESC;
504 def MODSUB : MODSUB_ENC, MODSUB_DESC;
505 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
506 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
507 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
508 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
509 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
510 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
511 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
512 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
513 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
514 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
515 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
516 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
517 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
518 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
519 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
520 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
521 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
522 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
523 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
524 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
525 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
526 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
527 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
528 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
529 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
530 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
531 def EXTP : EXTP_ENC, EXTP_DESC;
532 def EXTPV : EXTPV_ENC, EXTPV_DESC;
533 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
534 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
535 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
536 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
537 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
538 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
539 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
540 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
541 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
542 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
543 def SHILO : SHILO_ENC, SHILO_DESC;
544 def SHILOV : SHILOV_ENC, SHILOV_DESC;
545 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
548 let Predicates = [HasDSPR2] in {
550 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
551 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
552 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
553 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
554 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
555 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
556 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
557 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
558 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
559 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
560 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
561 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
562 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
563 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
568 def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary,
570 def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary,
572 def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary,
574 def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary,
576 def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary,
578 def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary,
580 def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary,
582 def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary,
584 def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary,
586 def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary,
588 def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary,
590 def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary,
592 def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary,
595 def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>,
597 def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>,
599 def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>,
601 def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>,
603 def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>,
605 def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>,
608 def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>;
609 def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>;
610 def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>;
612 let Predicates = [HasDSPR2] in {
614 def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>;
615 def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>;
616 def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary,
618 def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary,
620 def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary,
622 def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary,
624 def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary,
626 def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary,
628 def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
634 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
635 Pat<pattern, result>, Requires<[pred]>;
637 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
638 RegisterClass SrcRC> :
639 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
640 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
642 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
643 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
644 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
645 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
647 def : DSPPat<(v2i16 (load addr:$a)),
648 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
649 def : DSPPat<(v4i8 (load addr:$a)),
650 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
651 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
652 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
653 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
654 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
657 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
658 DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
660 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
661 DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
663 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
664 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
665 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
666 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
667 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
668 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
669 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
670 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
671 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
672 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
673 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
674 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;