1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips DSP ASE instructions.
12 //===----------------------------------------------------------------------===//
15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
23 // Mips-specific dsp nodes
24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
25 SDTCisVT<2, untyped>]>;
26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
27 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
29 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
34 SDNode<!strconcat("MipsISD::", Opc), Prof>;
36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
37 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
87 class Uses<list<Register> Regs> {
88 list<Register> Uses = Regs;
91 class Defs<list<Register> Regs> {
92 list<Register> Defs = Regs;
95 // Instruction encoding.
96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
152 class MFHI_ENC : MFHI_FMT<0b010000>;
153 class MFLO_ENC : MFHI_FMT<0b010010>;
154 class MTHI_ENC : MTHI_FMT<0b010001>;
155 class MTLO_ENC : MTHI_FMT<0b010011>;
156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
181 class REPL_QB_ENC : REPL_FMT<0b00010>;
182 class REPL_PH_ENC : REPL_FMT<0b01010>;
183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
187 class LWX_ENC : LX_FMT<0b00000>;
188 class LHX_ENC : LX_FMT<0b00100>;
189 class LBUX_ENC : LX_FMT<0b00110>;
190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
191 class INSV_ENC : INSV_FMT<0b001100>;
193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
254 class APPEND_ENC : APPEND_FMT<0b00000>;
255 class BALIGN_ENC : APPEND_FMT<0b10000>;
256 class PREPEND_ENC : APPEND_FMT<0b00001>;
259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
260 InstrItinClass itin, RegisterOperand ROD,
261 RegisterOperand ROS, RegisterOperand ROT = ROS> {
262 dag OutOperandList = (outs ROD:$rd);
263 dag InOperandList = (ins ROS:$rs, ROT:$rt);
264 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
265 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
266 InstrItinClass Itinerary = itin;
267 string BaseOpcode = instr_asm;
270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
271 InstrItinClass itin, RegisterOperand ROD,
272 RegisterOperand ROS = ROD> {
273 dag OutOperandList = (outs ROD:$rd);
274 dag InOperandList = (ins ROS:$rs);
275 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
276 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
277 InstrItinClass Itinerary = itin;
280 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
281 InstrItinClass itin, RegisterOperand ROS,
282 RegisterOperand ROT = ROS> {
283 dag OutOperandList = (outs);
284 dag InOperandList = (ins ROS:$rs, ROT:$rt);
285 string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
286 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
287 InstrItinClass Itinerary = itin;
290 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
291 InstrItinClass itin, RegisterOperand ROD,
292 RegisterOperand ROS, RegisterOperand ROT = ROS> {
293 dag OutOperandList = (outs ROD:$rd);
294 dag InOperandList = (ins ROS:$rs, ROT:$rt);
295 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
296 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
297 InstrItinClass Itinerary = itin;
300 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
301 InstrItinClass itin, RegisterOperand ROT,
302 RegisterOperand ROS = ROT> {
303 dag OutOperandList = (outs ROT:$rt);
304 dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
305 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
306 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
307 InstrItinClass Itinerary = itin;
308 string Constraints = "$src = $rt";
311 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
312 InstrItinClass itin, RegisterOperand ROD,
313 RegisterOperand ROT = ROD> {
314 dag OutOperandList = (outs ROD:$rd);
315 dag InOperandList = (ins ROT:$rt);
316 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
317 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
318 InstrItinClass Itinerary = itin;
319 string BaseOpcode = instr_asm;
322 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
323 ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
324 dag OutOperandList = (outs RO:$rd);
325 dag InOperandList = (ins uimm16:$imm);
326 string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
327 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
328 InstrItinClass Itinerary = itin;
331 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
332 InstrItinClass itin, RegisterOperand RO> {
333 dag OutOperandList = (outs RO:$rd);
334 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
335 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
336 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
337 InstrItinClass Itinerary = itin;
338 string BaseOpcode = instr_asm;
341 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
342 SDPatternOperator ImmPat, InstrItinClass itin,
343 RegisterOperand RO, Operand ImmOpnd> {
344 dag OutOperandList = (outs RO:$rd);
345 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
346 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
347 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
348 InstrItinClass Itinerary = itin;
349 bit hasSideEffects = 1;
350 string BaseOpcode = instr_asm;
353 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
354 InstrItinClass itin> {
355 dag OutOperandList = (outs GPR32Opnd:$rd);
356 dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
357 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
358 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
359 InstrItinClass Itinerary = itin;
363 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
364 InstrItinClass itin, RegisterOperand ROD,
365 RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
366 dag OutOperandList = (outs ROD:$rd);
367 dag InOperandList = (ins ROS:$rs, ROT:$rt);
368 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
369 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
370 InstrItinClass Itinerary = itin;
371 string BaseOpcode = instr_asm;
374 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
375 SDPatternOperator ImmOp, InstrItinClass itin> {
376 dag OutOperandList = (outs GPR32Opnd:$rt);
377 dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
378 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
379 list<dag> Pattern = [(set GPR32Opnd:$rt,
380 (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
381 InstrItinClass Itinerary = itin;
382 string Constraints = "$src = $rt";
385 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
386 InstrItinClass itin> {
387 dag OutOperandList = (outs GPR32Opnd:$rt);
388 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
389 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
390 InstrItinClass Itinerary = itin;
393 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
394 InstrItinClass itin> {
395 dag OutOperandList = (outs GPR32Opnd:$rt);
396 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
397 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
398 InstrItinClass Itinerary = itin;
401 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
402 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
403 dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
404 string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
405 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
406 (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
407 string Constraints = "$acin = $ac";
410 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
411 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
412 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
413 string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
414 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
415 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
416 string Constraints = "$acin = $ac";
419 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
420 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
421 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
422 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
423 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
424 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
425 string Constraints = "$acin = $ac";
428 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
429 InstrItinClass itin> {
430 dag OutOperandList = (outs GPR32Opnd:$rd);
431 dag InOperandList = (ins uimm16:$mask);
432 string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
433 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
434 InstrItinClass Itinerary = itin;
437 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
438 InstrItinClass itin> {
439 dag OutOperandList = (outs);
440 dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
441 string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
442 list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
443 InstrItinClass Itinerary = itin;
446 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
447 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
448 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
449 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
450 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
451 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
452 string Constraints = "$acin = $ac";
453 string BaseOpcode = instr_asm;
456 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
457 InstrItinClass itin> {
458 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
459 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
460 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
461 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
462 InstrItinClass Itinerary = itin;
463 bit isCommutable = 1;
464 string BaseOpcode = instr_asm;
467 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
468 InstrItinClass itin> {
469 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
470 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
471 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
472 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
473 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
474 InstrItinClass Itinerary = itin;
475 string Constraints = "$acin = $ac";
476 string BaseOpcode = instr_asm;
479 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
480 InstrItinClass itin> {
481 dag OutOperandList = (outs GPR32Opnd:$rd);
482 dag InOperandList = (ins RO:$ac);
483 string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
484 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
485 InstrItinClass Itinerary = itin;
488 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
489 dag OutOperandList = (outs RO:$ac);
490 dag InOperandList = (ins GPR32Opnd:$rs);
491 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
492 InstrItinClass Itinerary = itin;
495 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
496 MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
497 bit usesCustomInserter = 1;
500 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
501 dag OutOperandList = (outs);
502 dag InOperandList = (ins brtarget:$offset);
503 string AsmString = !strconcat(instr_asm, "\t$offset");
504 InstrItinClass Itinerary = itin;
506 bit isTerminator = 1;
507 bit hasDelaySlot = 1;
510 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
511 InstrItinClass itin> {
512 dag OutOperandList = (outs GPR32Opnd:$rt);
513 dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
514 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
515 list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
516 InstrItinClass Itinerary = itin;
517 string Constraints = "$src = $rt";
518 string BaseOpcode = instr_asm;
521 //===----------------------------------------------------------------------===//
523 //===----------------------------------------------------------------------===//
525 // Addition/subtraction
526 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
527 DSPROpnd, DSPROpnd>, IsCommutable,
528 Defs<[DSPOutFlag20]>;
530 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
531 NoItinerary, DSPROpnd, DSPROpnd>,
532 IsCommutable, Defs<[DSPOutFlag20]>;
534 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
536 Defs<[DSPOutFlag20]>;
538 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
539 NoItinerary, DSPROpnd, DSPROpnd>,
540 Defs<[DSPOutFlag20]>;
542 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
543 DSPROpnd, DSPROpnd>, IsCommutable,
544 Defs<[DSPOutFlag20]>;
546 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
547 NoItinerary, DSPROpnd, DSPROpnd>,
548 IsCommutable, Defs<[DSPOutFlag20]>;
550 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
552 Defs<[DSPOutFlag20]>;
554 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
555 NoItinerary, DSPROpnd, DSPROpnd>,
556 Defs<[DSPOutFlag20]>;
558 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
559 NoItinerary, GPR32Opnd, GPR32Opnd>,
560 IsCommutable, Defs<[DSPOutFlag20]>;
562 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
563 NoItinerary, GPR32Opnd, GPR32Opnd>,
564 Defs<[DSPOutFlag20]>;
566 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
567 GPR32Opnd, GPR32Opnd>, IsCommutable,
570 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
571 GPR32Opnd, GPR32Opnd>,
572 IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
574 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
575 GPR32Opnd, GPR32Opnd>;
577 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
578 NoItinerary, GPR32Opnd, DSPROpnd>;
581 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
582 NoItinerary, DSPROpnd>,
583 Defs<[DSPOutFlag20]>;
585 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
586 NoItinerary, GPR32Opnd>,
587 Defs<[DSPOutFlag20]>;
589 // Precision reduce/expand
590 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
591 int_mips_precrq_qb_ph,
592 NoItinerary, DSPROpnd, DSPROpnd>;
594 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
595 int_mips_precrq_ph_w,
596 NoItinerary, DSPROpnd, GPR32Opnd>;
598 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
599 int_mips_precrq_rs_ph_w,
600 NoItinerary, DSPROpnd,
602 Defs<[DSPOutFlag22]>;
604 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
605 int_mips_precrqu_s_qb_ph,
606 NoItinerary, DSPROpnd,
608 Defs<[DSPOutFlag22]>;
610 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
611 int_mips_preceq_w_phl,
612 NoItinerary, GPR32Opnd, DSPROpnd>;
614 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
615 int_mips_preceq_w_phr,
616 NoItinerary, GPR32Opnd, DSPROpnd>;
618 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
619 int_mips_precequ_ph_qbl,
620 NoItinerary, DSPROpnd>;
622 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
623 int_mips_precequ_ph_qbr,
624 NoItinerary, DSPROpnd>;
626 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
627 int_mips_precequ_ph_qbla,
628 NoItinerary, DSPROpnd>;
630 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
631 int_mips_precequ_ph_qbra,
632 NoItinerary, DSPROpnd>;
634 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
635 int_mips_preceu_ph_qbl,
636 NoItinerary, DSPROpnd>;
638 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
639 int_mips_preceu_ph_qbr,
640 NoItinerary, DSPROpnd>;
642 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
643 int_mips_preceu_ph_qbla,
644 NoItinerary, DSPROpnd>;
646 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
647 int_mips_preceu_ph_qbra,
648 NoItinerary, DSPROpnd>;
651 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
652 NoItinerary, DSPROpnd, uimm3>,
653 Defs<[DSPOutFlag22]>;
655 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
656 NoItinerary, DSPROpnd>,
657 Defs<[DSPOutFlag22]>;
659 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
660 NoItinerary, DSPROpnd, uimm3>;
662 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
663 NoItinerary, DSPROpnd>;
665 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
666 NoItinerary, DSPROpnd, uimm4>,
667 Defs<[DSPOutFlag22]>;
669 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
670 NoItinerary, DSPROpnd>,
671 Defs<[DSPOutFlag22]>;
673 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
674 immZExt4, NoItinerary, DSPROpnd,
676 Defs<[DSPOutFlag22]>;
678 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
679 NoItinerary, DSPROpnd>,
680 Defs<[DSPOutFlag22]>;
682 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
683 NoItinerary, DSPROpnd, uimm4>;
685 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
686 NoItinerary, DSPROpnd>;
688 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
689 immZExt4, NoItinerary, DSPROpnd,
692 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
693 NoItinerary, DSPROpnd>;
695 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
696 immZExt5, NoItinerary, GPR32Opnd,
698 Defs<[DSPOutFlag22]>;
700 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
701 NoItinerary, GPR32Opnd>,
702 Defs<[DSPOutFlag22]>;
704 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
705 immZExt5, NoItinerary, GPR32Opnd,
708 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
709 NoItinerary, GPR32Opnd>;
712 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
713 int_mips_muleu_s_ph_qbl,
714 NoItinerary, DSPROpnd, DSPROpnd>,
715 Defs<[DSPOutFlag21]>;
717 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
718 int_mips_muleu_s_ph_qbr,
719 NoItinerary, DSPROpnd, DSPROpnd>,
720 Defs<[DSPOutFlag21]>;
722 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
723 int_mips_muleq_s_w_phl,
724 NoItinerary, GPR32Opnd, DSPROpnd>,
725 IsCommutable, Defs<[DSPOutFlag21]>;
727 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
728 int_mips_muleq_s_w_phr,
729 NoItinerary, GPR32Opnd, DSPROpnd>,
730 IsCommutable, Defs<[DSPOutFlag21]>;
732 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
733 NoItinerary, DSPROpnd, DSPROpnd>,
734 IsCommutable, Defs<[DSPOutFlag21]>;
736 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
738 Defs<[DSPOutFlag16_19]>;
740 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
741 Defs<[DSPOutFlag16_19]>;
743 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
744 Defs<[DSPOutFlag16_19]>;
746 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
747 Defs<[DSPOutFlag16_19]>;
749 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
750 Defs<[DSPOutFlag16_19]>;
752 // Move from/to hi/lo.
753 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
754 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
755 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
756 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
758 // Dot product with accumulate/subtract
759 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
761 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
763 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
765 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
767 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
768 Defs<[DSPOutFlag16_19]>;
770 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
771 Defs<[DSPOutFlag16_19]>;
773 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
774 Defs<[DSPOutFlag16_19]>;
776 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
777 Defs<[DSPOutFlag16_19]>;
779 class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
780 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
781 class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
782 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
783 class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
784 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
787 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
788 int_mips_cmpu_eq_qb, NoItinerary,
790 IsCommutable, Defs<[DSPCCond]>;
792 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
793 int_mips_cmpu_lt_qb, NoItinerary,
794 DSPROpnd>, Defs<[DSPCCond]>;
796 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
797 int_mips_cmpu_le_qb, NoItinerary,
798 DSPROpnd>, Defs<[DSPCCond]>;
800 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
801 int_mips_cmpgu_eq_qb,
802 NoItinerary, GPR32Opnd, DSPROpnd>,
805 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
806 int_mips_cmpgu_lt_qb,
807 NoItinerary, GPR32Opnd, DSPROpnd>;
809 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
810 int_mips_cmpgu_le_qb,
811 NoItinerary, GPR32Opnd, DSPROpnd>;
813 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
814 NoItinerary, DSPROpnd>,
815 IsCommutable, Defs<[DSPCCond]>;
817 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
818 NoItinerary, DSPROpnd>,
821 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
822 NoItinerary, DSPROpnd>,
826 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
827 NoItinerary, GPR32Opnd>;
829 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
830 NoItinerary, DSPROpnd, DSPROpnd>;
832 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
833 NoItinerary, DSPROpnd>;
835 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
836 NoItinerary, DSPROpnd>;
838 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
839 NoItinerary, DSPROpnd, GPR32Opnd>;
841 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
842 NoItinerary, DSPROpnd, GPR32Opnd>;
844 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
845 NoItinerary, DSPROpnd, DSPROpnd>,
848 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
849 NoItinerary, DSPROpnd, DSPROpnd>,
852 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
854 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
856 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
858 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
861 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
862 Uses<[DSPPos]>, Defs<[DSPEFI]>;
864 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
865 Uses<[DSPPos]>, Defs<[DSPEFI]>;
867 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
868 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
870 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
872 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
874 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
875 Defs<[DSPOutFlag23]>;
877 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
878 NoItinerary>, Defs<[DSPOutFlag23]>;
880 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
882 Defs<[DSPOutFlag23]>;
884 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
886 Defs<[DSPOutFlag23]>;
888 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
890 Defs<[DSPOutFlag23]>;
892 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
894 Defs<[DSPOutFlag23]>;
896 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
898 Defs<[DSPOutFlag23]>;
900 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
902 Defs<[DSPOutFlag23]>;
904 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
906 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
908 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
910 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
912 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
914 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
915 Uses<[DSPPos, DSPSCount]>;
917 //===----------------------------------------------------------------------===//
919 // Addition/subtraction
920 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
921 DSPROpnd, DSPROpnd>, IsCommutable,
922 Defs<[DSPOutFlag20]>;
924 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
925 NoItinerary, DSPROpnd, DSPROpnd>,
926 IsCommutable, Defs<[DSPOutFlag20]>;
928 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
930 Defs<[DSPOutFlag20]>;
932 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
933 NoItinerary, DSPROpnd, DSPROpnd>,
934 Defs<[DSPOutFlag20]>;
936 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
937 NoItinerary, DSPROpnd>, IsCommutable;
939 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
940 NoItinerary, DSPROpnd>, IsCommutable;
942 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
943 NoItinerary, DSPROpnd>;
945 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
946 NoItinerary, DSPROpnd>;
948 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
949 NoItinerary, DSPROpnd>, IsCommutable;
951 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
952 NoItinerary, DSPROpnd>, IsCommutable;
954 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
955 NoItinerary, DSPROpnd>;
957 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
958 NoItinerary, DSPROpnd>;
960 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
961 NoItinerary, GPR32Opnd>, IsCommutable;
963 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
964 NoItinerary, GPR32Opnd>, IsCommutable;
966 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
967 NoItinerary, GPR32Opnd>;
969 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
970 NoItinerary, GPR32Opnd>;
973 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
974 int_mips_cmpgdu_eq_qb,
975 NoItinerary, GPR32Opnd, DSPROpnd>,
976 IsCommutable, Defs<[DSPCCond]>;
978 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
979 int_mips_cmpgdu_lt_qb,
980 NoItinerary, GPR32Opnd, DSPROpnd>,
983 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
984 int_mips_cmpgdu_le_qb,
985 NoItinerary, GPR32Opnd, DSPROpnd>,
989 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
990 NoItinerary, DSPROpnd>,
991 Defs<[DSPOutFlag20]>;
994 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
995 DSPROpnd>, IsCommutable,
996 Defs<[DSPOutFlag21]>;
998 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
999 NoItinerary, DSPROpnd>, IsCommutable,
1000 Defs<[DSPOutFlag21]>;
1002 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1003 NoItinerary, GPR32Opnd>, IsCommutable,
1004 Defs<[DSPOutFlag21]>;
1006 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1007 NoItinerary, GPR32Opnd>, IsCommutable,
1008 Defs<[DSPOutFlag21]>;
1010 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1011 NoItinerary, DSPROpnd, DSPROpnd>,
1012 IsCommutable, Defs<[DSPOutFlag21]>;
1014 // Dot product with accumulate/subtract
1015 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1017 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1019 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1020 Defs<[DSPOutFlag16_19]>;
1022 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1024 Defs<[DSPOutFlag16_19]>;
1026 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1028 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1030 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1031 Defs<[DSPOutFlag16_19]>;
1033 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1035 Defs<[DSPOutFlag16_19]>;
1037 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1039 // Precision reduce/expand
1040 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1041 int_mips_precr_qb_ph,
1042 NoItinerary, DSPROpnd, DSPROpnd>;
1044 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1045 int_mips_precr_sra_ph_w,
1046 NoItinerary, DSPROpnd,
1049 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1050 int_mips_precr_sra_r_ph_w,
1051 NoItinerary, DSPROpnd,
1055 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1056 NoItinerary, DSPROpnd, uimm3>;
1058 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1059 NoItinerary, DSPROpnd>;
1061 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1062 immZExt3, NoItinerary, DSPROpnd,
1065 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1066 NoItinerary, DSPROpnd>;
1068 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1069 NoItinerary, DSPROpnd, uimm4>;
1071 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1072 NoItinerary, DSPROpnd>;
1075 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1078 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1081 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1085 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1086 NoItinerary>, Uses<[DSPPos]>;
1088 // Instruction defs.
1090 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1091 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1092 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1093 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1094 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1095 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1096 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1097 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1098 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1099 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1100 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1101 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1102 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1103 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1104 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1105 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1106 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1107 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1108 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1109 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1110 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1111 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1112 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1113 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1114 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1115 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1116 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1117 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1118 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1119 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1120 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1121 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1122 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1123 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1124 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1125 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1126 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1127 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1128 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1129 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1130 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1131 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1132 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1133 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1134 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1135 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1136 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1137 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1138 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1139 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1140 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1141 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1142 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1143 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1144 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1145 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1146 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1147 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1148 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1149 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1150 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1151 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1152 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1153 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1154 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1155 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1156 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1157 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1158 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1159 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1160 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1161 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1162 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1163 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1164 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1165 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1166 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1167 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1168 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1169 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1170 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1171 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1172 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1173 def BITREV : BITREV_ENC, BITREV_DESC;
1174 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1175 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1176 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1177 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1178 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1179 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1180 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1181 def LWX : LWX_ENC, LWX_DESC;
1182 def LHX : LHX_ENC, LHX_DESC;
1183 def LBUX : LBUX_ENC, LBUX_DESC;
1184 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1185 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1186 def EXTP : EXTP_ENC, EXTP_DESC;
1187 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1188 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1189 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1190 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1191 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1192 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1193 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1194 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1195 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1196 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1197 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1198 def SHILO : SHILO_ENC, SHILO_DESC;
1199 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1200 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1201 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1202 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1205 let Predicates = [HasDSPR2] in {
1207 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1208 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1209 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1210 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1211 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1212 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1213 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1214 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1215 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1216 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1217 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1218 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1219 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1220 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1221 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1222 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1223 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1224 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1225 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1226 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1227 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1228 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1229 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1230 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1231 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1232 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1233 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1234 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1235 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1236 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1237 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1238 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1239 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1240 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1241 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1242 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1243 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1244 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1245 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
1246 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1247 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1248 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
1249 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
1250 def APPEND : APPEND_ENC, APPEND_DESC;
1251 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1252 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1257 let isPseudo = 1, isCodeGenOnly = 1 in {
1258 // Pseudo instructions for loading and storing accumulator registers.
1259 def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>;
1260 def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1262 // Pseudos for loading and storing ccond field of DSP control register.
1263 def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>;
1264 def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1267 // Pseudo CMP and PICK instructions.
1268 class PseudoCMP<Instruction RealInst> :
1269 PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1270 PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1272 class PseudoPICK<Instruction RealInst> :
1273 PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1274 PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1275 NeverHasSideEffects;
1277 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1278 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1279 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1280 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1281 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1282 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1284 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1285 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1287 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1290 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1291 Pat<pattern, result>, Requires<[pred]>;
1293 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1294 RegisterClass SrcRC> :
1295 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1296 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1298 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1299 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1300 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1301 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1303 def : DSPPat<(v2i16 (load addr:$a)),
1304 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1305 def : DSPPat<(v4i8 (load addr:$a)),
1306 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1307 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1308 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1309 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1310 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1312 // Binary operations.
1313 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1314 Predicate Pred = HasDSP> :
1315 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1317 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1318 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1319 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1320 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1321 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1322 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1323 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1324 def : DSPBinPat<ADDU_QB, v4i8, add>;
1325 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1326 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1327 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1328 def : DSPBinPat<ADDSC, i32, addc>;
1329 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1330 def : DSPBinPat<ADDWC, i32, adde>;
1332 // Shift immediate patterns.
1333 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1334 SDPatternOperator Imm, Predicate Pred = HasDSP> :
1335 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1337 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1338 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1339 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1340 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1341 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1342 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1343 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1344 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1345 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1346 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1347 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1348 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1350 // SETCC/SELECT_CC patterns.
1351 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1353 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1354 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1355 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1358 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1360 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1361 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1363 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1365 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1367 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1368 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1370 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1372 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1373 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1375 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1376 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1377 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1378 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1379 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1380 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1381 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1382 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1383 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1384 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1385 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1386 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1388 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1389 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1390 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1391 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1392 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1393 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1394 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1395 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1396 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1397 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1398 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1399 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1402 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1403 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1404 (Instr ACC64DSP:$ac, GPR32:$rs)>;
1406 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1407 DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1408 (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1410 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1411 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1412 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1413 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1414 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1415 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1416 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1417 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1418 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1419 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1420 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1421 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1423 // Indexed load patterns.
1424 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1425 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1426 (Instr i32:$base, i32:$index)>;
1428 let AddedComplexity = 20 in {
1429 def : IndexedLoadPat<zextloadi8, LBUX>;
1430 def : IndexedLoadPat<sextloadi16, LHX>;
1431 def : IndexedLoadPat<load, LWX>;