1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "delay-slot-filler"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
33 STATISTIC(FilledSlots, "Number of delay slots filled");
34 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
37 static cl::opt<bool> DisableDelaySlotFiller(
38 "disable-mips-delay-filler",
40 cl::desc("Fill all delay slots with NOPs."),
43 // This option can be used to silence complaints by machine verifier passes.
44 static cl::opt<bool> SkipDelaySlotFiller(
45 "skip-mips-delay-filler",
47 cl::desc("Skip MIPS' delay slot filling pass."),
53 RegDefsUses(TargetMachine &TM);
54 void init(const MachineInstr &MI);
55 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
58 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
61 /// Returns true if Reg or its alias is in RegSet.
62 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
64 const TargetRegisterInfo &TRI;
68 /// This class maintains memory dependence information.
71 MemDefsUses(const MachineFrameInfo *MFI);
73 /// Return true if MI cannot be moved to delay slot.
74 bool hasHazard(const MachineInstr &MI);
77 /// Update Defs and Uses. Return true if there exist dependences that
78 /// disqualify the delay slot candidate between V and values in Uses and Defs.
79 bool updateDefsUses(const Value *V, bool MayStore);
81 /// Get the list of underlying objects of MI's memory operand.
82 bool getUnderlyingObjects(const MachineInstr &MI,
83 SmallVectorImpl<const Value *> &Objects) const;
85 const MachineFrameInfo *MFI;
86 SmallPtrSet<const Value*, 4> Uses, Defs;
88 /// Flags indicating whether loads or stores have been seen.
89 bool SeenLoad, SeenStore;
91 /// Flags indicating whether loads or stores with no underlying objects have
93 bool SeenNoObjLoad, SeenNoObjStore;
95 /// Memory instructions are not allowed to move to delay slot if this flag
100 class Filler : public MachineFunctionPass {
102 Filler(TargetMachine &tm)
103 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
105 virtual const char *getPassName() const {
106 return "Mips Delay Slot Filler";
109 bool runOnMachineFunction(MachineFunction &F) {
110 if (SkipDelaySlotFiller)
113 bool Changed = false;
114 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
116 Changed |= runOnMachineBasicBlock(*FI);
121 typedef MachineBasicBlock::iterator Iter;
122 typedef MachineBasicBlock::reverse_iterator ReverseIter;
124 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
126 /// This function checks if it is valid to move Candidate to the delay slot
127 /// and returns true if it isn't. It also updates memory and register
128 /// dependence information.
129 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
130 MemDefsUses &MemDU) const;
132 /// This function searches range [Begin, End) for an instruction that can be
133 /// moved to the delay slot. Returns true on success.
134 template<typename IterTy>
135 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
136 RegDefsUses &RegDU, MemDefsUses &MemDU, IterTy &Filler) const;
138 bool searchBackward(MachineBasicBlock &MBB, Iter Slot, Iter &Filler) const;
140 bool terminateSearch(const MachineInstr &Candidate) const;
143 const TargetInstrInfo *TII;
148 } // end of anonymous namespace
150 RegDefsUses::RegDefsUses(TargetMachine &TM)
151 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
152 Uses(TRI.getNumRegs(), false) {}
154 void RegDefsUses::init(const MachineInstr &MI) {
155 // Add all register operands which are explicit and non-variadic.
156 update(MI, 0, MI.getDesc().getNumOperands());
158 // If MI is a call, add RA to Defs to prevent users of RA from going into
163 // Add all implicit register operands of branch instructions except
166 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
167 Defs.reset(Mips::AT);
171 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
172 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
173 bool HasHazard = false;
175 for (unsigned I = Begin; I != End; ++I) {
176 const MachineOperand &MO = MI.getOperand(I);
178 if (MO.isReg() && MO.getReg())
179 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
188 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
189 unsigned Reg, bool IsDef) const {
192 // check whether Reg has already been defined or used.
193 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
197 // check whether Reg has already been defined.
198 return isRegInSet(Defs, Reg);
201 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
202 // Check Reg and all aliased Registers.
203 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
204 if (RegSet.test(*AI))
209 MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
210 : MFI(MFI_), SeenLoad(false), SeenStore(false), SeenNoObjLoad(false),
211 SeenNoObjStore(false), ForbidMemInstr(false) {}
213 bool MemDefsUses::hasHazard(const MachineInstr &MI) {
214 if (!MI.mayStore() && !MI.mayLoad())
220 bool OrigSeenLoad = SeenLoad, OrigSeenStore = SeenStore;
222 SeenLoad |= MI.mayLoad();
223 SeenStore |= MI.mayStore();
225 // If MI is an ordered or volatile memory reference, disallow moving
226 // subsequent loads and stores to delay slot.
227 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
228 ForbidMemInstr = true;
232 bool HasHazard = false;
233 SmallVector<const Value *, 4> Objs;
235 // Check underlying object list.
236 if (getUnderlyingObjects(MI, Objs)) {
237 for (SmallVector<const Value *, 4>::const_iterator I = Objs.begin();
238 I != Objs.end(); ++I)
239 HasHazard |= updateDefsUses(*I, MI.mayStore());
244 // No underlying objects found.
245 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
246 HasHazard |= MI.mayLoad() || OrigSeenStore;
248 SeenNoObjLoad |= MI.mayLoad();
249 SeenNoObjStore |= MI.mayStore();
254 bool MemDefsUses::updateDefsUses(const Value *V, bool MayStore) {
256 return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
259 return Defs.count(V) || SeenNoObjStore;
263 getUnderlyingObjects(const MachineInstr &MI,
264 SmallVectorImpl<const Value *> &Objects) const {
265 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
268 const Value *V = (*MI.memoperands_begin())->getValue();
270 SmallVector<Value *, 4> Objs;
271 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
273 for (SmallVector<Value*, 4>::iterator I = Objs.begin(), E = Objs.end();
275 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(*I)) {
276 if (PSV->isAliased(MFI))
278 } else if (!isIdentifiedObject(V))
281 Objects.push_back(*I);
287 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
288 /// We assume there is only one delay slot per delayed instruction.
289 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
290 bool Changed = false;
292 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
293 if (!I->hasDelaySlot())
300 // Delay slot filling is disabled at -O0.
301 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
302 searchBackward(MBB, I, D)) {
303 MBB.splice(llvm::next(I), &MBB, D);
306 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
308 // Bundle the delay slot filler to the instruction with the delay slot.
309 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
315 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
316 /// slots in Mips MachineFunctions
317 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
318 return new Filler(tm);
321 template<typename IterTy>
322 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
323 RegDefsUses &RegDU, MemDefsUses &MemDU,
324 IterTy &Filler) const {
325 for (IterTy I = Begin; I != End; ++I) {
327 if (I->isDebugValue())
330 if (terminateSearch(*I))
333 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
334 "Cannot put calls, returns or branches in delay slot.");
336 if (delayHasHazard(*I, RegDU, MemDU))
346 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot,
347 Iter &Filler) const {
348 RegDefsUses RegDU(TM);
349 MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
350 ReverseIter FillerReverse;
354 if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU,
356 Filler = llvm::next(FillerReverse).base();
363 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
364 MemDefsUses &MemDU) const {
365 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
367 HasHazard |= MemDU.hasHazard(Candidate);
368 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
373 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
374 return (Candidate.isTerminator() || Candidate.isCall() ||
375 Candidate.isLabel() || Candidate.isInlineAsm() ||
376 Candidate.hasUnmodeledSideEffects());