1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "delay-slot-filler"
17 #include "MipsInstrInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
35 STATISTIC(FilledSlots, "Number of delay slots filled");
36 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
39 static cl::opt<bool> DisableDelaySlotFiller(
40 "disable-mips-delay-filler",
42 cl::desc("Fill all delay slots with NOPs."),
45 static cl::opt<bool> DisableForwardSearch(
46 "disable-mips-df-forward-search",
48 cl::desc("Disallow MIPS delay filler to search forward."),
51 static cl::opt<bool> DisableSuccBBSearch(
52 "disable-mips-df-succbb-search",
54 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
57 static cl::opt<bool> DisableBackwardSearch(
58 "disable-mips-df-backward-search",
60 cl::desc("Disallow MIPS delay filler to search backward."),
64 typedef MachineBasicBlock::iterator Iter;
65 typedef MachineBasicBlock::reverse_iterator ReverseIter;
66 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
68 /// \brief A functor comparing edge weight of two blocks.
70 CmpWeight(const MachineBasicBlock &S,
71 const MachineBranchProbabilityInfo &P) : Src(S), Prob(P) {}
73 bool operator()(const MachineBasicBlock *Dst0,
74 const MachineBasicBlock *Dst1) const {
75 return Prob.getEdgeWeight(&Src, Dst0) < Prob.getEdgeWeight(&Src, Dst1);
78 const MachineBasicBlock &Src;
79 const MachineBranchProbabilityInfo &Prob;
84 RegDefsUses(TargetMachine &TM);
85 void init(const MachineInstr &MI);
87 /// This function sets all caller-saved registers in Defs.
88 void setCallerSaved(const MachineInstr &MI);
90 /// This function sets all unallocatable registers in Defs.
91 void setUnallocatableRegs(const MachineFunction &MF);
93 /// Set bits in Uses corresponding to MBB's live-out registers except for
94 /// the registers that are live-in to SuccBB.
95 void addLiveOut(const MachineBasicBlock &MBB,
96 const MachineBasicBlock &SuccBB);
98 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
101 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
104 /// Returns true if Reg or its alias is in RegSet.
105 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
107 const TargetRegisterInfo &TRI;
108 BitVector Defs, Uses;
111 /// Base class for inspecting loads and stores.
112 class InspectMemInstr {
114 InspectMemInstr(bool ForbidMemInstr_)
115 : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
116 SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
118 /// Return true if MI cannot be moved to delay slot.
119 bool hasHazard(const MachineInstr &MI);
121 virtual ~InspectMemInstr() {}
124 /// Flags indicating whether loads or stores have been seen.
125 bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
127 /// Memory instructions are not allowed to move to delay slot if this flag
132 virtual bool hasHazard_(const MachineInstr &MI) = 0;
135 /// This subclass rejects any memory instructions.
136 class NoMemInstr : public InspectMemInstr {
138 NoMemInstr() : InspectMemInstr(true) {}
140 virtual bool hasHazard_(const MachineInstr &MI) { return true; }
143 /// This subclass accepts loads from stacks and constant loads.
144 class LoadFromStackOrConst : public InspectMemInstr {
146 LoadFromStackOrConst() : InspectMemInstr(false) {}
148 virtual bool hasHazard_(const MachineInstr &MI);
151 /// This subclass uses memory dependence information to determine whether a
152 /// memory instruction can be moved to a delay slot.
153 class MemDefsUses : public InspectMemInstr {
155 MemDefsUses(const MachineFrameInfo *MFI);
158 virtual bool hasHazard_(const MachineInstr &MI);
160 /// Update Defs and Uses. Return true if there exist dependences that
161 /// disqualify the delay slot candidate between V and values in Uses and
163 bool updateDefsUses(const Value *V, bool MayStore);
165 /// Get the list of underlying objects of MI's memory operand.
166 bool getUnderlyingObjects(const MachineInstr &MI,
167 SmallVectorImpl<const Value *> &Objects) const;
169 const MachineFrameInfo *MFI;
170 SmallPtrSet<const Value*, 4> Uses, Defs;
172 /// Flags indicating whether loads or stores with no underlying objects have
174 bool SeenNoObjLoad, SeenNoObjStore;
177 class Filler : public MachineFunctionPass {
179 Filler(TargetMachine &tm)
180 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
182 virtual const char *getPassName() const {
183 return "Mips Delay Slot Filler";
186 bool runOnMachineFunction(MachineFunction &F) {
187 bool Changed = false;
188 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
190 Changed |= runOnMachineBasicBlock(*FI);
194 void getAnalysisUsage(AnalysisUsage &AU) const {
195 AU.addRequired<MachineBranchProbabilityInfo>();
196 MachineFunctionPass::getAnalysisUsage(AU);
200 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
202 /// This function checks if it is valid to move Candidate to the delay slot
203 /// and returns true if it isn't. It also updates memory and register
204 /// dependence information.
205 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
206 InspectMemInstr &IM) const;
208 /// This function searches range [Begin, End) for an instruction that can be
209 /// moved to the delay slot. Returns true on success.
210 template<typename IterTy>
211 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
212 RegDefsUses &RegDU, InspectMemInstr &IM,
213 IterTy &Filler) const;
215 /// This function searches in the backward direction for an instruction that
216 /// can be moved to the delay slot. Returns true on success.
217 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
219 /// This function searches MBB in the forward direction for an instruction
220 /// that can be moved to the delay slot. Returns true on success.
221 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
223 /// This function searches one of MBB's successor blocks for an instruction
224 /// that can be moved to the delay slot and inserts clones of the
225 /// instruction into the successor's predecessor blocks.
226 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
228 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
229 /// successor block that is not a landing pad.
230 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
232 /// This function analyzes MBB and returns an instruction with an unoccupied
233 /// slot that branches to Dst.
234 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
235 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
237 /// Examine Pred and see if it is possible to insert an instruction into
238 /// one of its branches delay slot or its end.
239 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
240 RegDefsUses &RegDU, bool &HasMultipleSuccs,
241 BB2BrMap &BrMap) const;
243 bool terminateSearch(const MachineInstr &Candidate) const;
246 const TargetInstrInfo *TII;
251 } // end of anonymous namespace
253 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
254 return MI->hasDelaySlot() && !MI->isBundledWithSucc();
257 /// This function inserts clones of Filler into predecessor blocks.
258 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
259 MachineFunction *MF = Filler->getParent()->getParent();
261 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
263 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
266 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
271 /// This function adds registers Filler defines to MBB's live-in register list.
272 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
273 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
274 const MachineOperand &MO = Filler->getOperand(I);
277 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
281 const MachineFunction &MF = *MBB.getParent();
282 assert(MF.getTarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
283 "Shouldn't move an instruction with unallocatable registers across "
284 "basic block boundaries.");
287 if (!MBB.isLiveIn(R))
292 RegDefsUses::RegDefsUses(TargetMachine &TM)
293 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
294 Uses(TRI.getNumRegs(), false) {}
296 void RegDefsUses::init(const MachineInstr &MI) {
297 // Add all register operands which are explicit and non-variadic.
298 update(MI, 0, MI.getDesc().getNumOperands());
300 // If MI is a call, add RA to Defs to prevent users of RA from going into
305 // Add all implicit register operands of branch instructions except
308 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
309 Defs.reset(Mips::AT);
313 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
316 // If MI is a call, add all caller-saved registers to Defs.
317 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
319 CallerSavedRegs.reset(Mips::ZERO);
320 CallerSavedRegs.reset(Mips::ZERO_64);
322 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
323 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
324 CallerSavedRegs.reset(*AI);
326 Defs |= CallerSavedRegs;
329 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
330 BitVector AllocSet = TRI.getAllocatableSet(MF);
332 for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
333 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
336 AllocSet.set(Mips::ZERO);
337 AllocSet.set(Mips::ZERO_64);
339 Defs |= AllocSet.flip();
342 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
343 const MachineBasicBlock &SuccBB) {
344 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
345 SE = MBB.succ_end(); SI != SE; ++SI)
347 for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
348 LE = (*SI)->livein_end(); LI != LE; ++LI)
352 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
353 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
354 bool HasHazard = false;
356 for (unsigned I = Begin; I != End; ++I) {
357 const MachineOperand &MO = MI.getOperand(I);
359 if (MO.isReg() && MO.getReg())
360 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
369 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
370 unsigned Reg, bool IsDef) const {
373 // check whether Reg has already been defined or used.
374 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
378 // check whether Reg has already been defined.
379 return isRegInSet(Defs, Reg);
382 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
383 // Check Reg and all aliased Registers.
384 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
385 if (RegSet.test(*AI))
390 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
391 if (!MI.mayStore() && !MI.mayLoad())
397 OrigSeenLoad = SeenLoad;
398 OrigSeenStore = SeenStore;
399 SeenLoad |= MI.mayLoad();
400 SeenStore |= MI.mayStore();
402 // If MI is an ordered or volatile memory reference, disallow moving
403 // subsequent loads and stores to delay slot.
404 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
405 ForbidMemInstr = true;
409 return hasHazard_(MI);
412 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
416 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
419 const Value *V = (*MI.memoperands_begin())->getValue();
421 if (isa<FixedStackPseudoSourceValue>(V))
424 if (const PseudoSourceValue *PSV = dyn_cast<const PseudoSourceValue>(V))
425 return !PSV->PseudoSourceValue::isConstant(0) &&
426 (V != PseudoSourceValue::getStack());
431 MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
432 : InspectMemInstr(false), MFI(MFI_), SeenNoObjLoad(false),
433 SeenNoObjStore(false) {}
435 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
436 bool HasHazard = false;
437 SmallVector<const Value *, 4> Objs;
439 // Check underlying object list.
440 if (getUnderlyingObjects(MI, Objs)) {
441 for (SmallVector<const Value *, 4>::const_iterator I = Objs.begin();
442 I != Objs.end(); ++I)
443 HasHazard |= updateDefsUses(*I, MI.mayStore());
448 // No underlying objects found.
449 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
450 HasHazard |= MI.mayLoad() || OrigSeenStore;
452 SeenNoObjLoad |= MI.mayLoad();
453 SeenNoObjStore |= MI.mayStore();
458 bool MemDefsUses::updateDefsUses(const Value *V, bool MayStore) {
460 return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
463 return Defs.count(V) || SeenNoObjStore;
467 getUnderlyingObjects(const MachineInstr &MI,
468 SmallVectorImpl<const Value *> &Objects) const {
469 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
472 const Value *V = (*MI.memoperands_begin())->getValue();
474 SmallVector<Value *, 4> Objs;
475 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
477 for (SmallVector<Value*, 4>::iterator I = Objs.begin(), E = Objs.end();
479 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(*I)) {
480 if (PSV->isAliased(MFI))
482 } else if (!isIdentifiedObject(V))
485 Objects.push_back(*I);
491 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
492 /// We assume there is only one delay slot per delayed instruction.
493 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
494 bool Changed = false;
496 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
497 if (!hasUnoccupiedSlot(&*I))
503 // Delay slot filling is disabled at -O0.
504 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
505 if (searchBackward(MBB, I))
508 if (I->isTerminator()) {
509 if (searchSuccBBs(MBB, I))
511 } else if (searchForward(MBB, I)) {
516 // Bundle the NOP to the instruction with the delay slot.
517 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
518 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
524 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
525 /// slots in Mips MachineFunctions
526 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
527 return new Filler(tm);
530 template<typename IterTy>
531 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
532 RegDefsUses &RegDU, InspectMemInstr& IM,
533 IterTy &Filler) const {
534 for (IterTy I = Begin; I != End; ++I) {
536 if (I->isDebugValue())
539 if (terminateSearch(*I))
542 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
543 "Cannot put calls, returns or branches in delay slot.");
545 if (delayHasHazard(*I, RegDU, IM))
555 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
556 if (DisableBackwardSearch)
559 RegDefsUses RegDU(TM);
560 MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
565 if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler)) {
566 MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
567 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
575 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
576 // Can handle only calls.
577 if (DisableForwardSearch || !Slot->isCall())
580 RegDefsUses RegDU(TM);
584 RegDU.setCallerSaved(*Slot);
586 if (searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler)) {
587 MBB.splice(llvm::next(Slot), &MBB, Filler);
588 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
596 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
597 if (DisableSuccBBSearch)
600 MachineBasicBlock *SuccBB = selectSuccBB(MBB);
605 RegDefsUses RegDU(TM);
606 bool HasMultipleSuccs = false;
608 OwningPtr<InspectMemInstr> IM;
611 // Iterate over SuccBB's predecessor list.
612 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
613 PE = SuccBB->pred_end(); PI != PE; ++PI)
614 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
617 // Do not allow moving instructions which have unallocatable register operands
618 // across basic block boundaries.
619 RegDU.setUnallocatableRegs(*MBB.getParent());
621 // Only allow moving loads from stack or constants if any of the SuccBB's
622 // predecessors have multiple successors.
623 if (HasMultipleSuccs) {
624 IM.reset(new LoadFromStackOrConst());
626 const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();
627 IM.reset(new MemDefsUses(MFI));
630 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Filler))
633 insertDelayFiller(Filler, BrMap);
634 addLiveInRegs(Filler, *SuccBB);
635 Filler->eraseFromParent();
640 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
644 // Select the successor with the larget edge weight.
645 CmpWeight Cmp(B, getAnalysis<MachineBranchProbabilityInfo>());
646 MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(), Cmp);
647 return S->isLandingPad() ? NULL : S;
650 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
651 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
652 const MipsInstrInfo *TII =
653 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
654 MachineBasicBlock *TrueBB = 0, *FalseBB = 0;
655 SmallVector<MachineInstr*, 2> BranchInstrs;
656 SmallVector<MachineOperand, 2> Cond;
658 MipsInstrInfo::BranchType R =
659 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
661 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
662 return std::make_pair(R, (MachineInstr*)NULL);
664 if (R != MipsInstrInfo::BT_CondUncond) {
665 if (!hasUnoccupiedSlot(BranchInstrs[0]))
666 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
668 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
670 return std::make_pair(R, BranchInstrs[0]);
673 assert((TrueBB == &Dst) || (FalseBB == &Dst));
675 // Examine the conditional branch. See if its slot is occupied.
676 if (hasUnoccupiedSlot(BranchInstrs[0]))
677 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
679 // If that fails, try the unconditional branch.
680 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
681 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
683 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
686 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
687 RegDefsUses &RegDU, bool &HasMultipleSuccs,
688 BB2BrMap &BrMap) const {
689 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
690 getBranch(Pred, Succ);
692 // Return if either getBranch wasn't able to analyze the branches or there
693 // were no branches with unoccupied slots.
694 if (P.first == MipsInstrInfo::BT_None)
697 if ((P.first != MipsInstrInfo::BT_Uncond) &&
698 (P.first != MipsInstrInfo::BT_NoBranch)) {
699 HasMultipleSuccs = true;
700 RegDU.addLiveOut(Pred, Succ);
703 BrMap[&Pred] = P.second;
707 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
708 InspectMemInstr &IM) const {
709 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
711 HasHazard |= IM.hasHazard(Candidate);
712 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
717 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
718 return (Candidate.isTerminator() || Candidate.isCall() ||
719 Candidate.isLabel() || Candidate.isInlineAsm() ||
720 Candidate.hasUnmodeledSideEffects());