1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "delay-slot-filler"
16 #include "MCTargetDesc/MipsMCNaCl.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 STATISTIC(FilledSlots, "Number of delay slots filled");
37 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
40 static cl::opt<bool> DisableDelaySlotFiller(
41 "disable-mips-delay-filler",
43 cl::desc("Fill all delay slots with NOPs."),
46 static cl::opt<bool> DisableForwardSearch(
47 "disable-mips-df-forward-search",
49 cl::desc("Disallow MIPS delay filler to search forward."),
52 static cl::opt<bool> DisableSuccBBSearch(
53 "disable-mips-df-succbb-search",
55 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
58 static cl::opt<bool> DisableBackwardSearch(
59 "disable-mips-df-backward-search",
61 cl::desc("Disallow MIPS delay filler to search backward."),
65 typedef MachineBasicBlock::iterator Iter;
66 typedef MachineBasicBlock::reverse_iterator ReverseIter;
67 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
71 RegDefsUses(TargetMachine &TM);
72 void init(const MachineInstr &MI);
74 /// This function sets all caller-saved registers in Defs.
75 void setCallerSaved(const MachineInstr &MI);
77 /// This function sets all unallocatable registers in Defs.
78 void setUnallocatableRegs(const MachineFunction &MF);
80 /// Set bits in Uses corresponding to MBB's live-out registers except for
81 /// the registers that are live-in to SuccBB.
82 void addLiveOut(const MachineBasicBlock &MBB,
83 const MachineBasicBlock &SuccBB);
85 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
88 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
91 /// Returns true if Reg or its alias is in RegSet.
92 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
94 const TargetRegisterInfo &TRI;
98 /// Base class for inspecting loads and stores.
99 class InspectMemInstr {
101 InspectMemInstr(bool ForbidMemInstr_)
102 : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
103 SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
105 /// Return true if MI cannot be moved to delay slot.
106 bool hasHazard(const MachineInstr &MI);
108 virtual ~InspectMemInstr() {}
111 /// Flags indicating whether loads or stores have been seen.
112 bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
114 /// Memory instructions are not allowed to move to delay slot if this flag
119 virtual bool hasHazard_(const MachineInstr &MI) = 0;
122 /// This subclass rejects any memory instructions.
123 class NoMemInstr : public InspectMemInstr {
125 NoMemInstr() : InspectMemInstr(true) {}
127 virtual bool hasHazard_(const MachineInstr &MI) { return true; }
130 /// This subclass accepts loads from stacks and constant loads.
131 class LoadFromStackOrConst : public InspectMemInstr {
133 LoadFromStackOrConst() : InspectMemInstr(false) {}
135 virtual bool hasHazard_(const MachineInstr &MI);
138 /// This subclass uses memory dependence information to determine whether a
139 /// memory instruction can be moved to a delay slot.
140 class MemDefsUses : public InspectMemInstr {
142 MemDefsUses(const MachineFrameInfo *MFI);
145 virtual bool hasHazard_(const MachineInstr &MI);
147 /// Update Defs and Uses. Return true if there exist dependences that
148 /// disqualify the delay slot candidate between V and values in Uses and
150 bool updateDefsUses(const Value *V, bool MayStore);
152 /// Get the list of underlying objects of MI's memory operand.
153 bool getUnderlyingObjects(const MachineInstr &MI,
154 SmallVectorImpl<const Value *> &Objects) const;
156 const MachineFrameInfo *MFI;
157 SmallPtrSet<const Value*, 4> Uses, Defs;
159 /// Flags indicating whether loads or stores with no underlying objects have
161 bool SeenNoObjLoad, SeenNoObjStore;
164 class Filler : public MachineFunctionPass {
166 Filler(TargetMachine &tm)
167 : MachineFunctionPass(ID), TM(tm) { }
169 virtual const char *getPassName() const {
170 return "Mips Delay Slot Filler";
173 bool runOnMachineFunction(MachineFunction &F) {
174 bool Changed = false;
175 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
177 Changed |= runOnMachineBasicBlock(*FI);
181 void getAnalysisUsage(AnalysisUsage &AU) const {
182 AU.addRequired<MachineBranchProbabilityInfo>();
183 MachineFunctionPass::getAnalysisUsage(AU);
187 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
189 /// This function checks if it is valid to move Candidate to the delay slot
190 /// and returns true if it isn't. It also updates memory and register
191 /// dependence information.
192 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
193 InspectMemInstr &IM) const;
195 /// This function searches range [Begin, End) for an instruction that can be
196 /// moved to the delay slot. Returns true on success.
197 template<typename IterTy>
198 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
199 RegDefsUses &RegDU, InspectMemInstr &IM,
200 IterTy &Filler) const;
202 /// This function searches in the backward direction for an instruction that
203 /// can be moved to the delay slot. Returns true on success.
204 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
206 /// This function searches MBB in the forward direction for an instruction
207 /// that can be moved to the delay slot. Returns true on success.
208 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
210 /// This function searches one of MBB's successor blocks for an instruction
211 /// that can be moved to the delay slot and inserts clones of the
212 /// instruction into the successor's predecessor blocks.
213 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
215 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
216 /// successor block that is not a landing pad.
217 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
219 /// This function analyzes MBB and returns an instruction with an unoccupied
220 /// slot that branches to Dst.
221 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
222 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
224 /// Examine Pred and see if it is possible to insert an instruction into
225 /// one of its branches delay slot or its end.
226 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
227 RegDefsUses &RegDU, bool &HasMultipleSuccs,
228 BB2BrMap &BrMap) const;
230 bool terminateSearch(const MachineInstr &Candidate) const;
237 } // end of anonymous namespace
239 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
240 return MI->hasDelaySlot() && !MI->isBundledWithSucc();
243 /// This function inserts clones of Filler into predecessor blocks.
244 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
245 MachineFunction *MF = Filler->getParent()->getParent();
247 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
249 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
252 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
257 /// This function adds registers Filler defines to MBB's live-in register list.
258 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
259 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
260 const MachineOperand &MO = Filler->getOperand(I);
263 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
267 const MachineFunction &MF = *MBB.getParent();
268 assert(MF.getTarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
269 "Shouldn't move an instruction with unallocatable registers across "
270 "basic block boundaries.");
273 if (!MBB.isLiveIn(R))
278 RegDefsUses::RegDefsUses(TargetMachine &TM)
279 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
280 Uses(TRI.getNumRegs(), false) {}
282 void RegDefsUses::init(const MachineInstr &MI) {
283 // Add all register operands which are explicit and non-variadic.
284 update(MI, 0, MI.getDesc().getNumOperands());
286 // If MI is a call, add RA to Defs to prevent users of RA from going into
291 // Add all implicit register operands of branch instructions except
294 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
295 Defs.reset(Mips::AT);
299 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
302 // If MI is a call, add all caller-saved registers to Defs.
303 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
305 CallerSavedRegs.reset(Mips::ZERO);
306 CallerSavedRegs.reset(Mips::ZERO_64);
308 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
309 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
310 CallerSavedRegs.reset(*AI);
312 Defs |= CallerSavedRegs;
315 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
316 BitVector AllocSet = TRI.getAllocatableSet(MF);
318 for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
319 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
322 AllocSet.set(Mips::ZERO);
323 AllocSet.set(Mips::ZERO_64);
325 Defs |= AllocSet.flip();
328 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
329 const MachineBasicBlock &SuccBB) {
330 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
331 SE = MBB.succ_end(); SI != SE; ++SI)
333 for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
334 LE = (*SI)->livein_end(); LI != LE; ++LI)
338 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
339 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
340 bool HasHazard = false;
342 for (unsigned I = Begin; I != End; ++I) {
343 const MachineOperand &MO = MI.getOperand(I);
345 if (MO.isReg() && MO.getReg())
346 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
355 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
356 unsigned Reg, bool IsDef) const {
359 // check whether Reg has already been defined or used.
360 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
364 // check whether Reg has already been defined.
365 return isRegInSet(Defs, Reg);
368 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
369 // Check Reg and all aliased Registers.
370 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
371 if (RegSet.test(*AI))
376 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
377 if (!MI.mayStore() && !MI.mayLoad())
383 OrigSeenLoad = SeenLoad;
384 OrigSeenStore = SeenStore;
385 SeenLoad |= MI.mayLoad();
386 SeenStore |= MI.mayStore();
388 // If MI is an ordered or volatile memory reference, disallow moving
389 // subsequent loads and stores to delay slot.
390 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
391 ForbidMemInstr = true;
395 return hasHazard_(MI);
398 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
402 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
405 const Value *V = (*MI.memoperands_begin())->getValue();
407 if (isa<FixedStackPseudoSourceValue>(V))
410 if (const PseudoSourceValue *PSV = dyn_cast<const PseudoSourceValue>(V))
411 return !PSV->isConstant(0) && V != PseudoSourceValue::getStack();
416 MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
417 : InspectMemInstr(false), MFI(MFI_), SeenNoObjLoad(false),
418 SeenNoObjStore(false) {}
420 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
421 bool HasHazard = false;
422 SmallVector<const Value *, 4> Objs;
424 // Check underlying object list.
425 if (getUnderlyingObjects(MI, Objs)) {
426 for (SmallVectorImpl<const Value *>::const_iterator I = Objs.begin();
427 I != Objs.end(); ++I)
428 HasHazard |= updateDefsUses(*I, MI.mayStore());
433 // No underlying objects found.
434 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
435 HasHazard |= MI.mayLoad() || OrigSeenStore;
437 SeenNoObjLoad |= MI.mayLoad();
438 SeenNoObjStore |= MI.mayStore();
443 bool MemDefsUses::updateDefsUses(const Value *V, bool MayStore) {
445 return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
448 return Defs.count(V) || SeenNoObjStore;
452 getUnderlyingObjects(const MachineInstr &MI,
453 SmallVectorImpl<const Value *> &Objects) const {
454 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
457 const Value *V = (*MI.memoperands_begin())->getValue();
459 SmallVector<Value *, 4> Objs;
460 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
462 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end();
464 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(*I)) {
465 if (PSV->isAliased(MFI))
467 } else if (!isIdentifiedObject(V))
470 Objects.push_back(*I);
476 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
477 /// We assume there is only one delay slot per delayed instruction.
478 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
479 bool Changed = false;
481 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
482 if (!hasUnoccupiedSlot(&*I))
488 // Delay slot filling is disabled at -O0.
489 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
490 if (searchBackward(MBB, I))
493 if (I->isTerminator()) {
494 if (searchSuccBBs(MBB, I))
496 } else if (searchForward(MBB, I)) {
501 // Bundle the NOP to the instruction with the delay slot.
502 const MipsInstrInfo *TII =
503 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
504 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
505 MIBundleBuilder(MBB, I, std::next(I, 2));
511 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
512 /// slots in Mips MachineFunctions
513 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
514 return new Filler(tm);
517 template<typename IterTy>
518 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
519 RegDefsUses &RegDU, InspectMemInstr& IM,
520 IterTy &Filler) const {
521 for (IterTy I = Begin; I != End; ++I) {
523 if (I->isDebugValue())
526 if (terminateSearch(*I))
529 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
530 "Cannot put calls, returns or branches in delay slot.");
532 if (delayHasHazard(*I, RegDU, IM))
535 if (TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
536 // In NaCl, instructions that must be masked are forbidden in delay slots.
537 // We only check for loads, stores and SP changes. Calls, returns and
538 // branches are not checked because non-NaCl targets never put them in
541 if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx)
542 && baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg()))
543 || I->modifiesRegister(Mips::SP, TM.getRegisterInfo()))
554 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
555 if (DisableBackwardSearch)
558 RegDefsUses RegDU(TM);
559 MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
564 if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler))
567 MBB.splice(std::next(Slot), &MBB, std::next(Filler).base());
568 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
573 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
574 // Can handle only calls.
575 if (DisableForwardSearch || !Slot->isCall())
578 RegDefsUses RegDU(TM);
582 RegDU.setCallerSaved(*Slot);
584 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Filler))
587 MBB.splice(std::next(Slot), &MBB, Filler);
588 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
593 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
594 if (DisableSuccBBSearch)
597 MachineBasicBlock *SuccBB = selectSuccBB(MBB);
602 RegDefsUses RegDU(TM);
603 bool HasMultipleSuccs = false;
605 OwningPtr<InspectMemInstr> IM;
608 // Iterate over SuccBB's predecessor list.
609 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
610 PE = SuccBB->pred_end(); PI != PE; ++PI)
611 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
614 // Do not allow moving instructions which have unallocatable register operands
615 // across basic block boundaries.
616 RegDU.setUnallocatableRegs(*MBB.getParent());
618 // Only allow moving loads from stack or constants if any of the SuccBB's
619 // predecessors have multiple successors.
620 if (HasMultipleSuccs) {
621 IM.reset(new LoadFromStackOrConst());
623 const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();
624 IM.reset(new MemDefsUses(MFI));
627 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Filler))
630 insertDelayFiller(Filler, BrMap);
631 addLiveInRegs(Filler, *SuccBB);
632 Filler->eraseFromParent();
637 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
641 // Select the successor with the larget edge weight.
642 auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
643 MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(),
644 [&](const MachineBasicBlock *Dst0,
645 const MachineBasicBlock *Dst1) {
646 return Prob.getEdgeWeight(&B, Dst0) < Prob.getEdgeWeight(&B, Dst1);
648 return S->isLandingPad() ? NULL : S;
651 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
652 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
653 const MipsInstrInfo *TII =
654 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
655 MachineBasicBlock *TrueBB = 0, *FalseBB = 0;
656 SmallVector<MachineInstr*, 2> BranchInstrs;
657 SmallVector<MachineOperand, 2> Cond;
659 MipsInstrInfo::BranchType R =
660 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
662 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
663 return std::make_pair(R, (MachineInstr*)NULL);
665 if (R != MipsInstrInfo::BT_CondUncond) {
666 if (!hasUnoccupiedSlot(BranchInstrs[0]))
667 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
669 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
671 return std::make_pair(R, BranchInstrs[0]);
674 assert((TrueBB == &Dst) || (FalseBB == &Dst));
676 // Examine the conditional branch. See if its slot is occupied.
677 if (hasUnoccupiedSlot(BranchInstrs[0]))
678 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
680 // If that fails, try the unconditional branch.
681 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
682 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
684 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
687 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
688 RegDefsUses &RegDU, bool &HasMultipleSuccs,
689 BB2BrMap &BrMap) const {
690 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
691 getBranch(Pred, Succ);
693 // Return if either getBranch wasn't able to analyze the branches or there
694 // were no branches with unoccupied slots.
695 if (P.first == MipsInstrInfo::BT_None)
698 if ((P.first != MipsInstrInfo::BT_Uncond) &&
699 (P.first != MipsInstrInfo::BT_NoBranch)) {
700 HasMultipleSuccs = true;
701 RegDU.addLiveOut(Pred, Succ);
704 BrMap[&Pred] = P.second;
708 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
709 InspectMemInstr &IM) const {
710 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
712 HasHazard |= IM.hasHazard(Candidate);
713 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
718 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
719 return (Candidate.isTerminator() || Candidate.isCall() ||
720 Candidate.isPosition() || Candidate.isInlineAsm() ||
721 Candidate.hasUnmodeledSideEffects());