1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/MipsMCNaCl.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
35 #define DEBUG_TYPE "delay-slot-filler"
37 STATISTIC(FilledSlots, "Number of delay slots filled");
38 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
41 static cl::opt<bool> DisableDelaySlotFiller(
42 "disable-mips-delay-filler",
44 cl::desc("Fill all delay slots with NOPs."),
47 static cl::opt<bool> DisableForwardSearch(
48 "disable-mips-df-forward-search",
50 cl::desc("Disallow MIPS delay filler to search forward."),
53 static cl::opt<bool> DisableSuccBBSearch(
54 "disable-mips-df-succbb-search",
56 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
59 static cl::opt<bool> DisableBackwardSearch(
60 "disable-mips-df-backward-search",
62 cl::desc("Disallow MIPS delay filler to search backward."),
66 typedef MachineBasicBlock::iterator Iter;
67 typedef MachineBasicBlock::reverse_iterator ReverseIter;
68 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
72 RegDefsUses(TargetMachine &TM);
73 void init(const MachineInstr &MI);
75 /// This function sets all caller-saved registers in Defs.
76 void setCallerSaved(const MachineInstr &MI);
78 /// This function sets all unallocatable registers in Defs.
79 void setUnallocatableRegs(const MachineFunction &MF);
81 /// Set bits in Uses corresponding to MBB's live-out registers except for
82 /// the registers that are live-in to SuccBB.
83 void addLiveOut(const MachineBasicBlock &MBB,
84 const MachineBasicBlock &SuccBB);
86 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
89 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
92 /// Returns true if Reg or its alias is in RegSet.
93 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
95 const TargetRegisterInfo &TRI;
99 /// Base class for inspecting loads and stores.
100 class InspectMemInstr {
102 InspectMemInstr(bool ForbidMemInstr_)
103 : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
104 SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
106 /// Return true if MI cannot be moved to delay slot.
107 bool hasHazard(const MachineInstr &MI);
109 virtual ~InspectMemInstr() {}
112 /// Flags indicating whether loads or stores have been seen.
113 bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
115 /// Memory instructions are not allowed to move to delay slot if this flag
120 virtual bool hasHazard_(const MachineInstr &MI) = 0;
123 /// This subclass rejects any memory instructions.
124 class NoMemInstr : public InspectMemInstr {
126 NoMemInstr() : InspectMemInstr(true) {}
128 bool hasHazard_(const MachineInstr &MI) override { return true; }
131 /// This subclass accepts loads from stacks and constant loads.
132 class LoadFromStackOrConst : public InspectMemInstr {
134 LoadFromStackOrConst() : InspectMemInstr(false) {}
136 bool hasHazard_(const MachineInstr &MI) override;
139 /// This subclass uses memory dependence information to determine whether a
140 /// memory instruction can be moved to a delay slot.
141 class MemDefsUses : public InspectMemInstr {
143 MemDefsUses(const MachineFrameInfo *MFI);
146 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
148 bool hasHazard_(const MachineInstr &MI) override;
150 /// Update Defs and Uses. Return true if there exist dependences that
151 /// disqualify the delay slot candidate between V and values in Uses and
153 bool updateDefsUses(ValueType V, bool MayStore);
155 /// Get the list of underlying objects of MI's memory operand.
156 bool getUnderlyingObjects(const MachineInstr &MI,
157 SmallVectorImpl<ValueType> &Objects) const;
159 const MachineFrameInfo *MFI;
160 SmallPtrSet<ValueType, 4> Uses, Defs;
162 /// Flags indicating whether loads or stores with no underlying objects have
164 bool SeenNoObjLoad, SeenNoObjStore;
167 class Filler : public MachineFunctionPass {
169 Filler(TargetMachine &tm)
170 : MachineFunctionPass(ID), TM(tm) { }
172 const char *getPassName() const override {
173 return "Mips Delay Slot Filler";
176 bool runOnMachineFunction(MachineFunction &F) override {
177 bool Changed = false;
178 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
180 Changed |= runOnMachineBasicBlock(*FI);
182 // This pass invalidates liveness information when it reorders
183 // instructions to fill delay slot. Without this, -verify-machineinstrs
186 F.getRegInfo().invalidateLiveness();
191 void getAnalysisUsage(AnalysisUsage &AU) const override {
192 AU.addRequired<MachineBranchProbabilityInfo>();
193 MachineFunctionPass::getAnalysisUsage(AU);
197 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
199 /// This function checks if it is valid to move Candidate to the delay slot
200 /// and returns true if it isn't. It also updates memory and register
201 /// dependence information.
202 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
203 InspectMemInstr &IM) const;
205 /// This function searches range [Begin, End) for an instruction that can be
206 /// moved to the delay slot. Returns true on success.
207 template<typename IterTy>
208 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
209 RegDefsUses &RegDU, InspectMemInstr &IM,
210 IterTy &Filler) const;
212 /// This function searches in the backward direction for an instruction that
213 /// can be moved to the delay slot. Returns true on success.
214 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
216 /// This function searches MBB in the forward direction for an instruction
217 /// that can be moved to the delay slot. Returns true on success.
218 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
220 /// This function searches one of MBB's successor blocks for an instruction
221 /// that can be moved to the delay slot and inserts clones of the
222 /// instruction into the successor's predecessor blocks.
223 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
225 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
226 /// successor block that is not a landing pad.
227 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
229 /// This function analyzes MBB and returns an instruction with an unoccupied
230 /// slot that branches to Dst.
231 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
232 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
234 /// Examine Pred and see if it is possible to insert an instruction into
235 /// one of its branches delay slot or its end.
236 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
237 RegDefsUses &RegDU, bool &HasMultipleSuccs,
238 BB2BrMap &BrMap) const;
240 bool terminateSearch(const MachineInstr &Candidate) const;
247 } // end of anonymous namespace
249 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
250 return MI->hasDelaySlot() && !MI->isBundledWithSucc();
253 /// This function inserts clones of Filler into predecessor blocks.
254 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
255 MachineFunction *MF = Filler->getParent()->getParent();
257 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
259 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
262 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
267 /// This function adds registers Filler defines to MBB's live-in register list.
268 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
269 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
270 const MachineOperand &MO = Filler->getOperand(I);
273 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
277 const MachineFunction &MF = *MBB.getParent();
278 assert(MF.getTarget()
281 ->getAllocatableSet(MF)
283 "Shouldn't move an instruction with unallocatable registers across "
284 "basic block boundaries.");
287 if (!MBB.isLiveIn(R))
292 RegDefsUses::RegDefsUses(TargetMachine &TM)
293 : TRI(*TM.getSubtargetImpl()->getRegisterInfo()),
294 Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
296 void RegDefsUses::init(const MachineInstr &MI) {
297 // Add all register operands which are explicit and non-variadic.
298 update(MI, 0, MI.getDesc().getNumOperands());
300 // If MI is a call, add RA to Defs to prevent users of RA from going into
305 // Add all implicit register operands of branch instructions except
308 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
309 Defs.reset(Mips::AT);
313 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
316 // If MI is a call, add all caller-saved registers to Defs.
317 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
319 CallerSavedRegs.reset(Mips::ZERO);
320 CallerSavedRegs.reset(Mips::ZERO_64);
322 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
323 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
324 CallerSavedRegs.reset(*AI);
326 Defs |= CallerSavedRegs;
329 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
330 BitVector AllocSet = TRI.getAllocatableSet(MF);
332 for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
333 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
336 AllocSet.set(Mips::ZERO);
337 AllocSet.set(Mips::ZERO_64);
339 Defs |= AllocSet.flip();
342 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
343 const MachineBasicBlock &SuccBB) {
344 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
345 SE = MBB.succ_end(); SI != SE; ++SI)
347 for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
348 LE = (*SI)->livein_end(); LI != LE; ++LI)
352 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
353 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
354 bool HasHazard = false;
356 for (unsigned I = Begin; I != End; ++I) {
357 const MachineOperand &MO = MI.getOperand(I);
359 if (MO.isReg() && MO.getReg())
360 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
369 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
370 unsigned Reg, bool IsDef) const {
373 // check whether Reg has already been defined or used.
374 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
378 // check whether Reg has already been defined.
379 return isRegInSet(Defs, Reg);
382 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
383 // Check Reg and all aliased Registers.
384 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
385 if (RegSet.test(*AI))
390 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
391 if (!MI.mayStore() && !MI.mayLoad())
397 OrigSeenLoad = SeenLoad;
398 OrigSeenStore = SeenStore;
399 SeenLoad |= MI.mayLoad();
400 SeenStore |= MI.mayStore();
402 // If MI is an ordered or volatile memory reference, disallow moving
403 // subsequent loads and stores to delay slot.
404 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
405 ForbidMemInstr = true;
409 return hasHazard_(MI);
412 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
416 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue())
419 if (const PseudoSourceValue *PSV =
420 (*MI.memoperands_begin())->getPseudoValue()) {
421 if (isa<FixedStackPseudoSourceValue>(PSV))
423 return !PSV->isConstant(nullptr) && PSV != PseudoSourceValue::getStack();
429 MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
430 : InspectMemInstr(false), MFI(MFI_), SeenNoObjLoad(false),
431 SeenNoObjStore(false) {}
433 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
434 bool HasHazard = false;
435 SmallVector<ValueType, 4> Objs;
437 // Check underlying object list.
438 if (getUnderlyingObjects(MI, Objs)) {
439 for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin();
440 I != Objs.end(); ++I)
441 HasHazard |= updateDefsUses(*I, MI.mayStore());
446 // No underlying objects found.
447 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
448 HasHazard |= MI.mayLoad() || OrigSeenStore;
450 SeenNoObjLoad |= MI.mayLoad();
451 SeenNoObjStore |= MI.mayStore();
456 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) {
458 return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
461 return Defs.count(V) || SeenNoObjStore;
465 getUnderlyingObjects(const MachineInstr &MI,
466 SmallVectorImpl<ValueType> &Objects) const {
467 if (!MI.hasOneMemOperand() ||
468 (!(*MI.memoperands_begin())->getValue() &&
469 !(*MI.memoperands_begin())->getPseudoValue()))
472 if (const PseudoSourceValue *PSV =
473 (*MI.memoperands_begin())->getPseudoValue()) {
474 if (!PSV->isAliased(MFI))
476 Objects.push_back(PSV);
480 const Value *V = (*MI.memoperands_begin())->getValue();
482 SmallVector<Value *, 4> Objs;
483 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
485 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end();
487 if (!isIdentifiedObject(V))
490 Objects.push_back(*I);
496 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
497 /// We assume there is only one delay slot per delayed instruction.
498 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
499 bool Changed = false;
501 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
502 if (!hasUnoccupiedSlot(&*I))
508 // Delay slot filling is disabled at -O0.
509 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
510 if (searchBackward(MBB, I))
513 if (I->isTerminator()) {
514 if (searchSuccBBs(MBB, I))
516 } else if (searchForward(MBB, I)) {
521 // Bundle the NOP to the instruction with the delay slot.
522 const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
523 TM.getSubtargetImpl()->getInstrInfo());
524 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
525 MIBundleBuilder(MBB, I, std::next(I, 2));
531 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
532 /// slots in Mips MachineFunctions
533 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
534 return new Filler(tm);
537 template<typename IterTy>
538 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
539 RegDefsUses &RegDU, InspectMemInstr& IM,
540 IterTy &Filler) const {
541 for (IterTy I = Begin; I != End; ++I) {
543 if (I->isDebugValue())
546 if (terminateSearch(*I))
549 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
550 "Cannot put calls, returns or branches in delay slot.");
552 if (delayHasHazard(*I, RegDU, IM))
555 if (TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
556 // In NaCl, instructions that must be masked are forbidden in delay slots.
557 // We only check for loads, stores and SP changes. Calls, returns and
558 // branches are not checked because non-NaCl targets never put them in
561 if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) &&
562 baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) ||
563 I->modifiesRegister(Mips::SP,
564 TM.getSubtargetImpl()->getRegisterInfo()))
575 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
576 if (DisableBackwardSearch)
579 RegDefsUses RegDU(TM);
580 MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
585 if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler))
588 MBB.splice(std::next(Slot), &MBB, std::next(Filler).base());
589 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
594 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
595 // Can handle only calls.
596 if (DisableForwardSearch || !Slot->isCall())
599 RegDefsUses RegDU(TM);
603 RegDU.setCallerSaved(*Slot);
605 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Filler))
608 MBB.splice(std::next(Slot), &MBB, Filler);
609 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
614 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
615 if (DisableSuccBBSearch)
618 MachineBasicBlock *SuccBB = selectSuccBB(MBB);
623 RegDefsUses RegDU(TM);
624 bool HasMultipleSuccs = false;
626 std::unique_ptr<InspectMemInstr> IM;
629 // Iterate over SuccBB's predecessor list.
630 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
631 PE = SuccBB->pred_end(); PI != PE; ++PI)
632 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
635 // Do not allow moving instructions which have unallocatable register operands
636 // across basic block boundaries.
637 RegDU.setUnallocatableRegs(*MBB.getParent());
639 // Only allow moving loads from stack or constants if any of the SuccBB's
640 // predecessors have multiple successors.
641 if (HasMultipleSuccs) {
642 IM.reset(new LoadFromStackOrConst());
644 const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();
645 IM.reset(new MemDefsUses(MFI));
648 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Filler))
651 insertDelayFiller(Filler, BrMap);
652 addLiveInRegs(Filler, *SuccBB);
653 Filler->eraseFromParent();
658 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
662 // Select the successor with the larget edge weight.
663 auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
664 MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(),
665 [&](const MachineBasicBlock *Dst0,
666 const MachineBasicBlock *Dst1) {
667 return Prob.getEdgeWeight(&B, Dst0) < Prob.getEdgeWeight(&B, Dst1);
669 return S->isLandingPad() ? nullptr : S;
672 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
673 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
674 const MipsInstrInfo *TII =
675 static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo());
676 MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
677 SmallVector<MachineInstr*, 2> BranchInstrs;
678 SmallVector<MachineOperand, 2> Cond;
680 MipsInstrInfo::BranchType R =
681 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
683 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
684 return std::make_pair(R, nullptr);
686 if (R != MipsInstrInfo::BT_CondUncond) {
687 if (!hasUnoccupiedSlot(BranchInstrs[0]))
688 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
690 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
692 return std::make_pair(R, BranchInstrs[0]);
695 assert((TrueBB == &Dst) || (FalseBB == &Dst));
697 // Examine the conditional branch. See if its slot is occupied.
698 if (hasUnoccupiedSlot(BranchInstrs[0]))
699 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
701 // If that fails, try the unconditional branch.
702 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
703 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
705 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
708 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
709 RegDefsUses &RegDU, bool &HasMultipleSuccs,
710 BB2BrMap &BrMap) const {
711 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
712 getBranch(Pred, Succ);
714 // Return if either getBranch wasn't able to analyze the branches or there
715 // were no branches with unoccupied slots.
716 if (P.first == MipsInstrInfo::BT_None)
719 if ((P.first != MipsInstrInfo::BT_Uncond) &&
720 (P.first != MipsInstrInfo::BT_NoBranch)) {
721 HasMultipleSuccs = true;
722 RegDU.addLiveOut(Pred, Succ);
725 BrMap[&Pred] = P.second;
729 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
730 InspectMemInstr &IM) const {
731 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
733 HasHazard |= IM.hasHazard(Candidate);
734 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
739 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
740 return (Candidate.isTerminator() || Candidate.isCall() ||
741 Candidate.isPosition() || Candidate.isInlineAsm() ||
742 Candidate.hasUnmodeledSideEffects());