1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GlobalAlias.h"
17 #include "llvm/IR/GlobalVariable.h"
18 #include "llvm/Target/TargetInstrInfo.h"
24 class MipsFastISel final : public FastISel {
26 // All possible address modes.
29 typedef enum { RegBase, FrameIndexBase } BaseKind;
40 const GlobalValue *GV;
43 // Innocuous defaults for our address.
44 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
45 void setKind(BaseKind K) { Kind = K; }
46 BaseKind getKind() const { return Kind; }
47 bool isRegBase() const { return Kind == RegBase; }
48 bool isFIBase() const { return Kind == FrameIndexBase; }
49 void setReg(unsigned Reg) {
50 assert(isRegBase() && "Invalid base register access!");
53 unsigned getReg() const {
54 assert(isRegBase() && "Invalid base register access!");
57 void setFI(unsigned FI) {
58 assert(isFIBase() && "Invalid base frame index access!");
61 unsigned getFI() const {
62 assert(isFIBase() && "Invalid base frame index access!");
66 void setOffset(int64_t Offset_) { Offset = Offset_; }
67 int64_t getOffset() const { return Offset; }
68 void setGlobalValue(const GlobalValue *G) { GV = G; }
69 const GlobalValue *getGlobalValue() { return GV; }
72 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
73 /// make the right decision when generating code for different targets.
74 const TargetMachine &TM;
75 const MipsSubtarget *Subtarget;
76 const TargetInstrInfo &TII;
77 const TargetLowering &TLI;
78 MipsFunctionInfo *MFI;
80 // Convenience variables to avoid some queries.
83 bool fastLowerCall(CallLoweringInfo &CLI) override;
86 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
87 // floating point but not reject doing fast-isel in other
91 // Selection routines.
92 bool selectLogicalOp(const Instruction *I);
93 bool selectLoad(const Instruction *I);
94 bool selectStore(const Instruction *I);
95 bool selectBranch(const Instruction *I);
96 bool selectCmp(const Instruction *I);
97 bool selectFPExt(const Instruction *I);
98 bool selectFPTrunc(const Instruction *I);
99 bool selectFPToInt(const Instruction *I, bool IsSigned);
100 bool selectRet(const Instruction *I);
101 bool selectTrunc(const Instruction *I);
102 bool selectIntExt(const Instruction *I);
103 bool selectShift(const Instruction *I);
105 // Utility helper routines.
106 bool isTypeLegal(Type *Ty, MVT &VT);
107 bool isTypeSupported(Type *Ty, MVT &VT);
108 bool isLoadTypeLegal(Type *Ty, MVT &VT);
109 bool computeAddress(const Value *Obj, Address &Addr);
110 bool computeCallAddress(const Value *V, Address &Addr);
111 void simplifyAddress(Address &Addr);
113 // Emit helper routines.
114 bool emitCmp(unsigned DestReg, const CmpInst *CI);
115 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
116 unsigned Alignment = 0);
117 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
118 MachineMemOperand *MMO = nullptr);
119 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
120 unsigned Alignment = 0);
121 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
122 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
125 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
127 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
128 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
130 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
133 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
135 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
138 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
139 unsigned materializeGV(const GlobalValue *GV, MVT VT);
140 unsigned materializeInt(const Constant *C, MVT VT);
141 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
143 MachineInstrBuilder emitInst(unsigned Opc) {
144 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
146 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
147 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
150 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
151 unsigned MemReg, int64_t MemOffset) {
152 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
154 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
155 unsigned MemReg, int64_t MemOffset) {
156 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
158 // for some reason, this default is not generated by tablegen
159 // so we explicitly generate it here.
161 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
162 unsigned Op0, bool Op0IsKill, uint64_t imm1,
163 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
167 // Call handling routines.
169 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
170 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
172 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
175 // Backend specific FastISel code.
176 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
177 const TargetLibraryInfo *libInfo)
178 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
179 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
180 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
181 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
182 Context = &funcInfo.Fn->getContext();
184 ((TM.getRelocationModel() == Reloc::PIC_) &&
185 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
186 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
187 UnsupportedFPMode = Subtarget->isFP64bit();
190 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
191 unsigned fastMaterializeConstant(const Constant *C) override;
192 bool fastSelectInstruction(const Instruction *I) override;
194 #include "MipsGenFastISel.inc"
196 } // end anonymous namespace.
198 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
199 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
200 CCState &State) LLVM_ATTRIBUTE_UNUSED;
202 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
203 CCValAssign::LocInfo LocInfo,
204 ISD::ArgFlagsTy ArgFlags, CCState &State) {
205 llvm_unreachable("should not be called");
208 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
209 CCValAssign::LocInfo LocInfo,
210 ISD::ArgFlagsTy ArgFlags, CCState &State) {
211 llvm_unreachable("should not be called");
214 #include "MipsGenCallingConv.inc"
216 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
220 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
221 const Value *LHS, const Value *RHS) {
222 // Canonicalize immediates to the RHS first.
223 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
227 if (ISDOpc == ISD::AND) {
229 } else if (ISDOpc == ISD::OR) {
231 } else if (ISDOpc == ISD::XOR) {
234 llvm_unreachable("unexpected opcode");
236 unsigned LHSReg = getRegForValue(LHS);
237 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
245 if (const auto *C = dyn_cast<ConstantInt>(RHS))
246 RHSReg = materializeInt(C, MVT::i32);
248 RHSReg = getRegForValue(RHS);
253 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
257 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
258 assert(TLI.getValueType(AI->getType(), true) == MVT::i32 &&
259 "Alloca should always return a pointer.");
261 DenseMap<const AllocaInst *, int>::iterator SI =
262 FuncInfo.StaticAllocaMap.find(AI);
264 if (SI != FuncInfo.StaticAllocaMap.end()) {
265 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
268 .addFrameIndex(SI->second)
276 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
277 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
279 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
280 const ConstantInt *CI = cast<ConstantInt>(C);
282 if ((VT != MVT::i1) && CI->isNegative())
283 Imm = CI->getSExtValue();
285 Imm = CI->getZExtValue();
286 return materialize32BitInt(Imm, RC);
289 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
290 const TargetRegisterClass *RC) {
291 unsigned ResultReg = createResultReg(RC);
293 if (isInt<16>(Imm)) {
294 unsigned Opc = Mips::ADDiu;
295 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
297 } else if (isUInt<16>(Imm)) {
298 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
301 unsigned Lo = Imm & 0xFFFF;
302 unsigned Hi = (Imm >> 16) & 0xFFFF;
304 // Both Lo and Hi have nonzero bits.
305 unsigned TmpReg = createResultReg(RC);
306 emitInst(Mips::LUi, TmpReg).addImm(Hi);
307 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
309 emitInst(Mips::LUi, ResultReg).addImm(Hi);
314 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
315 if (UnsupportedFPMode)
317 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
318 if (VT == MVT::f32) {
319 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
320 unsigned DestReg = createResultReg(RC);
321 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
322 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
324 } else if (VT == MVT::f64) {
325 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
326 unsigned DestReg = createResultReg(RC);
327 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
329 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
330 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
336 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
337 // For now 32-bit only.
340 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
341 unsigned DestReg = createResultReg(RC);
342 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
343 bool IsThreadLocal = GVar && GVar->isThreadLocal();
344 // TLS not supported at this time.
347 emitInst(Mips::LW, DestReg)
348 .addReg(MFI->getGlobalBaseReg())
349 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
350 if ((GV->hasInternalLinkage() ||
351 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
352 unsigned TempReg = createResultReg(RC);
353 emitInst(Mips::ADDiu, TempReg)
355 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
361 // Materialize a constant into a register, and return the register
362 // number (or zero if we failed to handle it).
363 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
364 EVT CEVT = TLI.getValueType(C->getType(), true);
366 // Only handle simple types.
367 if (!CEVT.isSimple())
369 MVT VT = CEVT.getSimpleVT();
371 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
372 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
373 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
374 return materializeGV(GV, VT);
375 else if (isa<ConstantInt>(C))
376 return materializeInt(C, VT);
381 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
383 const User *U = nullptr;
384 unsigned Opcode = Instruction::UserOp1;
385 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
386 // Don't walk into other basic blocks unless the object is an alloca from
387 // another block, otherwise it may not have a virtual register assigned.
388 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
389 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
390 Opcode = I->getOpcode();
393 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
394 Opcode = C->getOpcode();
400 case Instruction::BitCast: {
401 // Look through bitcasts.
402 return computeAddress(U->getOperand(0), Addr);
404 case Instruction::GetElementPtr: {
405 Address SavedAddr = Addr;
406 uint64_t TmpOffset = Addr.getOffset();
407 // Iterate through the GEP folding the constants into offsets where
409 gep_type_iterator GTI = gep_type_begin(U);
410 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
412 const Value *Op = *i;
413 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
414 const StructLayout *SL = DL.getStructLayout(STy);
415 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
416 TmpOffset += SL->getElementOffset(Idx);
418 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
420 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
421 // Constant-offset addressing.
422 TmpOffset += CI->getSExtValue() * S;
425 if (canFoldAddIntoGEP(U, Op)) {
426 // A compatible add with a constant operand. Fold the constant.
428 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
429 TmpOffset += CI->getSExtValue() * S;
430 // Iterate on the other operand.
431 Op = cast<AddOperator>(Op)->getOperand(0);
435 goto unsupported_gep;
439 // Try to grab the base operand now.
440 Addr.setOffset(TmpOffset);
441 if (computeAddress(U->getOperand(0), Addr))
443 // We failed, restore everything and try the other options.
448 case Instruction::Alloca: {
449 const AllocaInst *AI = cast<AllocaInst>(Obj);
450 DenseMap<const AllocaInst *, int>::iterator SI =
451 FuncInfo.StaticAllocaMap.find(AI);
452 if (SI != FuncInfo.StaticAllocaMap.end()) {
453 Addr.setKind(Address::FrameIndexBase);
454 Addr.setFI(SI->second);
460 Addr.setReg(getRegForValue(Obj));
461 return Addr.getReg() != 0;
464 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
465 const GlobalValue *GV = dyn_cast<GlobalValue>(V);
466 if (GV && isa<Function>(GV) && cast<Function>(GV)->isIntrinsic())
470 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
471 Addr.setGlobalValue(GV);
477 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
478 EVT evt = TLI.getValueType(Ty, true);
479 // Only handle simple types.
480 if (evt == MVT::Other || !evt.isSimple())
482 VT = evt.getSimpleVT();
484 // Handle all legal types, i.e. a register that will directly hold this
486 return TLI.isTypeLegal(VT);
489 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
490 if (Ty->isVectorTy())
493 if (isTypeLegal(Ty, VT))
496 // If this is a type than can be sign or zero-extended to a basic operation
497 // go ahead and accept it now.
498 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
504 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
505 if (isTypeLegal(Ty, VT))
507 // We will extend this in a later patch:
508 // If this is a type than can be sign or zero-extended to a basic operation
509 // go ahead and accept it now.
510 if (VT == MVT::i8 || VT == MVT::i16)
514 // Because of how EmitCmp is called with fast-isel, you can
515 // end up with redundant "andi" instructions after the sequences emitted below.
516 // We should try and solve this issue in the future.
518 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
519 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
520 bool IsUnsigned = CI->isUnsigned();
521 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
524 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
527 CmpInst::Predicate P = CI->getPredicate();
532 case CmpInst::ICMP_EQ: {
533 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
534 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
535 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
538 case CmpInst::ICMP_NE: {
539 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
540 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
541 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
544 case CmpInst::ICMP_UGT: {
545 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
548 case CmpInst::ICMP_ULT: {
549 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
552 case CmpInst::ICMP_UGE: {
553 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
554 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
555 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
558 case CmpInst::ICMP_ULE: {
559 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
560 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
561 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
564 case CmpInst::ICMP_SGT: {
565 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
568 case CmpInst::ICMP_SLT: {
569 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
572 case CmpInst::ICMP_SGE: {
573 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
574 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
575 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
578 case CmpInst::ICMP_SLE: {
579 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
580 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
581 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
584 case CmpInst::FCMP_OEQ:
585 case CmpInst::FCMP_UNE:
586 case CmpInst::FCMP_OLT:
587 case CmpInst::FCMP_OLE:
588 case CmpInst::FCMP_OGT:
589 case CmpInst::FCMP_OGE: {
590 if (UnsupportedFPMode)
592 bool IsFloat = Left->getType()->isFloatTy();
593 bool IsDouble = Left->getType()->isDoubleTy();
594 if (!IsFloat && !IsDouble)
596 unsigned Opc, CondMovOpc;
598 case CmpInst::FCMP_OEQ:
599 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
600 CondMovOpc = Mips::MOVT_I;
602 case CmpInst::FCMP_UNE:
603 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
604 CondMovOpc = Mips::MOVF_I;
606 case CmpInst::FCMP_OLT:
607 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
608 CondMovOpc = Mips::MOVT_I;
610 case CmpInst::FCMP_OLE:
611 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
612 CondMovOpc = Mips::MOVT_I;
614 case CmpInst::FCMP_OGT:
615 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
616 CondMovOpc = Mips::MOVF_I;
618 case CmpInst::FCMP_OGE:
619 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
620 CondMovOpc = Mips::MOVF_I;
623 llvm_unreachable("Only switching of a subset of CCs.");
625 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
626 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
627 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
628 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
629 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
630 Mips::FCC0, RegState::ImplicitDefine);
631 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
634 .addReg(RegWithZero, RegState::Implicit);
635 MI->tieOperands(0, 3);
641 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
642 unsigned Alignment) {
644 // more cases will be handled here in following patches.
647 switch (VT.SimpleTy) {
649 ResultReg = createResultReg(&Mips::GPR32RegClass);
654 ResultReg = createResultReg(&Mips::GPR32RegClass);
659 ResultReg = createResultReg(&Mips::GPR32RegClass);
664 if (UnsupportedFPMode)
666 ResultReg = createResultReg(&Mips::FGR32RegClass);
671 if (UnsupportedFPMode)
673 ResultReg = createResultReg(&Mips::AFGR64RegClass);
680 if (Addr.isRegBase()) {
681 simplifyAddress(Addr);
682 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
685 if (Addr.isFIBase()) {
686 unsigned FI = Addr.getFI();
688 unsigned Offset = Addr.getOffset();
689 MachineFrameInfo &MFI = *MF->getFrameInfo();
690 MachineMemOperand *MMO = MF->getMachineMemOperand(
691 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
692 MFI.getObjectSize(FI), Align);
693 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
702 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
703 unsigned Alignment) {
705 // more cases will be handled here in following patches.
708 switch (VT.SimpleTy) {
719 if (UnsupportedFPMode)
724 if (UnsupportedFPMode)
731 if (Addr.isRegBase()) {
732 simplifyAddress(Addr);
733 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
736 if (Addr.isFIBase()) {
737 unsigned FI = Addr.getFI();
739 unsigned Offset = Addr.getOffset();
740 MachineFrameInfo &MFI = *MF->getFrameInfo();
741 MachineMemOperand *MMO = MF->getMachineMemOperand(
742 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
743 MFI.getObjectSize(FI), Align);
744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
754 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
756 if (!isTypeSupported(I->getType(), VT))
760 switch (I->getOpcode()) {
762 llvm_unreachable("Unexpected instruction.");
763 case Instruction::And:
764 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
766 case Instruction::Or:
767 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
769 case Instruction::Xor:
770 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
777 updateValueMap(I, ResultReg);
781 bool MipsFastISel::selectLoad(const Instruction *I) {
782 // Atomic loads need special handling.
783 if (cast<LoadInst>(I)->isAtomic())
786 // Verify we have a legal type before going any further.
788 if (!isLoadTypeLegal(I->getType(), VT))
791 // See if we can handle this address.
793 if (!computeAddress(I->getOperand(0), Addr))
797 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
799 updateValueMap(I, ResultReg);
803 bool MipsFastISel::selectStore(const Instruction *I) {
804 Value *Op0 = I->getOperand(0);
807 // Atomic stores need special handling.
808 if (cast<StoreInst>(I)->isAtomic())
811 // Verify we have a legal type before going any further.
813 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
816 // Get the value to be stored into a register.
817 SrcReg = getRegForValue(Op0);
821 // See if we can handle this address.
823 if (!computeAddress(I->getOperand(1), Addr))
826 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
832 // This can cause a redundant sltiu to be generated.
833 // FIXME: try and eliminate this in a future patch.
835 bool MipsFastISel::selectBranch(const Instruction *I) {
836 const BranchInst *BI = cast<BranchInst>(I);
837 MachineBasicBlock *BrBB = FuncInfo.MBB;
839 // TBB is the basic block for the case where the comparison is true.
840 // FBB is the basic block for the case where the comparison is false.
841 // if (cond) goto TBB
845 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
846 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
848 // For now, just try the simplest case where it's fed by a compare.
849 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
850 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
851 if (!emitCmp(CondReg, CI))
853 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
856 fastEmitBranch(FBB, DbgLoc);
857 FuncInfo.MBB->addSuccessor(TBB);
863 bool MipsFastISel::selectCmp(const Instruction *I) {
864 const CmpInst *CI = cast<CmpInst>(I);
865 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
866 if (!emitCmp(ResultReg, CI))
868 updateValueMap(I, ResultReg);
872 // Attempt to fast-select a floating-point extend instruction.
873 bool MipsFastISel::selectFPExt(const Instruction *I) {
874 if (UnsupportedFPMode)
876 Value *Src = I->getOperand(0);
877 EVT SrcVT = TLI.getValueType(Src->getType(), true);
878 EVT DestVT = TLI.getValueType(I->getType(), true);
880 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
884 getRegForValue(Src); // his must be a 32 bit floating point register class
885 // maybe we should handle this differently
889 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
890 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
891 updateValueMap(I, DestReg);
895 // Attempt to fast-select a floating-point truncate instruction.
896 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
897 if (UnsupportedFPMode)
899 Value *Src = I->getOperand(0);
900 EVT SrcVT = TLI.getValueType(Src->getType(), true);
901 EVT DestVT = TLI.getValueType(I->getType(), true);
903 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
906 unsigned SrcReg = getRegForValue(Src);
910 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
914 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
915 updateValueMap(I, DestReg);
919 // Attempt to fast-select a floating-point-to-integer conversion.
920 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
921 if (UnsupportedFPMode)
925 return false; // We don't handle this case yet. There is no native
926 // instruction for this but it can be synthesized.
927 Type *DstTy = I->getType();
928 if (!isTypeLegal(DstTy, DstVT))
931 if (DstVT != MVT::i32)
934 Value *Src = I->getOperand(0);
935 Type *SrcTy = Src->getType();
936 if (!isTypeLegal(SrcTy, SrcVT))
939 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
942 unsigned SrcReg = getRegForValue(Src);
946 // Determine the opcode for the conversion, which takes place
947 // entirely within FPRs.
948 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
949 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
952 if (SrcVT == MVT::f32)
953 Opc = Mips::TRUNC_W_S;
955 Opc = Mips::TRUNC_W_D32;
957 // Generate the convert.
958 emitInst(Opc, TempReg).addReg(SrcReg);
960 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
962 updateValueMap(I, DestReg);
966 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
967 SmallVectorImpl<MVT> &OutVTs,
968 unsigned &NumBytes) {
969 CallingConv::ID CC = CLI.CallConv;
970 SmallVector<CCValAssign, 16> ArgLocs;
971 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
972 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
973 // Get a count of how many bytes are to be pushed on the stack.
974 NumBytes = CCInfo.getNextStackOffset();
975 // This is the minimum argument area used for A0-A3.
979 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
982 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
983 CCValAssign &VA = ArgLocs[i];
984 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
985 MVT ArgVT = OutVTs[VA.getValNo()];
989 if (ArgVT == MVT::f32) {
990 VA.convertToReg(Mips::F12);
991 } else if (ArgVT == MVT::f64) {
992 VA.convertToReg(Mips::D6);
995 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
996 if (ArgVT == MVT::f32) {
997 VA.convertToReg(Mips::F14);
998 } else if (ArgVT == MVT::f64) {
999 VA.convertToReg(Mips::D7);
1003 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1004 (ArgVT == MVT::i8)) &&
1006 switch (VA.getLocMemOffset()) {
1008 VA.convertToReg(Mips::A0);
1011 VA.convertToReg(Mips::A1);
1014 VA.convertToReg(Mips::A2);
1017 VA.convertToReg(Mips::A3);
1023 unsigned ArgReg = getRegForValue(ArgVal);
1027 // Handle arg promotion: SExt, ZExt, AExt.
1028 switch (VA.getLocInfo()) {
1029 case CCValAssign::Full:
1031 case CCValAssign::AExt:
1032 case CCValAssign::SExt: {
1033 MVT DestVT = VA.getLocVT();
1035 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1040 case CCValAssign::ZExt: {
1041 MVT DestVT = VA.getLocVT();
1043 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1049 llvm_unreachable("Unknown arg promotion!");
1052 // Now copy/store arg to correct locations.
1053 if (VA.isRegLoc() && !VA.needsCustom()) {
1054 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1055 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1056 CLI.OutRegs.push_back(VA.getLocReg());
1057 } else if (VA.needsCustom()) {
1058 llvm_unreachable("Mips does not use custom args.");
1062 // FIXME: This path will currently return false. It was copied
1063 // from the AArch64 port and should be essentially fine for Mips too.
1064 // The work to finish up this path will be done in a follow-on patch.
1066 assert(VA.isMemLoc() && "Assuming store on stack.");
1067 // Don't emit stores for undef values.
1068 if (isa<UndefValue>(ArgVal))
1071 // Need to store on the stack.
1072 // FIXME: This alignment is incorrect but this path is disabled
1073 // for now (will return false). We need to determine the right alignment
1074 // based on the normal alignment for the underlying machine type.
1076 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1078 unsigned BEAlign = 0;
1079 if (ArgSize < 8 && !Subtarget->isLittle())
1080 BEAlign = 8 - ArgSize;
1083 Addr.setKind(Address::RegBase);
1084 Addr.setReg(Mips::SP);
1085 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1087 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1088 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1089 MachinePointerInfo::getStack(Addr.getOffset()),
1090 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1092 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1093 return false; // can't store on the stack yet.
1100 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1101 unsigned NumBytes) {
1102 CallingConv::ID CC = CLI.CallConv;
1103 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1104 if (RetVT != MVT::isVoid) {
1105 SmallVector<CCValAssign, 16> RVLocs;
1106 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1107 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1109 // Only handle a single return value.
1110 if (RVLocs.size() != 1)
1112 // Copy all of the result registers out of their specified physreg.
1113 MVT CopyVT = RVLocs[0].getValVT();
1114 // Special handling for extended integers.
1115 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1118 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1121 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1122 TII.get(TargetOpcode::COPY),
1123 ResultReg).addReg(RVLocs[0].getLocReg());
1124 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1126 CLI.ResultReg = ResultReg;
1127 CLI.NumResultRegs = 1;
1132 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1133 CallingConv::ID CC = CLI.CallConv;
1134 bool IsTailCall = CLI.IsTailCall;
1135 bool IsVarArg = CLI.IsVarArg;
1136 const Value *Callee = CLI.Callee;
1137 // const char *SymName = CLI.SymName;
1139 // Allow SelectionDAG isel to handle tail calls.
1143 // Let SDISel handle vararg functions.
1147 // FIXME: Only handle *simple* calls for now.
1149 if (CLI.RetTy->isVoidTy())
1150 RetVT = MVT::isVoid;
1151 else if (!isTypeSupported(CLI.RetTy, RetVT))
1154 for (auto Flag : CLI.OutFlags)
1155 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1158 // Set up the argument vectors.
1159 SmallVector<MVT, 16> OutVTs;
1160 OutVTs.reserve(CLI.OutVals.size());
1162 for (auto *Val : CLI.OutVals) {
1164 if (!isTypeLegal(Val->getType(), VT) &&
1165 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1168 // We don't handle vector parameters yet.
1169 if (VT.isVector() || VT.getSizeInBits() > 64)
1172 OutVTs.push_back(VT);
1176 if (!computeCallAddress(Callee, Addr))
1179 // Handle the arguments now that we've gotten them.
1181 if (!processCallArgs(CLI, OutVTs, NumBytes))
1185 unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1186 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1187 MachineInstrBuilder MIB =
1188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1189 Mips::RA).addReg(Mips::T9);
1191 // Add implicit physical register uses to the call.
1192 for (auto Reg : CLI.OutRegs)
1193 MIB.addReg(Reg, RegState::Implicit);
1195 // Add a register mask with the call-preserved registers.
1196 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1197 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1201 // Finish off the call including any return values.
1202 return finishCall(CLI, RetVT, NumBytes);
1205 bool MipsFastISel::selectRet(const Instruction *I) {
1206 const Function &F = *I->getParent()->getParent();
1207 const ReturnInst *Ret = cast<ReturnInst>(I);
1209 if (!FuncInfo.CanLowerReturn)
1212 // Build a list of return value registers.
1213 SmallVector<unsigned, 4> RetRegs;
1215 if (Ret->getNumOperands() > 0) {
1216 CallingConv::ID CC = F.getCallingConv();
1217 SmallVector<ISD::OutputArg, 4> Outs;
1218 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1219 // Analyze operands of the call, assigning locations to each operand.
1220 SmallVector<CCValAssign, 16> ValLocs;
1221 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1223 CCAssignFn *RetCC = RetCC_Mips;
1224 CCInfo.AnalyzeReturn(Outs, RetCC);
1226 // Only handle a single return value for now.
1227 if (ValLocs.size() != 1)
1230 CCValAssign &VA = ValLocs[0];
1231 const Value *RV = Ret->getOperand(0);
1233 // Don't bother handling odd stuff for now.
1234 if ((VA.getLocInfo() != CCValAssign::Full) &&
1235 (VA.getLocInfo() != CCValAssign::BCvt))
1238 // Only handle register returns for now.
1242 unsigned Reg = getRegForValue(RV);
1246 unsigned SrcReg = Reg + VA.getValNo();
1247 unsigned DestReg = VA.getLocReg();
1248 // Avoid a cross-class copy. This is very unlikely.
1249 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1252 EVT RVEVT = TLI.getValueType(RV->getType());
1253 if (!RVEVT.isSimple())
1256 if (RVEVT.isVector())
1259 MVT RVVT = RVEVT.getSimpleVT();
1260 if (RVVT == MVT::f128)
1263 MVT DestVT = VA.getValVT();
1264 // Special handling for extended integers.
1265 if (RVVT != DestVT) {
1266 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1269 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1270 bool IsZExt = Outs[0].Flags.isZExt();
1271 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1279 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1281 // Add register to return instruction.
1282 RetRegs.push_back(VA.getLocReg());
1284 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1285 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1286 MIB.addReg(RetRegs[i], RegState::Implicit);
1290 bool MipsFastISel::selectTrunc(const Instruction *I) {
1291 // The high bits for a type smaller than the register size are assumed to be
1293 Value *Op = I->getOperand(0);
1296 SrcVT = TLI.getValueType(Op->getType(), true);
1297 DestVT = TLI.getValueType(I->getType(), true);
1299 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1301 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1304 unsigned SrcReg = getRegForValue(Op);
1308 // Because the high bits are undefined, a truncate doesn't generate
1310 updateValueMap(I, SrcReg);
1313 bool MipsFastISel::selectIntExt(const Instruction *I) {
1314 Type *DestTy = I->getType();
1315 Value *Src = I->getOperand(0);
1316 Type *SrcTy = Src->getType();
1318 bool isZExt = isa<ZExtInst>(I);
1319 unsigned SrcReg = getRegForValue(Src);
1323 EVT SrcEVT, DestEVT;
1324 SrcEVT = TLI.getValueType(SrcTy, true);
1325 DestEVT = TLI.getValueType(DestTy, true);
1326 if (!SrcEVT.isSimple())
1328 if (!DestEVT.isSimple())
1331 MVT SrcVT = SrcEVT.getSimpleVT();
1332 MVT DestVT = DestEVT.getSimpleVT();
1333 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1335 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1337 updateValueMap(I, ResultReg);
1340 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1343 switch (SrcVT.SimpleTy) {
1353 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1354 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1355 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1359 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1361 switch (SrcVT.SimpleTy) {
1365 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1368 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1374 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1376 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1378 if (Subtarget->hasMips32r2())
1379 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1380 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1383 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1385 switch (SrcVT.SimpleTy) {
1389 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1392 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1395 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1401 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1402 unsigned DestReg, bool IsZExt) {
1403 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1404 // DestVT are odd things, so test to make sure that they are both types we can
1405 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1406 // bail out to SelectionDAG.
1407 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1408 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1411 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1412 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1415 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1417 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1418 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1419 return Success ? DestReg : 0;
1422 bool MipsFastISel::selectShift(const Instruction *I) {
1425 if (!isTypeSupported(I->getType(), RetVT))
1428 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1432 unsigned Opcode = I->getOpcode();
1433 const Value *Op0 = I->getOperand(0);
1434 unsigned Op0Reg = getRegForValue(Op0);
1438 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1439 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1440 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1444 MVT Op0MVT = TLI.getValueType(Op0->getType(), true).getSimpleVT();
1445 bool IsZExt = Opcode == Instruction::LShr;
1446 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1452 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1453 uint64_t ShiftVal = C->getZExtValue();
1457 llvm_unreachable("Unexpected instruction.");
1458 case Instruction::Shl:
1461 case Instruction::AShr:
1464 case Instruction::LShr:
1469 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1470 updateValueMap(I, ResultReg);
1474 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1480 llvm_unreachable("Unexpected instruction.");
1481 case Instruction::Shl:
1482 Opcode = Mips::SLLV;
1484 case Instruction::AShr:
1485 Opcode = Mips::SRAV;
1487 case Instruction::LShr:
1488 Opcode = Mips::SRLV;
1492 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1493 updateValueMap(I, ResultReg);
1497 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1498 if (!TargetSupported)
1500 switch (I->getOpcode()) {
1503 case Instruction::Load:
1504 return selectLoad(I);
1505 case Instruction::Store:
1506 return selectStore(I);
1507 case Instruction::Shl:
1508 case Instruction::LShr:
1509 case Instruction::AShr:
1510 return selectShift(I);
1511 case Instruction::And:
1512 case Instruction::Or:
1513 case Instruction::Xor:
1514 return selectLogicalOp(I);
1515 case Instruction::Br:
1516 return selectBranch(I);
1517 case Instruction::Ret:
1518 return selectRet(I);
1519 case Instruction::Trunc:
1520 return selectTrunc(I);
1521 case Instruction::ZExt:
1522 case Instruction::SExt:
1523 return selectIntExt(I);
1524 case Instruction::FPTrunc:
1525 return selectFPTrunc(I);
1526 case Instruction::FPExt:
1527 return selectFPExt(I);
1528 case Instruction::FPToSI:
1529 return selectFPToInt(I, /*isSigned*/ true);
1530 case Instruction::FPToUI:
1531 return selectFPToInt(I, /*isSigned*/ false);
1532 case Instruction::ICmp:
1533 case Instruction::FCmp:
1534 return selectCmp(I);
1539 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1541 unsigned VReg = getRegForValue(V);
1544 MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1545 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1546 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1547 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1554 void MipsFastISel::simplifyAddress(Address &Addr) {
1555 if (!isInt<16>(Addr.getOffset())) {
1557 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1558 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1559 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1560 Addr.setReg(DestReg);
1566 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1567 const TargetLibraryInfo *libInfo) {
1568 return new MipsFastISel(funcInfo, libInfo);