1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
21 // All possible address modes.
22 typedef struct Address {
23 enum { RegBase, FrameIndexBase } BaseType;
32 // Innocuous defaults for our address.
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
36 class MipsFastISel final : public FastISel {
38 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39 /// make the right decision when generating code for different targets.
41 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
44 const MipsSubtarget *Subtarget;
45 MipsFunctionInfo *MFI;
47 // Convenience variables to avoid some queries.
53 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo)
55 : FastISel(funcInfo, libInfo),
56 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57 TM(funcInfo.MF->getTarget()),
58 TII(*TM.getSubtargetImpl()->getInstrInfo()),
59 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
60 Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
61 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
62 Context = &funcInfo.Fn->getContext();
63 TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
64 (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
67 bool TargetSelectInstruction(const Instruction *I) override;
68 unsigned TargetMaterializeConstant(const Constant *C) override;
70 bool ComputeAddress(const Value *Obj, Address &Addr);
73 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
74 unsigned Alignment = 0);
75 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
76 unsigned Alignment = 0);
77 bool SelectLoad(const Instruction *I);
78 bool SelectRet(const Instruction *I);
79 bool SelectStore(const Instruction *I);
81 bool isTypeLegal(Type *Ty, MVT &VT);
82 bool isLoadTypeLegal(Type *Ty, MVT &VT);
84 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
85 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
86 unsigned MaterializeInt(const Constant *C, MVT VT);
87 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
89 // for some reason, this default is not generated by tablegen
90 // so we explicitly generate it here.
92 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
93 unsigned Op0, bool Op0IsKill, uint64_t imm1,
94 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
98 MachineInstrBuilder EmitInst(unsigned Opc) {
99 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
102 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
103 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
107 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
108 unsigned MemReg, int64_t MemOffset) {
109 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
112 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
113 unsigned MemReg, int64_t MemOffset) {
114 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
117 #include "MipsGenFastISel.inc"
120 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
121 EVT evt = TLI.getValueType(Ty, true);
122 // Only handle simple types.
123 if (evt == MVT::Other || !evt.isSimple())
125 VT = evt.getSimpleVT();
127 // Handle all legal types, i.e. a register that will directly hold this
129 return TLI.isTypeLegal(VT);
132 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
133 if (isTypeLegal(Ty, VT))
135 // We will extend this in a later patch:
136 // If this is a type than can be sign or zero-extended to a basic operation
137 // go ahead and accept it now.
138 if (VT == MVT::i8 || VT == MVT::i16)
143 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
144 // This construct looks a big awkward but it is how other ports handle this
145 // and as this function is more fully completed, these cases which
146 // return false will have additional code in them.
148 if (isa<Instruction>(Obj))
150 else if (isa<ConstantExpr>(Obj))
152 Addr.Base.Reg = getRegForValue(Obj);
153 return Addr.Base.Reg != 0;
156 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
157 unsigned Alignment) {
159 // more cases will be handled here in following patches.
162 switch (VT.SimpleTy) {
164 ResultReg = createResultReg(&Mips::GPR32RegClass);
169 ResultReg = createResultReg(&Mips::GPR32RegClass);
174 ResultReg = createResultReg(&Mips::GPR32RegClass);
179 ResultReg = createResultReg(&Mips::FGR32RegClass);
184 ResultReg = createResultReg(&Mips::AFGR64RegClass);
191 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
195 // Materialize a constant into a register, and return the register
196 // number (or zero if we failed to handle it).
197 unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
198 EVT CEVT = TLI.getValueType(C->getType(), true);
200 // Only handle simple types.
201 if (!CEVT.isSimple())
203 MVT VT = CEVT.getSimpleVT();
205 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
206 return MaterializeFP(CFP, VT);
207 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
208 return MaterializeGV(GV, VT);
209 else if (isa<ConstantInt>(C))
210 return MaterializeInt(C, VT);
215 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
216 unsigned Alignment) {
218 // more cases will be handled here in following patches.
221 switch (VT.SimpleTy) {
240 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
244 bool MipsFastISel::SelectLoad(const Instruction *I) {
245 // Atomic loads need special handling.
246 if (cast<LoadInst>(I)->isAtomic())
249 // Verify we have a legal type before going any further.
251 if (!isLoadTypeLegal(I->getType(), VT))
254 // See if we can handle this address.
256 if (!ComputeAddress(I->getOperand(0), Addr))
260 if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
262 UpdateValueMap(I, ResultReg);
266 bool MipsFastISel::SelectStore(const Instruction *I) {
267 Value *Op0 = I->getOperand(0);
270 // Atomic stores need special handling.
271 if (cast<StoreInst>(I)->isAtomic())
274 // Verify we have a legal type before going any further.
276 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
279 // Get the value to be stored into a register.
280 SrcReg = getRegForValue(Op0);
284 // See if we can handle this address.
286 if (!ComputeAddress(I->getOperand(1), Addr))
289 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
294 bool MipsFastISel::SelectRet(const Instruction *I) {
295 const ReturnInst *Ret = cast<ReturnInst>(I);
297 if (!FuncInfo.CanLowerReturn)
299 if (Ret->getNumOperands() > 0) {
302 EmitInst(Mips::RetRA);
306 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
307 if (!TargetSupported)
309 switch (I->getOpcode()) {
312 case Instruction::Load:
313 return SelectLoad(I);
314 case Instruction::Store:
315 return SelectStore(I);
316 case Instruction::Ret:
323 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
324 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
325 if (VT == MVT::f32) {
326 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
327 unsigned DestReg = createResultReg(RC);
328 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
329 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
331 } else if (VT == MVT::f64) {
332 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
333 unsigned DestReg = createResultReg(RC);
334 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
336 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
337 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
343 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
344 // For now 32-bit only.
347 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
348 unsigned DestReg = createResultReg(RC);
349 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
350 bool IsThreadLocal = GVar && GVar->isThreadLocal();
351 // TLS not supported at this time.
354 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
355 GV, 0, MipsII::MO_GOT);
356 if ((GV->hasInternalLinkage() ||
357 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
358 unsigned TempReg = createResultReg(RC);
359 EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
360 GV, 0, MipsII::MO_ABS_LO);
366 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
367 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
369 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
370 const ConstantInt *CI = cast<ConstantInt>(C);
372 if ((VT != MVT::i1) && CI->isNegative())
373 Imm = CI->getSExtValue();
375 Imm = CI->getZExtValue();
376 return Materialize32BitInt(Imm, RC);
379 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
380 const TargetRegisterClass *RC) {
381 unsigned ResultReg = createResultReg(RC);
383 if (isInt<16>(Imm)) {
384 unsigned Opc = Mips::ADDiu;
385 EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
387 } else if (isUInt<16>(Imm)) {
388 EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
391 unsigned Lo = Imm & 0xFFFF;
392 unsigned Hi = (Imm >> 16) & 0xFFFF;
394 // Both Lo and Hi have nonzero bits.
395 unsigned TmpReg = createResultReg(RC);
396 EmitInst(Mips::LUi, TmpReg).addImm(Hi);
397 EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
399 EmitInst(Mips::LUi, ResultReg).addImm(Hi);
405 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
406 const TargetLibraryInfo *libInfo) {
407 return new MipsFastISel(funcInfo, libInfo);