1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Target/TargetInstrInfo.h"
26 class MipsFastISel final : public FastISel {
28 // All possible address modes.
31 typedef enum { RegBase, FrameIndexBase } BaseKind;
42 const GlobalValue *GV;
45 // Innocuous defaults for our address.
46 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
47 void setKind(BaseKind K) { Kind = K; }
48 BaseKind getKind() const { return Kind; }
49 bool isRegBase() const { return Kind == RegBase; }
50 bool isFIBase() const { return Kind == FrameIndexBase; }
51 void setReg(unsigned Reg) {
52 assert(isRegBase() && "Invalid base register access!");
55 unsigned getReg() const {
56 assert(isRegBase() && "Invalid base register access!");
59 void setFI(unsigned FI) {
60 assert(isFIBase() && "Invalid base frame index access!");
63 unsigned getFI() const {
64 assert(isFIBase() && "Invalid base frame index access!");
68 void setOffset(int64_t Offset_) { Offset = Offset_; }
69 int64_t getOffset() const { return Offset; }
70 void setGlobalValue(const GlobalValue *G) { GV = G; }
71 const GlobalValue *getGlobalValue() { return GV; }
74 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
75 /// make the right decision when generating code for different targets.
76 const TargetMachine &TM;
77 const MipsSubtarget *Subtarget;
78 const TargetInstrInfo &TII;
79 const TargetLowering &TLI;
80 MipsFunctionInfo *MFI;
82 // Convenience variables to avoid some queries.
85 bool fastLowerCall(CallLoweringInfo &CLI) override;
86 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
89 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
90 // floating point but not reject doing fast-isel in other
94 // Selection routines.
95 bool selectLogicalOp(const Instruction *I);
96 bool selectLoad(const Instruction *I);
97 bool selectStore(const Instruction *I);
98 bool selectBranch(const Instruction *I);
99 bool selectSelect(const Instruction *I);
100 bool selectCmp(const Instruction *I);
101 bool selectFPExt(const Instruction *I);
102 bool selectFPTrunc(const Instruction *I);
103 bool selectFPToInt(const Instruction *I, bool IsSigned);
104 bool selectRet(const Instruction *I);
105 bool selectTrunc(const Instruction *I);
106 bool selectIntExt(const Instruction *I);
107 bool selectShift(const Instruction *I);
108 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
110 // Utility helper routines.
111 bool isTypeLegal(Type *Ty, MVT &VT);
112 bool isTypeSupported(Type *Ty, MVT &VT);
113 bool isLoadTypeLegal(Type *Ty, MVT &VT);
114 bool computeAddress(const Value *Obj, Address &Addr);
115 bool computeCallAddress(const Value *V, Address &Addr);
116 void simplifyAddress(Address &Addr);
118 // Emit helper routines.
119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
120 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
121 unsigned Alignment = 0);
122 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
123 MachineMemOperand *MMO = nullptr);
124 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
125 unsigned Alignment = 0);
126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
138 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
140 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
143 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
144 unsigned materializeGV(const GlobalValue *GV, MVT VT);
145 unsigned materializeInt(const Constant *C, MVT VT);
146 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
147 unsigned materializeExternalCallSym(MCSymbol *Syn);
149 MachineInstrBuilder emitInst(unsigned Opc) {
150 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
153 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
156 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
157 unsigned MemReg, int64_t MemOffset) {
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
160 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
161 unsigned MemReg, int64_t MemOffset) {
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
165 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
166 const TargetRegisterClass *RC,
167 unsigned Op0, bool Op0IsKill,
168 unsigned Op1, bool Op1IsKill);
170 // for some reason, this default is not generated by tablegen
171 // so we explicitly generate it here.
173 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
174 unsigned Op0, bool Op0IsKill, uint64_t imm1,
175 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
179 // Call handling routines.
181 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
182 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
184 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
187 // Backend specific FastISel code.
188 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
189 const TargetLibraryInfo *libInfo)
190 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
191 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
193 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
194 Context = &funcInfo.Fn->getContext();
196 ((TM.getRelocationModel() == Reloc::PIC_) &&
197 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
198 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
199 UnsupportedFPMode = Subtarget->isFP64bit();
202 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
203 unsigned fastMaterializeConstant(const Constant *C) override;
204 bool fastSelectInstruction(const Instruction *I) override;
206 #include "MipsGenFastISel.inc"
208 } // end anonymous namespace.
210 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
211 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
212 CCState &State) LLVM_ATTRIBUTE_UNUSED;
214 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
215 CCValAssign::LocInfo LocInfo,
216 ISD::ArgFlagsTy ArgFlags, CCState &State) {
217 llvm_unreachable("should not be called");
220 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
221 CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
223 llvm_unreachable("should not be called");
226 #include "MipsGenCallingConv.inc"
228 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
232 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
233 const Value *LHS, const Value *RHS) {
234 // Canonicalize immediates to the RHS first.
235 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
239 if (ISDOpc == ISD::AND) {
241 } else if (ISDOpc == ISD::OR) {
243 } else if (ISDOpc == ISD::XOR) {
246 llvm_unreachable("unexpected opcode");
248 unsigned LHSReg = getRegForValue(LHS);
249 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
257 if (const auto *C = dyn_cast<ConstantInt>(RHS))
258 RHSReg = materializeInt(C, MVT::i32);
260 RHSReg = getRegForValue(RHS);
265 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
269 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
270 if (!TargetSupported)
273 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
274 "Alloca should always return a pointer.");
276 DenseMap<const AllocaInst *, int>::iterator SI =
277 FuncInfo.StaticAllocaMap.find(AI);
279 if (SI != FuncInfo.StaticAllocaMap.end()) {
280 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
281 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
283 .addFrameIndex(SI->second)
291 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
292 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
294 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
295 const ConstantInt *CI = cast<ConstantInt>(C);
296 return materialize32BitInt(CI->getZExtValue(), RC);
299 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
300 const TargetRegisterClass *RC) {
301 unsigned ResultReg = createResultReg(RC);
303 if (isInt<16>(Imm)) {
304 unsigned Opc = Mips::ADDiu;
305 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
307 } else if (isUInt<16>(Imm)) {
308 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
311 unsigned Lo = Imm & 0xFFFF;
312 unsigned Hi = (Imm >> 16) & 0xFFFF;
314 // Both Lo and Hi have nonzero bits.
315 unsigned TmpReg = createResultReg(RC);
316 emitInst(Mips::LUi, TmpReg).addImm(Hi);
317 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
319 emitInst(Mips::LUi, ResultReg).addImm(Hi);
324 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
325 if (UnsupportedFPMode)
327 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
328 if (VT == MVT::f32) {
329 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
330 unsigned DestReg = createResultReg(RC);
331 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
332 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
334 } else if (VT == MVT::f64) {
335 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
336 unsigned DestReg = createResultReg(RC);
337 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
339 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
340 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
346 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
347 // For now 32-bit only.
350 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
351 unsigned DestReg = createResultReg(RC);
352 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
353 bool IsThreadLocal = GVar && GVar->isThreadLocal();
354 // TLS not supported at this time.
357 emitInst(Mips::LW, DestReg)
358 .addReg(MFI->getGlobalBaseReg())
359 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
360 if ((GV->hasInternalLinkage() ||
361 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
362 unsigned TempReg = createResultReg(RC);
363 emitInst(Mips::ADDiu, TempReg)
365 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
371 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
372 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
373 unsigned DestReg = createResultReg(RC);
374 emitInst(Mips::LW, DestReg)
375 .addReg(MFI->getGlobalBaseReg())
376 .addSym(Sym, MipsII::MO_GOT);
380 // Materialize a constant into a register, and return the register
381 // number (or zero if we failed to handle it).
382 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
383 if (!TargetSupported)
386 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
388 // Only handle simple types.
389 if (!CEVT.isSimple())
391 MVT VT = CEVT.getSimpleVT();
393 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
394 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
395 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
396 return materializeGV(GV, VT);
397 else if (isa<ConstantInt>(C))
398 return materializeInt(C, VT);
403 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
405 const User *U = nullptr;
406 unsigned Opcode = Instruction::UserOp1;
407 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
408 // Don't walk into other basic blocks unless the object is an alloca from
409 // another block, otherwise it may not have a virtual register assigned.
410 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
411 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
412 Opcode = I->getOpcode();
415 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
416 Opcode = C->getOpcode();
422 case Instruction::BitCast: {
423 // Look through bitcasts.
424 return computeAddress(U->getOperand(0), Addr);
426 case Instruction::GetElementPtr: {
427 Address SavedAddr = Addr;
428 uint64_t TmpOffset = Addr.getOffset();
429 // Iterate through the GEP folding the constants into offsets where
431 gep_type_iterator GTI = gep_type_begin(U);
432 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
434 const Value *Op = *i;
435 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
436 const StructLayout *SL = DL.getStructLayout(STy);
437 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
438 TmpOffset += SL->getElementOffset(Idx);
440 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
442 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
443 // Constant-offset addressing.
444 TmpOffset += CI->getSExtValue() * S;
447 if (canFoldAddIntoGEP(U, Op)) {
448 // A compatible add with a constant operand. Fold the constant.
450 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
451 TmpOffset += CI->getSExtValue() * S;
452 // Iterate on the other operand.
453 Op = cast<AddOperator>(Op)->getOperand(0);
457 goto unsupported_gep;
461 // Try to grab the base operand now.
462 Addr.setOffset(TmpOffset);
463 if (computeAddress(U->getOperand(0), Addr))
465 // We failed, restore everything and try the other options.
470 case Instruction::Alloca: {
471 const AllocaInst *AI = cast<AllocaInst>(Obj);
472 DenseMap<const AllocaInst *, int>::iterator SI =
473 FuncInfo.StaticAllocaMap.find(AI);
474 if (SI != FuncInfo.StaticAllocaMap.end()) {
475 Addr.setKind(Address::FrameIndexBase);
476 Addr.setFI(SI->second);
482 Addr.setReg(getRegForValue(Obj));
483 return Addr.getReg() != 0;
486 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
487 const User *U = nullptr;
488 unsigned Opcode = Instruction::UserOp1;
490 if (const auto *I = dyn_cast<Instruction>(V)) {
491 // Check if the value is defined in the same basic block. This information
492 // is crucial to know whether or not folding an operand is valid.
493 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
494 Opcode = I->getOpcode();
497 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
498 Opcode = C->getOpcode();
505 case Instruction::BitCast:
506 // Look past bitcasts if its operand is in the same BB.
507 return computeCallAddress(U->getOperand(0), Addr);
509 case Instruction::IntToPtr:
510 // Look past no-op inttoptrs if its operand is in the same BB.
511 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
512 TLI.getPointerTy(DL))
513 return computeCallAddress(U->getOperand(0), Addr);
515 case Instruction::PtrToInt:
516 // Look past no-op ptrtoints if its operand is in the same BB.
517 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
518 return computeCallAddress(U->getOperand(0), Addr);
522 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
523 Addr.setGlobalValue(GV);
527 // If all else fails, try to materialize the value in a register.
528 if (!Addr.getGlobalValue()) {
529 Addr.setReg(getRegForValue(V));
530 return Addr.getReg() != 0;
536 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
537 EVT evt = TLI.getValueType(DL, Ty, true);
538 // Only handle simple types.
539 if (evt == MVT::Other || !evt.isSimple())
541 VT = evt.getSimpleVT();
543 // Handle all legal types, i.e. a register that will directly hold this
545 return TLI.isTypeLegal(VT);
548 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
549 if (Ty->isVectorTy())
552 if (isTypeLegal(Ty, VT))
555 // If this is a type than can be sign or zero-extended to a basic operation
556 // go ahead and accept it now.
557 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
563 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
564 if (isTypeLegal(Ty, VT))
566 // We will extend this in a later patch:
567 // If this is a type than can be sign or zero-extended to a basic operation
568 // go ahead and accept it now.
569 if (VT == MVT::i8 || VT == MVT::i16)
573 // Because of how EmitCmp is called with fast-isel, you can
574 // end up with redundant "andi" instructions after the sequences emitted below.
575 // We should try and solve this issue in the future.
577 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
578 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
579 bool IsUnsigned = CI->isUnsigned();
580 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
583 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
586 CmpInst::Predicate P = CI->getPredicate();
591 case CmpInst::ICMP_EQ: {
592 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
593 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
594 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
597 case CmpInst::ICMP_NE: {
598 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
599 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
600 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
603 case CmpInst::ICMP_UGT: {
604 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
607 case CmpInst::ICMP_ULT: {
608 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
611 case CmpInst::ICMP_UGE: {
612 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
613 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
614 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
617 case CmpInst::ICMP_ULE: {
618 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
619 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
620 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
623 case CmpInst::ICMP_SGT: {
624 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
627 case CmpInst::ICMP_SLT: {
628 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
631 case CmpInst::ICMP_SGE: {
632 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
633 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
634 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
637 case CmpInst::ICMP_SLE: {
638 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
639 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
640 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
643 case CmpInst::FCMP_OEQ:
644 case CmpInst::FCMP_UNE:
645 case CmpInst::FCMP_OLT:
646 case CmpInst::FCMP_OLE:
647 case CmpInst::FCMP_OGT:
648 case CmpInst::FCMP_OGE: {
649 if (UnsupportedFPMode)
651 bool IsFloat = Left->getType()->isFloatTy();
652 bool IsDouble = Left->getType()->isDoubleTy();
653 if (!IsFloat && !IsDouble)
655 unsigned Opc, CondMovOpc;
657 case CmpInst::FCMP_OEQ:
658 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
659 CondMovOpc = Mips::MOVT_I;
661 case CmpInst::FCMP_UNE:
662 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
663 CondMovOpc = Mips::MOVF_I;
665 case CmpInst::FCMP_OLT:
666 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
667 CondMovOpc = Mips::MOVT_I;
669 case CmpInst::FCMP_OLE:
670 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
671 CondMovOpc = Mips::MOVT_I;
673 case CmpInst::FCMP_OGT:
674 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
675 CondMovOpc = Mips::MOVF_I;
677 case CmpInst::FCMP_OGE:
678 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
679 CondMovOpc = Mips::MOVF_I;
682 llvm_unreachable("Only switching of a subset of CCs.");
684 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
685 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
686 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
687 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
688 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
689 Mips::FCC0, RegState::ImplicitDefine);
690 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
693 .addReg(RegWithZero, RegState::Implicit);
694 MI->tieOperands(0, 3);
700 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
701 unsigned Alignment) {
703 // more cases will be handled here in following patches.
706 switch (VT.SimpleTy) {
708 ResultReg = createResultReg(&Mips::GPR32RegClass);
713 ResultReg = createResultReg(&Mips::GPR32RegClass);
718 ResultReg = createResultReg(&Mips::GPR32RegClass);
723 if (UnsupportedFPMode)
725 ResultReg = createResultReg(&Mips::FGR32RegClass);
730 if (UnsupportedFPMode)
732 ResultReg = createResultReg(&Mips::AFGR64RegClass);
739 if (Addr.isRegBase()) {
740 simplifyAddress(Addr);
741 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
744 if (Addr.isFIBase()) {
745 unsigned FI = Addr.getFI();
747 unsigned Offset = Addr.getOffset();
748 MachineFrameInfo &MFI = *MF->getFrameInfo();
749 MachineMemOperand *MMO = MF->getMachineMemOperand(
750 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
751 MFI.getObjectSize(FI), Align);
752 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
761 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
762 unsigned Alignment) {
764 // more cases will be handled here in following patches.
767 switch (VT.SimpleTy) {
778 if (UnsupportedFPMode)
783 if (UnsupportedFPMode)
790 if (Addr.isRegBase()) {
791 simplifyAddress(Addr);
792 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
795 if (Addr.isFIBase()) {
796 unsigned FI = Addr.getFI();
798 unsigned Offset = Addr.getOffset();
799 MachineFrameInfo &MFI = *MF->getFrameInfo();
800 MachineMemOperand *MMO = MF->getMachineMemOperand(
801 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
802 MFI.getObjectSize(FI), Align);
803 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
813 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
815 if (!isTypeSupported(I->getType(), VT))
819 switch (I->getOpcode()) {
821 llvm_unreachable("Unexpected instruction.");
822 case Instruction::And:
823 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
825 case Instruction::Or:
826 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
828 case Instruction::Xor:
829 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
836 updateValueMap(I, ResultReg);
840 bool MipsFastISel::selectLoad(const Instruction *I) {
841 // Atomic loads need special handling.
842 if (cast<LoadInst>(I)->isAtomic())
845 // Verify we have a legal type before going any further.
847 if (!isLoadTypeLegal(I->getType(), VT))
850 // See if we can handle this address.
852 if (!computeAddress(I->getOperand(0), Addr))
856 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
858 updateValueMap(I, ResultReg);
862 bool MipsFastISel::selectStore(const Instruction *I) {
863 Value *Op0 = I->getOperand(0);
866 // Atomic stores need special handling.
867 if (cast<StoreInst>(I)->isAtomic())
870 // Verify we have a legal type before going any further.
872 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
875 // Get the value to be stored into a register.
876 SrcReg = getRegForValue(Op0);
880 // See if we can handle this address.
882 if (!computeAddress(I->getOperand(1), Addr))
885 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
891 // This can cause a redundant sltiu to be generated.
892 // FIXME: try and eliminate this in a future patch.
894 bool MipsFastISel::selectBranch(const Instruction *I) {
895 const BranchInst *BI = cast<BranchInst>(I);
896 MachineBasicBlock *BrBB = FuncInfo.MBB;
898 // TBB is the basic block for the case where the comparison is true.
899 // FBB is the basic block for the case where the comparison is false.
900 // if (cond) goto TBB
904 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
905 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
907 // For now, just try the simplest case where it's fed by a compare.
908 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
909 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
910 if (!emitCmp(CondReg, CI))
912 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
915 finishCondBranch(BI->getParent(), TBB, FBB);
921 bool MipsFastISel::selectCmp(const Instruction *I) {
922 const CmpInst *CI = cast<CmpInst>(I);
923 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
924 if (!emitCmp(ResultReg, CI))
926 updateValueMap(I, ResultReg);
930 // Attempt to fast-select a floating-point extend instruction.
931 bool MipsFastISel::selectFPExt(const Instruction *I) {
932 if (UnsupportedFPMode)
934 Value *Src = I->getOperand(0);
935 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
936 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
938 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
942 getRegForValue(Src); // his must be a 32 bit floating point register class
943 // maybe we should handle this differently
947 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
948 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
949 updateValueMap(I, DestReg);
953 bool MipsFastISel::selectSelect(const Instruction *I) {
954 assert(isa<SelectInst>(I) && "Expected a select instruction.");
957 if (!isTypeSupported(I->getType(), VT))
961 const TargetRegisterClass *RC;
963 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
964 CondMovOpc = Mips::MOVN_I_I;
965 RC = &Mips::GPR32RegClass;
966 } else if (VT == MVT::f32) {
967 CondMovOpc = Mips::MOVN_I_S;
968 RC = &Mips::FGR32RegClass;
969 } else if (VT == MVT::f64) {
970 CondMovOpc = Mips::MOVN_I_D32;
971 RC = &Mips::AFGR64RegClass;
975 const SelectInst *SI = cast<SelectInst>(I);
976 const Value *Cond = SI->getCondition();
977 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
978 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
979 unsigned CondReg = getRegForValue(Cond);
981 if (!Src1Reg || !Src2Reg || !CondReg)
984 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
988 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
991 unsigned ResultReg = createResultReg(RC);
992 unsigned TempReg = createResultReg(RC);
994 if (!ResultReg || !TempReg)
997 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
998 emitInst(CondMovOpc, ResultReg)
999 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1000 updateValueMap(I, ResultReg);
1004 // Attempt to fast-select a floating-point truncate instruction.
1005 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1006 if (UnsupportedFPMode)
1008 Value *Src = I->getOperand(0);
1009 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1010 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1012 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1015 unsigned SrcReg = getRegForValue(Src);
1019 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1023 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1024 updateValueMap(I, DestReg);
1028 // Attempt to fast-select a floating-point-to-integer conversion.
1029 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1030 if (UnsupportedFPMode)
1034 return false; // We don't handle this case yet. There is no native
1035 // instruction for this but it can be synthesized.
1036 Type *DstTy = I->getType();
1037 if (!isTypeLegal(DstTy, DstVT))
1040 if (DstVT != MVT::i32)
1043 Value *Src = I->getOperand(0);
1044 Type *SrcTy = Src->getType();
1045 if (!isTypeLegal(SrcTy, SrcVT))
1048 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1051 unsigned SrcReg = getRegForValue(Src);
1055 // Determine the opcode for the conversion, which takes place
1056 // entirely within FPRs.
1057 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1058 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1061 if (SrcVT == MVT::f32)
1062 Opc = Mips::TRUNC_W_S;
1064 Opc = Mips::TRUNC_W_D32;
1066 // Generate the convert.
1067 emitInst(Opc, TempReg).addReg(SrcReg);
1069 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1071 updateValueMap(I, DestReg);
1075 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1076 SmallVectorImpl<MVT> &OutVTs,
1077 unsigned &NumBytes) {
1078 CallingConv::ID CC = CLI.CallConv;
1079 SmallVector<CCValAssign, 16> ArgLocs;
1080 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1081 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1082 // Get a count of how many bytes are to be pushed on the stack.
1083 NumBytes = CCInfo.getNextStackOffset();
1084 // This is the minimum argument area used for A0-A3.
1088 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1089 // Process the args.
1091 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1092 CCValAssign &VA = ArgLocs[i];
1093 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1094 MVT ArgVT = OutVTs[VA.getValNo()];
1098 if (ArgVT == MVT::f32) {
1099 VA.convertToReg(Mips::F12);
1100 } else if (ArgVT == MVT::f64) {
1101 VA.convertToReg(Mips::D6);
1103 } else if (i == 1) {
1104 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1105 if (ArgVT == MVT::f32) {
1106 VA.convertToReg(Mips::F14);
1107 } else if (ArgVT == MVT::f64) {
1108 VA.convertToReg(Mips::D7);
1112 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1113 (ArgVT == MVT::i8)) &&
1115 switch (VA.getLocMemOffset()) {
1117 VA.convertToReg(Mips::A0);
1120 VA.convertToReg(Mips::A1);
1123 VA.convertToReg(Mips::A2);
1126 VA.convertToReg(Mips::A3);
1132 unsigned ArgReg = getRegForValue(ArgVal);
1136 // Handle arg promotion: SExt, ZExt, AExt.
1137 switch (VA.getLocInfo()) {
1138 case CCValAssign::Full:
1140 case CCValAssign::AExt:
1141 case CCValAssign::SExt: {
1142 MVT DestVT = VA.getLocVT();
1144 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1149 case CCValAssign::ZExt: {
1150 MVT DestVT = VA.getLocVT();
1152 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1158 llvm_unreachable("Unknown arg promotion!");
1161 // Now copy/store arg to correct locations.
1162 if (VA.isRegLoc() && !VA.needsCustom()) {
1163 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1164 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1165 CLI.OutRegs.push_back(VA.getLocReg());
1166 } else if (VA.needsCustom()) {
1167 llvm_unreachable("Mips does not use custom args.");
1171 // FIXME: This path will currently return false. It was copied
1172 // from the AArch64 port and should be essentially fine for Mips too.
1173 // The work to finish up this path will be done in a follow-on patch.
1175 assert(VA.isMemLoc() && "Assuming store on stack.");
1176 // Don't emit stores for undef values.
1177 if (isa<UndefValue>(ArgVal))
1180 // Need to store on the stack.
1181 // FIXME: This alignment is incorrect but this path is disabled
1182 // for now (will return false). We need to determine the right alignment
1183 // based on the normal alignment for the underlying machine type.
1185 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1187 unsigned BEAlign = 0;
1188 if (ArgSize < 8 && !Subtarget->isLittle())
1189 BEAlign = 8 - ArgSize;
1192 Addr.setKind(Address::RegBase);
1193 Addr.setReg(Mips::SP);
1194 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1196 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1197 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1198 MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1199 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1201 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1202 return false; // can't store on the stack yet.
1209 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1210 unsigned NumBytes) {
1211 CallingConv::ID CC = CLI.CallConv;
1212 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1213 if (RetVT != MVT::isVoid) {
1214 SmallVector<CCValAssign, 16> RVLocs;
1215 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1216 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1218 // Only handle a single return value.
1219 if (RVLocs.size() != 1)
1221 // Copy all of the result registers out of their specified physreg.
1222 MVT CopyVT = RVLocs[0].getValVT();
1223 // Special handling for extended integers.
1224 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1227 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1230 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1231 TII.get(TargetOpcode::COPY),
1232 ResultReg).addReg(RVLocs[0].getLocReg());
1233 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1235 CLI.ResultReg = ResultReg;
1236 CLI.NumResultRegs = 1;
1241 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1242 if (!TargetSupported)
1245 CallingConv::ID CC = CLI.CallConv;
1246 bool IsTailCall = CLI.IsTailCall;
1247 bool IsVarArg = CLI.IsVarArg;
1248 const Value *Callee = CLI.Callee;
1249 MCSymbol *Symbol = CLI.Symbol;
1251 // Do not handle FastCC.
1252 if (CC == CallingConv::Fast)
1255 // Allow SelectionDAG isel to handle tail calls.
1259 // Let SDISel handle vararg functions.
1263 // FIXME: Only handle *simple* calls for now.
1265 if (CLI.RetTy->isVoidTy())
1266 RetVT = MVT::isVoid;
1267 else if (!isTypeSupported(CLI.RetTy, RetVT))
1270 for (auto Flag : CLI.OutFlags)
1271 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1274 // Set up the argument vectors.
1275 SmallVector<MVT, 16> OutVTs;
1276 OutVTs.reserve(CLI.OutVals.size());
1278 for (auto *Val : CLI.OutVals) {
1280 if (!isTypeLegal(Val->getType(), VT) &&
1281 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1284 // We don't handle vector parameters yet.
1285 if (VT.isVector() || VT.getSizeInBits() > 64)
1288 OutVTs.push_back(VT);
1292 if (!computeCallAddress(Callee, Addr))
1295 // Handle the arguments now that we've gotten them.
1297 if (!processCallArgs(CLI, OutVTs, NumBytes))
1300 if (!Addr.getGlobalValue())
1304 unsigned DestAddress;
1306 DestAddress = materializeExternalCallSym(Symbol);
1308 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1309 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1310 MachineInstrBuilder MIB =
1311 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1312 Mips::RA).addReg(Mips::T9);
1314 // Add implicit physical register uses to the call.
1315 for (auto Reg : CLI.OutRegs)
1316 MIB.addReg(Reg, RegState::Implicit);
1318 // Add a register mask with the call-preserved registers.
1319 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1320 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1324 // Finish off the call including any return values.
1325 return finishCall(CLI, RetVT, NumBytes);
1328 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1329 if (!TargetSupported)
1332 switch (II->getIntrinsicID()) {
1335 case Intrinsic::bswap: {
1336 Type *RetTy = II->getCalledFunction()->getReturnType();
1339 if (!isTypeSupported(RetTy, VT))
1342 unsigned SrcReg = getRegForValue(II->getOperand(0));
1345 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1348 if (VT == MVT::i16) {
1349 if (Subtarget->hasMips32r2()) {
1350 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1351 updateValueMap(II, DestReg);
1354 unsigned TempReg[3];
1355 for (int i = 0; i < 3; i++) {
1356 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1357 if (TempReg[i] == 0)
1360 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1361 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1362 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1363 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1364 updateValueMap(II, DestReg);
1367 } else if (VT == MVT::i32) {
1368 if (Subtarget->hasMips32r2()) {
1369 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1370 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1371 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1372 updateValueMap(II, DestReg);
1375 unsigned TempReg[8];
1376 for (int i = 0; i < 8; i++) {
1377 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1378 if (TempReg[i] == 0)
1382 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1383 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1384 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1385 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1387 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1388 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1390 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1391 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1392 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1393 updateValueMap(II, DestReg);
1399 case Intrinsic::memcpy:
1400 case Intrinsic::memmove: {
1401 const auto *MTI = cast<MemTransferInst>(II);
1402 // Don't handle volatile.
1403 if (MTI->isVolatile())
1405 if (!MTI->getLength()->getType()->isIntegerTy(32))
1407 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1408 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1410 case Intrinsic::memset: {
1411 const MemSetInst *MSI = cast<MemSetInst>(II);
1412 // Don't handle volatile.
1413 if (MSI->isVolatile())
1415 if (!MSI->getLength()->getType()->isIntegerTy(32))
1417 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1423 bool MipsFastISel::selectRet(const Instruction *I) {
1424 const Function &F = *I->getParent()->getParent();
1425 const ReturnInst *Ret = cast<ReturnInst>(I);
1427 if (!FuncInfo.CanLowerReturn)
1430 // Build a list of return value registers.
1431 SmallVector<unsigned, 4> RetRegs;
1433 if (Ret->getNumOperands() > 0) {
1434 CallingConv::ID CC = F.getCallingConv();
1436 // Do not handle FastCC.
1437 if (CC == CallingConv::Fast)
1440 SmallVector<ISD::OutputArg, 4> Outs;
1441 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1443 // Analyze operands of the call, assigning locations to each operand.
1444 SmallVector<CCValAssign, 16> ValLocs;
1445 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1447 CCAssignFn *RetCC = RetCC_Mips;
1448 CCInfo.AnalyzeReturn(Outs, RetCC);
1450 // Only handle a single return value for now.
1451 if (ValLocs.size() != 1)
1454 CCValAssign &VA = ValLocs[0];
1455 const Value *RV = Ret->getOperand(0);
1457 // Don't bother handling odd stuff for now.
1458 if ((VA.getLocInfo() != CCValAssign::Full) &&
1459 (VA.getLocInfo() != CCValAssign::BCvt))
1462 // Only handle register returns for now.
1466 unsigned Reg = getRegForValue(RV);
1470 unsigned SrcReg = Reg + VA.getValNo();
1471 unsigned DestReg = VA.getLocReg();
1472 // Avoid a cross-class copy. This is very unlikely.
1473 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1476 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1477 if (!RVEVT.isSimple())
1480 if (RVEVT.isVector())
1483 MVT RVVT = RVEVT.getSimpleVT();
1484 if (RVVT == MVT::f128)
1487 MVT DestVT = VA.getValVT();
1488 // Special handling for extended integers.
1489 if (RVVT != DestVT) {
1490 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1493 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1494 bool IsZExt = Outs[0].Flags.isZExt();
1495 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1503 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1505 // Add register to return instruction.
1506 RetRegs.push_back(VA.getLocReg());
1508 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1509 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1510 MIB.addReg(RetRegs[i], RegState::Implicit);
1514 bool MipsFastISel::selectTrunc(const Instruction *I) {
1515 // The high bits for a type smaller than the register size are assumed to be
1517 Value *Op = I->getOperand(0);
1520 SrcVT = TLI.getValueType(DL, Op->getType(), true);
1521 DestVT = TLI.getValueType(DL, I->getType(), true);
1523 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1525 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1528 unsigned SrcReg = getRegForValue(Op);
1532 // Because the high bits are undefined, a truncate doesn't generate
1534 updateValueMap(I, SrcReg);
1537 bool MipsFastISel::selectIntExt(const Instruction *I) {
1538 Type *DestTy = I->getType();
1539 Value *Src = I->getOperand(0);
1540 Type *SrcTy = Src->getType();
1542 bool isZExt = isa<ZExtInst>(I);
1543 unsigned SrcReg = getRegForValue(Src);
1547 EVT SrcEVT, DestEVT;
1548 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1549 DestEVT = TLI.getValueType(DL, DestTy, true);
1550 if (!SrcEVT.isSimple())
1552 if (!DestEVT.isSimple())
1555 MVT SrcVT = SrcEVT.getSimpleVT();
1556 MVT DestVT = DestEVT.getSimpleVT();
1557 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1559 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1561 updateValueMap(I, ResultReg);
1564 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1567 switch (SrcVT.SimpleTy) {
1577 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1578 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1579 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1583 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1585 switch (SrcVT.SimpleTy) {
1589 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1592 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1598 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1600 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1602 if (Subtarget->hasMips32r2())
1603 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1604 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1607 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1609 switch (SrcVT.SimpleTy) {
1613 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1616 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1619 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1625 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1626 unsigned DestReg, bool IsZExt) {
1627 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1628 // DestVT are odd things, so test to make sure that they are both types we can
1629 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1630 // bail out to SelectionDAG.
1631 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1632 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1635 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1636 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1639 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1641 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1642 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1643 return Success ? DestReg : 0;
1646 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1647 EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1648 if (!DestEVT.isSimple())
1651 MVT DestVT = DestEVT.getSimpleVT();
1652 if (DestVT != MVT::i32)
1656 switch (ISDOpcode) {
1661 DivOpc = Mips::SDIV;
1665 DivOpc = Mips::UDIV;
1669 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1670 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1671 if (!Src0Reg || !Src1Reg)
1674 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1675 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1677 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1681 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1684 emitInst(MFOpc, ResultReg);
1686 updateValueMap(I, ResultReg);
1690 bool MipsFastISel::selectShift(const Instruction *I) {
1693 if (!isTypeSupported(I->getType(), RetVT))
1696 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1700 unsigned Opcode = I->getOpcode();
1701 const Value *Op0 = I->getOperand(0);
1702 unsigned Op0Reg = getRegForValue(Op0);
1706 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1707 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1708 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1712 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1713 bool IsZExt = Opcode == Instruction::LShr;
1714 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1720 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1721 uint64_t ShiftVal = C->getZExtValue();
1725 llvm_unreachable("Unexpected instruction.");
1726 case Instruction::Shl:
1729 case Instruction::AShr:
1732 case Instruction::LShr:
1737 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1738 updateValueMap(I, ResultReg);
1742 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1748 llvm_unreachable("Unexpected instruction.");
1749 case Instruction::Shl:
1750 Opcode = Mips::SLLV;
1752 case Instruction::AShr:
1753 Opcode = Mips::SRAV;
1755 case Instruction::LShr:
1756 Opcode = Mips::SRLV;
1760 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1761 updateValueMap(I, ResultReg);
1765 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1766 if (!TargetSupported)
1768 switch (I->getOpcode()) {
1771 case Instruction::Load:
1772 return selectLoad(I);
1773 case Instruction::Store:
1774 return selectStore(I);
1775 case Instruction::SDiv:
1776 if (!selectBinaryOp(I, ISD::SDIV))
1777 return selectDivRem(I, ISD::SDIV);
1779 case Instruction::UDiv:
1780 if (!selectBinaryOp(I, ISD::UDIV))
1781 return selectDivRem(I, ISD::UDIV);
1783 case Instruction::SRem:
1784 if (!selectBinaryOp(I, ISD::SREM))
1785 return selectDivRem(I, ISD::SREM);
1787 case Instruction::URem:
1788 if (!selectBinaryOp(I, ISD::UREM))
1789 return selectDivRem(I, ISD::UREM);
1791 case Instruction::Shl:
1792 case Instruction::LShr:
1793 case Instruction::AShr:
1794 return selectShift(I);
1795 case Instruction::And:
1796 case Instruction::Or:
1797 case Instruction::Xor:
1798 return selectLogicalOp(I);
1799 case Instruction::Br:
1800 return selectBranch(I);
1801 case Instruction::Ret:
1802 return selectRet(I);
1803 case Instruction::Trunc:
1804 return selectTrunc(I);
1805 case Instruction::ZExt:
1806 case Instruction::SExt:
1807 return selectIntExt(I);
1808 case Instruction::FPTrunc:
1809 return selectFPTrunc(I);
1810 case Instruction::FPExt:
1811 return selectFPExt(I);
1812 case Instruction::FPToSI:
1813 return selectFPToInt(I, /*isSigned*/ true);
1814 case Instruction::FPToUI:
1815 return selectFPToInt(I, /*isSigned*/ false);
1816 case Instruction::ICmp:
1817 case Instruction::FCmp:
1818 return selectCmp(I);
1819 case Instruction::Select:
1820 return selectSelect(I);
1825 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1827 unsigned VReg = getRegForValue(V);
1830 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
1831 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1832 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1833 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1840 void MipsFastISel::simplifyAddress(Address &Addr) {
1841 if (!isInt<16>(Addr.getOffset())) {
1843 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1844 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1845 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1846 Addr.setReg(DestReg);
1851 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1852 const TargetRegisterClass *RC,
1853 unsigned Op0, bool Op0IsKill,
1854 unsigned Op1, bool Op1IsKill) {
1855 // We treat the MUL instruction in a special way because it clobbers
1856 // the HI0 & LO0 registers. The TableGen definition of this instruction can
1857 // mark these registers only as implicitly defined. As a result, the
1858 // register allocator runs out of registers when this instruction is
1859 // followed by another instruction that defines the same registers too.
1860 // We can fix this by explicitly marking those registers as dead.
1861 if (MachineInstOpcode == Mips::MUL) {
1862 unsigned ResultReg = createResultReg(RC);
1863 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1864 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1865 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1867 .addReg(Op0, getKillRegState(Op0IsKill))
1868 .addReg(Op1, getKillRegState(Op1IsKill))
1869 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1870 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1874 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1879 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1880 const TargetLibraryInfo *libInfo) {
1881 return new MipsFastISel(funcInfo, libInfo);