1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Target/TargetInstrInfo.h"
26 class MipsFastISel final : public FastISel {
28 // All possible address modes.
31 typedef enum { RegBase, FrameIndexBase } BaseKind;
42 const GlobalValue *GV;
45 // Innocuous defaults for our address.
46 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
47 void setKind(BaseKind K) { Kind = K; }
48 BaseKind getKind() const { return Kind; }
49 bool isRegBase() const { return Kind == RegBase; }
50 bool isFIBase() const { return Kind == FrameIndexBase; }
51 void setReg(unsigned Reg) {
52 assert(isRegBase() && "Invalid base register access!");
55 unsigned getReg() const {
56 assert(isRegBase() && "Invalid base register access!");
59 void setFI(unsigned FI) {
60 assert(isFIBase() && "Invalid base frame index access!");
63 unsigned getFI() const {
64 assert(isFIBase() && "Invalid base frame index access!");
68 void setOffset(int64_t Offset_) { Offset = Offset_; }
69 int64_t getOffset() const { return Offset; }
70 void setGlobalValue(const GlobalValue *G) { GV = G; }
71 const GlobalValue *getGlobalValue() { return GV; }
74 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
75 /// make the right decision when generating code for different targets.
76 const TargetMachine &TM;
77 const MipsSubtarget *Subtarget;
78 const TargetInstrInfo &TII;
79 const TargetLowering &TLI;
80 MipsFunctionInfo *MFI;
82 // Convenience variables to avoid some queries.
85 bool fastLowerCall(CallLoweringInfo &CLI) override;
86 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
89 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
90 // floating point but not reject doing fast-isel in other
94 // Selection routines.
95 bool selectLogicalOp(const Instruction *I);
96 bool selectLoad(const Instruction *I);
97 bool selectStore(const Instruction *I);
98 bool selectBranch(const Instruction *I);
99 bool selectSelect(const Instruction *I);
100 bool selectCmp(const Instruction *I);
101 bool selectFPExt(const Instruction *I);
102 bool selectFPTrunc(const Instruction *I);
103 bool selectFPToInt(const Instruction *I, bool IsSigned);
104 bool selectRet(const Instruction *I);
105 bool selectTrunc(const Instruction *I);
106 bool selectIntExt(const Instruction *I);
107 bool selectShift(const Instruction *I);
108 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
110 // Utility helper routines.
111 bool isTypeLegal(Type *Ty, MVT &VT);
112 bool isTypeSupported(Type *Ty, MVT &VT);
113 bool isLoadTypeLegal(Type *Ty, MVT &VT);
114 bool computeAddress(const Value *Obj, Address &Addr);
115 bool computeCallAddress(const Value *V, Address &Addr);
116 void simplifyAddress(Address &Addr);
118 // Emit helper routines.
119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
120 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
121 unsigned Alignment = 0);
122 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
123 MachineMemOperand *MMO = nullptr);
124 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
125 unsigned Alignment = 0);
126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
138 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
140 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
143 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
144 unsigned materializeGV(const GlobalValue *GV, MVT VT);
145 unsigned materializeInt(const Constant *C, MVT VT);
146 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
147 unsigned materializeExternalCallSym(MCSymbol *Syn);
149 MachineInstrBuilder emitInst(unsigned Opc) {
150 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
153 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
156 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
157 unsigned MemReg, int64_t MemOffset) {
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
160 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
161 unsigned MemReg, int64_t MemOffset) {
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
165 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
166 const TargetRegisterClass *RC,
167 unsigned Op0, bool Op0IsKill,
168 unsigned Op1, bool Op1IsKill);
170 // for some reason, this default is not generated by tablegen
171 // so we explicitly generate it here.
173 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
174 unsigned Op0, bool Op0IsKill, uint64_t imm1,
175 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
179 // Call handling routines.
181 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
182 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
184 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
187 // Backend specific FastISel code.
188 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
189 const TargetLibraryInfo *libInfo)
190 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
191 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
193 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
194 Context = &funcInfo.Fn->getContext();
196 ((TM.getRelocationModel() == Reloc::PIC_) &&
197 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
198 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
199 UnsupportedFPMode = Subtarget->isFP64bit();
202 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
203 unsigned fastMaterializeConstant(const Constant *C) override;
204 bool fastSelectInstruction(const Instruction *I) override;
206 #include "MipsGenFastISel.inc"
208 } // end anonymous namespace.
210 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
211 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
212 CCState &State) LLVM_ATTRIBUTE_UNUSED;
214 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
215 CCValAssign::LocInfo LocInfo,
216 ISD::ArgFlagsTy ArgFlags, CCState &State) {
217 llvm_unreachable("should not be called");
220 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
221 CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
223 llvm_unreachable("should not be called");
226 #include "MipsGenCallingConv.inc"
228 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
232 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
233 const Value *LHS, const Value *RHS) {
234 // Canonicalize immediates to the RHS first.
235 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
239 if (ISDOpc == ISD::AND) {
241 } else if (ISDOpc == ISD::OR) {
243 } else if (ISDOpc == ISD::XOR) {
246 llvm_unreachable("unexpected opcode");
248 unsigned LHSReg = getRegForValue(LHS);
249 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
257 if (const auto *C = dyn_cast<ConstantInt>(RHS))
258 RHSReg = materializeInt(C, MVT::i32);
260 RHSReg = getRegForValue(RHS);
265 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
269 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
270 assert(TLI.getValueType(AI->getType(), true) == MVT::i32 &&
271 "Alloca should always return a pointer.");
273 DenseMap<const AllocaInst *, int>::iterator SI =
274 FuncInfo.StaticAllocaMap.find(AI);
276 if (SI != FuncInfo.StaticAllocaMap.end()) {
277 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
280 .addFrameIndex(SI->second)
288 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
289 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
291 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
292 const ConstantInt *CI = cast<ConstantInt>(C);
294 if ((VT != MVT::i1) && CI->isNegative())
295 Imm = CI->getSExtValue();
297 Imm = CI->getZExtValue();
298 return materialize32BitInt(Imm, RC);
301 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
302 const TargetRegisterClass *RC) {
303 unsigned ResultReg = createResultReg(RC);
305 if (isInt<16>(Imm)) {
306 unsigned Opc = Mips::ADDiu;
307 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
309 } else if (isUInt<16>(Imm)) {
310 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
313 unsigned Lo = Imm & 0xFFFF;
314 unsigned Hi = (Imm >> 16) & 0xFFFF;
316 // Both Lo and Hi have nonzero bits.
317 unsigned TmpReg = createResultReg(RC);
318 emitInst(Mips::LUi, TmpReg).addImm(Hi);
319 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
321 emitInst(Mips::LUi, ResultReg).addImm(Hi);
326 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
327 if (UnsupportedFPMode)
329 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
330 if (VT == MVT::f32) {
331 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
332 unsigned DestReg = createResultReg(RC);
333 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
334 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
336 } else if (VT == MVT::f64) {
337 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
338 unsigned DestReg = createResultReg(RC);
339 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
341 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
342 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
348 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
349 // For now 32-bit only.
352 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
353 unsigned DestReg = createResultReg(RC);
354 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
355 bool IsThreadLocal = GVar && GVar->isThreadLocal();
356 // TLS not supported at this time.
359 emitInst(Mips::LW, DestReg)
360 .addReg(MFI->getGlobalBaseReg())
361 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
362 if ((GV->hasInternalLinkage() ||
363 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
364 unsigned TempReg = createResultReg(RC);
365 emitInst(Mips::ADDiu, TempReg)
367 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
373 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
374 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
375 unsigned DestReg = createResultReg(RC);
376 emitInst(Mips::LW, DestReg)
377 .addReg(MFI->getGlobalBaseReg())
378 .addSym(Sym, MipsII::MO_GOT);
382 // Materialize a constant into a register, and return the register
383 // number (or zero if we failed to handle it).
384 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
385 EVT CEVT = TLI.getValueType(C->getType(), true);
387 // Only handle simple types.
388 if (!CEVT.isSimple())
390 MVT VT = CEVT.getSimpleVT();
392 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
393 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
394 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
395 return materializeGV(GV, VT);
396 else if (isa<ConstantInt>(C))
397 return materializeInt(C, VT);
402 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
404 const User *U = nullptr;
405 unsigned Opcode = Instruction::UserOp1;
406 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
407 // Don't walk into other basic blocks unless the object is an alloca from
408 // another block, otherwise it may not have a virtual register assigned.
409 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
410 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
411 Opcode = I->getOpcode();
414 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
415 Opcode = C->getOpcode();
421 case Instruction::BitCast: {
422 // Look through bitcasts.
423 return computeAddress(U->getOperand(0), Addr);
425 case Instruction::GetElementPtr: {
426 Address SavedAddr = Addr;
427 uint64_t TmpOffset = Addr.getOffset();
428 // Iterate through the GEP folding the constants into offsets where
430 gep_type_iterator GTI = gep_type_begin(U);
431 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
433 const Value *Op = *i;
434 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
435 const StructLayout *SL = DL.getStructLayout(STy);
436 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
437 TmpOffset += SL->getElementOffset(Idx);
439 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
441 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
442 // Constant-offset addressing.
443 TmpOffset += CI->getSExtValue() * S;
446 if (canFoldAddIntoGEP(U, Op)) {
447 // A compatible add with a constant operand. Fold the constant.
449 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
450 TmpOffset += CI->getSExtValue() * S;
451 // Iterate on the other operand.
452 Op = cast<AddOperator>(Op)->getOperand(0);
456 goto unsupported_gep;
460 // Try to grab the base operand now.
461 Addr.setOffset(TmpOffset);
462 if (computeAddress(U->getOperand(0), Addr))
464 // We failed, restore everything and try the other options.
469 case Instruction::Alloca: {
470 const AllocaInst *AI = cast<AllocaInst>(Obj);
471 DenseMap<const AllocaInst *, int>::iterator SI =
472 FuncInfo.StaticAllocaMap.find(AI);
473 if (SI != FuncInfo.StaticAllocaMap.end()) {
474 Addr.setKind(Address::FrameIndexBase);
475 Addr.setFI(SI->second);
481 Addr.setReg(getRegForValue(Obj));
482 return Addr.getReg() != 0;
485 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
486 const User *U = nullptr;
487 unsigned Opcode = Instruction::UserOp1;
489 if (const auto *I = dyn_cast<Instruction>(V)) {
490 // Check if the value is defined in the same basic block. This information
491 // is crucial to know whether or not folding an operand is valid.
492 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
493 Opcode = I->getOpcode();
496 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
497 Opcode = C->getOpcode();
504 case Instruction::BitCast:
505 // Look past bitcasts if its operand is in the same BB.
506 return computeCallAddress(U->getOperand(0), Addr);
508 case Instruction::IntToPtr:
509 // Look past no-op inttoptrs if its operand is in the same BB.
510 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
511 return computeCallAddress(U->getOperand(0), Addr);
513 case Instruction::PtrToInt:
514 // Look past no-op ptrtoints if its operand is in the same BB.
515 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
516 return computeCallAddress(U->getOperand(0), Addr);
520 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
521 Addr.setGlobalValue(GV);
525 // If all else fails, try to materialize the value in a register.
526 if (!Addr.getGlobalValue()) {
527 Addr.setReg(getRegForValue(V));
528 return Addr.getReg() != 0;
534 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
535 EVT evt = TLI.getValueType(Ty, true);
536 // Only handle simple types.
537 if (evt == MVT::Other || !evt.isSimple())
539 VT = evt.getSimpleVT();
541 // Handle all legal types, i.e. a register that will directly hold this
543 return TLI.isTypeLegal(VT);
546 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
547 if (Ty->isVectorTy())
550 if (isTypeLegal(Ty, VT))
553 // If this is a type than can be sign or zero-extended to a basic operation
554 // go ahead and accept it now.
555 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
561 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
562 if (isTypeLegal(Ty, VT))
564 // We will extend this in a later patch:
565 // If this is a type than can be sign or zero-extended to a basic operation
566 // go ahead and accept it now.
567 if (VT == MVT::i8 || VT == MVT::i16)
571 // Because of how EmitCmp is called with fast-isel, you can
572 // end up with redundant "andi" instructions after the sequences emitted below.
573 // We should try and solve this issue in the future.
575 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
576 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
577 bool IsUnsigned = CI->isUnsigned();
578 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
581 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
584 CmpInst::Predicate P = CI->getPredicate();
589 case CmpInst::ICMP_EQ: {
590 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
591 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
592 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
595 case CmpInst::ICMP_NE: {
596 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
597 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
598 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
601 case CmpInst::ICMP_UGT: {
602 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
605 case CmpInst::ICMP_ULT: {
606 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
609 case CmpInst::ICMP_UGE: {
610 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
611 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
612 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
615 case CmpInst::ICMP_ULE: {
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
617 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
618 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
621 case CmpInst::ICMP_SGT: {
622 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
625 case CmpInst::ICMP_SLT: {
626 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
629 case CmpInst::ICMP_SGE: {
630 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
631 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
632 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
635 case CmpInst::ICMP_SLE: {
636 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
637 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
641 case CmpInst::FCMP_OEQ:
642 case CmpInst::FCMP_UNE:
643 case CmpInst::FCMP_OLT:
644 case CmpInst::FCMP_OLE:
645 case CmpInst::FCMP_OGT:
646 case CmpInst::FCMP_OGE: {
647 if (UnsupportedFPMode)
649 bool IsFloat = Left->getType()->isFloatTy();
650 bool IsDouble = Left->getType()->isDoubleTy();
651 if (!IsFloat && !IsDouble)
653 unsigned Opc, CondMovOpc;
655 case CmpInst::FCMP_OEQ:
656 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
657 CondMovOpc = Mips::MOVT_I;
659 case CmpInst::FCMP_UNE:
660 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
661 CondMovOpc = Mips::MOVF_I;
663 case CmpInst::FCMP_OLT:
664 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
665 CondMovOpc = Mips::MOVT_I;
667 case CmpInst::FCMP_OLE:
668 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
669 CondMovOpc = Mips::MOVT_I;
671 case CmpInst::FCMP_OGT:
672 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
673 CondMovOpc = Mips::MOVF_I;
675 case CmpInst::FCMP_OGE:
676 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
677 CondMovOpc = Mips::MOVF_I;
680 llvm_unreachable("Only switching of a subset of CCs.");
682 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
683 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
684 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
685 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
686 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
687 Mips::FCC0, RegState::ImplicitDefine);
688 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
691 .addReg(RegWithZero, RegState::Implicit);
692 MI->tieOperands(0, 3);
698 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
699 unsigned Alignment) {
701 // more cases will be handled here in following patches.
704 switch (VT.SimpleTy) {
706 ResultReg = createResultReg(&Mips::GPR32RegClass);
711 ResultReg = createResultReg(&Mips::GPR32RegClass);
716 ResultReg = createResultReg(&Mips::GPR32RegClass);
721 if (UnsupportedFPMode)
723 ResultReg = createResultReg(&Mips::FGR32RegClass);
728 if (UnsupportedFPMode)
730 ResultReg = createResultReg(&Mips::AFGR64RegClass);
737 if (Addr.isRegBase()) {
738 simplifyAddress(Addr);
739 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
742 if (Addr.isFIBase()) {
743 unsigned FI = Addr.getFI();
745 unsigned Offset = Addr.getOffset();
746 MachineFrameInfo &MFI = *MF->getFrameInfo();
747 MachineMemOperand *MMO = MF->getMachineMemOperand(
748 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
749 MFI.getObjectSize(FI), Align);
750 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
759 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
760 unsigned Alignment) {
762 // more cases will be handled here in following patches.
765 switch (VT.SimpleTy) {
776 if (UnsupportedFPMode)
781 if (UnsupportedFPMode)
788 if (Addr.isRegBase()) {
789 simplifyAddress(Addr);
790 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
793 if (Addr.isFIBase()) {
794 unsigned FI = Addr.getFI();
796 unsigned Offset = Addr.getOffset();
797 MachineFrameInfo &MFI = *MF->getFrameInfo();
798 MachineMemOperand *MMO = MF->getMachineMemOperand(
799 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
800 MFI.getObjectSize(FI), Align);
801 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
811 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
813 if (!isTypeSupported(I->getType(), VT))
817 switch (I->getOpcode()) {
819 llvm_unreachable("Unexpected instruction.");
820 case Instruction::And:
821 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
823 case Instruction::Or:
824 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
826 case Instruction::Xor:
827 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
834 updateValueMap(I, ResultReg);
838 bool MipsFastISel::selectLoad(const Instruction *I) {
839 // Atomic loads need special handling.
840 if (cast<LoadInst>(I)->isAtomic())
843 // Verify we have a legal type before going any further.
845 if (!isLoadTypeLegal(I->getType(), VT))
848 // See if we can handle this address.
850 if (!computeAddress(I->getOperand(0), Addr))
854 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
856 updateValueMap(I, ResultReg);
860 bool MipsFastISel::selectStore(const Instruction *I) {
861 Value *Op0 = I->getOperand(0);
864 // Atomic stores need special handling.
865 if (cast<StoreInst>(I)->isAtomic())
868 // Verify we have a legal type before going any further.
870 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
873 // Get the value to be stored into a register.
874 SrcReg = getRegForValue(Op0);
878 // See if we can handle this address.
880 if (!computeAddress(I->getOperand(1), Addr))
883 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
889 // This can cause a redundant sltiu to be generated.
890 // FIXME: try and eliminate this in a future patch.
892 bool MipsFastISel::selectBranch(const Instruction *I) {
893 const BranchInst *BI = cast<BranchInst>(I);
894 MachineBasicBlock *BrBB = FuncInfo.MBB;
896 // TBB is the basic block for the case where the comparison is true.
897 // FBB is the basic block for the case where the comparison is false.
898 // if (cond) goto TBB
902 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
903 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
905 // For now, just try the simplest case where it's fed by a compare.
906 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
907 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
908 if (!emitCmp(CondReg, CI))
910 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
913 fastEmitBranch(FBB, DbgLoc);
914 FuncInfo.MBB->addSuccessor(TBB);
920 bool MipsFastISel::selectCmp(const Instruction *I) {
921 const CmpInst *CI = cast<CmpInst>(I);
922 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
923 if (!emitCmp(ResultReg, CI))
925 updateValueMap(I, ResultReg);
929 // Attempt to fast-select a floating-point extend instruction.
930 bool MipsFastISel::selectFPExt(const Instruction *I) {
931 if (UnsupportedFPMode)
933 Value *Src = I->getOperand(0);
934 EVT SrcVT = TLI.getValueType(Src->getType(), true);
935 EVT DestVT = TLI.getValueType(I->getType(), true);
937 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
941 getRegForValue(Src); // his must be a 32 bit floating point register class
942 // maybe we should handle this differently
946 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
947 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
948 updateValueMap(I, DestReg);
952 bool MipsFastISel::selectSelect(const Instruction *I) {
953 assert(isa<SelectInst>(I) && "Expected a select instruction.");
956 if (!isTypeSupported(I->getType(), VT))
960 const TargetRegisterClass *RC;
962 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
963 CondMovOpc = Mips::MOVN_I_I;
964 RC = &Mips::GPR32RegClass;
965 } else if (VT == MVT::f32) {
966 CondMovOpc = Mips::MOVN_I_S;
967 RC = &Mips::FGR32RegClass;
968 } else if (VT == MVT::f64) {
969 CondMovOpc = Mips::MOVN_I_D32;
970 RC = &Mips::AFGR64RegClass;
974 const SelectInst *SI = cast<SelectInst>(I);
975 const Value *Cond = SI->getCondition();
976 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
977 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
978 unsigned CondReg = getRegForValue(Cond);
980 if (!Src1Reg || !Src2Reg || !CondReg)
983 unsigned ResultReg = createResultReg(RC);
984 unsigned TempReg = createResultReg(RC);
986 if (!ResultReg || !TempReg)
989 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
990 emitInst(CondMovOpc, ResultReg)
991 .addReg(Src1Reg).addReg(CondReg).addReg(TempReg);
992 updateValueMap(I, ResultReg);
996 // Attempt to fast-select a floating-point truncate instruction.
997 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
998 if (UnsupportedFPMode)
1000 Value *Src = I->getOperand(0);
1001 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1002 EVT DestVT = TLI.getValueType(I->getType(), true);
1004 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1007 unsigned SrcReg = getRegForValue(Src);
1011 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1015 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1016 updateValueMap(I, DestReg);
1020 // Attempt to fast-select a floating-point-to-integer conversion.
1021 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1022 if (UnsupportedFPMode)
1026 return false; // We don't handle this case yet. There is no native
1027 // instruction for this but it can be synthesized.
1028 Type *DstTy = I->getType();
1029 if (!isTypeLegal(DstTy, DstVT))
1032 if (DstVT != MVT::i32)
1035 Value *Src = I->getOperand(0);
1036 Type *SrcTy = Src->getType();
1037 if (!isTypeLegal(SrcTy, SrcVT))
1040 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1043 unsigned SrcReg = getRegForValue(Src);
1047 // Determine the opcode for the conversion, which takes place
1048 // entirely within FPRs.
1049 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1050 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1053 if (SrcVT == MVT::f32)
1054 Opc = Mips::TRUNC_W_S;
1056 Opc = Mips::TRUNC_W_D32;
1058 // Generate the convert.
1059 emitInst(Opc, TempReg).addReg(SrcReg);
1061 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1063 updateValueMap(I, DestReg);
1067 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1068 SmallVectorImpl<MVT> &OutVTs,
1069 unsigned &NumBytes) {
1070 CallingConv::ID CC = CLI.CallConv;
1071 SmallVector<CCValAssign, 16> ArgLocs;
1072 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1073 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1074 // Get a count of how many bytes are to be pushed on the stack.
1075 NumBytes = CCInfo.getNextStackOffset();
1076 // This is the minimum argument area used for A0-A3.
1080 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1081 // Process the args.
1083 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1084 CCValAssign &VA = ArgLocs[i];
1085 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1086 MVT ArgVT = OutVTs[VA.getValNo()];
1090 if (ArgVT == MVT::f32) {
1091 VA.convertToReg(Mips::F12);
1092 } else if (ArgVT == MVT::f64) {
1093 VA.convertToReg(Mips::D6);
1095 } else if (i == 1) {
1096 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1097 if (ArgVT == MVT::f32) {
1098 VA.convertToReg(Mips::F14);
1099 } else if (ArgVT == MVT::f64) {
1100 VA.convertToReg(Mips::D7);
1104 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1105 (ArgVT == MVT::i8)) &&
1107 switch (VA.getLocMemOffset()) {
1109 VA.convertToReg(Mips::A0);
1112 VA.convertToReg(Mips::A1);
1115 VA.convertToReg(Mips::A2);
1118 VA.convertToReg(Mips::A3);
1124 unsigned ArgReg = getRegForValue(ArgVal);
1128 // Handle arg promotion: SExt, ZExt, AExt.
1129 switch (VA.getLocInfo()) {
1130 case CCValAssign::Full:
1132 case CCValAssign::AExt:
1133 case CCValAssign::SExt: {
1134 MVT DestVT = VA.getLocVT();
1136 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1141 case CCValAssign::ZExt: {
1142 MVT DestVT = VA.getLocVT();
1144 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1150 llvm_unreachable("Unknown arg promotion!");
1153 // Now copy/store arg to correct locations.
1154 if (VA.isRegLoc() && !VA.needsCustom()) {
1155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1156 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1157 CLI.OutRegs.push_back(VA.getLocReg());
1158 } else if (VA.needsCustom()) {
1159 llvm_unreachable("Mips does not use custom args.");
1163 // FIXME: This path will currently return false. It was copied
1164 // from the AArch64 port and should be essentially fine for Mips too.
1165 // The work to finish up this path will be done in a follow-on patch.
1167 assert(VA.isMemLoc() && "Assuming store on stack.");
1168 // Don't emit stores for undef values.
1169 if (isa<UndefValue>(ArgVal))
1172 // Need to store on the stack.
1173 // FIXME: This alignment is incorrect but this path is disabled
1174 // for now (will return false). We need to determine the right alignment
1175 // based on the normal alignment for the underlying machine type.
1177 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1179 unsigned BEAlign = 0;
1180 if (ArgSize < 8 && !Subtarget->isLittle())
1181 BEAlign = 8 - ArgSize;
1184 Addr.setKind(Address::RegBase);
1185 Addr.setReg(Mips::SP);
1186 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1188 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1189 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1190 MachinePointerInfo::getStack(Addr.getOffset()),
1191 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1193 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1194 return false; // can't store on the stack yet.
1201 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1202 unsigned NumBytes) {
1203 CallingConv::ID CC = CLI.CallConv;
1204 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1205 if (RetVT != MVT::isVoid) {
1206 SmallVector<CCValAssign, 16> RVLocs;
1207 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1208 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1210 // Only handle a single return value.
1211 if (RVLocs.size() != 1)
1213 // Copy all of the result registers out of their specified physreg.
1214 MVT CopyVT = RVLocs[0].getValVT();
1215 // Special handling for extended integers.
1216 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1219 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1223 TII.get(TargetOpcode::COPY),
1224 ResultReg).addReg(RVLocs[0].getLocReg());
1225 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1227 CLI.ResultReg = ResultReg;
1228 CLI.NumResultRegs = 1;
1233 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1234 CallingConv::ID CC = CLI.CallConv;
1235 bool IsTailCall = CLI.IsTailCall;
1236 bool IsVarArg = CLI.IsVarArg;
1237 const Value *Callee = CLI.Callee;
1238 MCSymbol *Symbol = CLI.Symbol;
1240 // Allow SelectionDAG isel to handle tail calls.
1244 // Let SDISel handle vararg functions.
1248 // FIXME: Only handle *simple* calls for now.
1250 if (CLI.RetTy->isVoidTy())
1251 RetVT = MVT::isVoid;
1252 else if (!isTypeSupported(CLI.RetTy, RetVT))
1255 for (auto Flag : CLI.OutFlags)
1256 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1259 // Set up the argument vectors.
1260 SmallVector<MVT, 16> OutVTs;
1261 OutVTs.reserve(CLI.OutVals.size());
1263 for (auto *Val : CLI.OutVals) {
1265 if (!isTypeLegal(Val->getType(), VT) &&
1266 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1269 // We don't handle vector parameters yet.
1270 if (VT.isVector() || VT.getSizeInBits() > 64)
1273 OutVTs.push_back(VT);
1277 if (!computeCallAddress(Callee, Addr))
1280 // Handle the arguments now that we've gotten them.
1282 if (!processCallArgs(CLI, OutVTs, NumBytes))
1285 if (!Addr.getGlobalValue())
1289 unsigned DestAddress;
1291 DestAddress = materializeExternalCallSym(Symbol);
1293 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1294 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1295 MachineInstrBuilder MIB =
1296 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1297 Mips::RA).addReg(Mips::T9);
1299 // Add implicit physical register uses to the call.
1300 for (auto Reg : CLI.OutRegs)
1301 MIB.addReg(Reg, RegState::Implicit);
1303 // Add a register mask with the call-preserved registers.
1304 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1305 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1309 // Finish off the call including any return values.
1310 return finishCall(CLI, RetVT, NumBytes);
1313 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1314 switch (II->getIntrinsicID()) {
1317 case Intrinsic::bswap: {
1318 Type *RetTy = II->getCalledFunction()->getReturnType();
1321 if (!isTypeSupported(RetTy, VT))
1324 unsigned SrcReg = getRegForValue(II->getOperand(0));
1327 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1330 if (VT == MVT::i16) {
1331 if (Subtarget->hasMips32r2()) {
1332 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1333 updateValueMap(II, DestReg);
1336 unsigned TempReg[3];
1337 for (int i = 0; i < 3; i++) {
1338 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1339 if (TempReg[i] == 0)
1342 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1343 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1344 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1345 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1346 updateValueMap(II, DestReg);
1349 } else if (VT == MVT::i32) {
1350 if (Subtarget->hasMips32r2()) {
1351 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1352 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1353 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1354 updateValueMap(II, DestReg);
1357 unsigned TempReg[8];
1358 for (int i = 0; i < 8; i++) {
1359 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1360 if (TempReg[i] == 0)
1364 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1365 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1366 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1367 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1369 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1370 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1372 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1373 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1374 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1375 updateValueMap(II, DestReg);
1381 case Intrinsic::memcpy:
1382 case Intrinsic::memmove: {
1383 const auto *MTI = cast<MemTransferInst>(II);
1384 // Don't handle volatile.
1385 if (MTI->isVolatile())
1387 if (!MTI->getLength()->getType()->isIntegerTy(32))
1389 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1390 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1392 case Intrinsic::memset: {
1393 const MemSetInst *MSI = cast<MemSetInst>(II);
1394 // Don't handle volatile.
1395 if (MSI->isVolatile())
1397 if (!MSI->getLength()->getType()->isIntegerTy(32))
1399 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1405 bool MipsFastISel::selectRet(const Instruction *I) {
1406 const Function &F = *I->getParent()->getParent();
1407 const ReturnInst *Ret = cast<ReturnInst>(I);
1409 if (!FuncInfo.CanLowerReturn)
1412 // Build a list of return value registers.
1413 SmallVector<unsigned, 4> RetRegs;
1415 if (Ret->getNumOperands() > 0) {
1416 CallingConv::ID CC = F.getCallingConv();
1417 SmallVector<ISD::OutputArg, 4> Outs;
1418 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1419 // Analyze operands of the call, assigning locations to each operand.
1420 SmallVector<CCValAssign, 16> ValLocs;
1421 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1423 CCAssignFn *RetCC = RetCC_Mips;
1424 CCInfo.AnalyzeReturn(Outs, RetCC);
1426 // Only handle a single return value for now.
1427 if (ValLocs.size() != 1)
1430 CCValAssign &VA = ValLocs[0];
1431 const Value *RV = Ret->getOperand(0);
1433 // Don't bother handling odd stuff for now.
1434 if ((VA.getLocInfo() != CCValAssign::Full) &&
1435 (VA.getLocInfo() != CCValAssign::BCvt))
1438 // Only handle register returns for now.
1442 unsigned Reg = getRegForValue(RV);
1446 unsigned SrcReg = Reg + VA.getValNo();
1447 unsigned DestReg = VA.getLocReg();
1448 // Avoid a cross-class copy. This is very unlikely.
1449 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1452 EVT RVEVT = TLI.getValueType(RV->getType());
1453 if (!RVEVT.isSimple())
1456 if (RVEVT.isVector())
1459 MVT RVVT = RVEVT.getSimpleVT();
1460 if (RVVT == MVT::f128)
1463 MVT DestVT = VA.getValVT();
1464 // Special handling for extended integers.
1465 if (RVVT != DestVT) {
1466 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1469 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1470 bool IsZExt = Outs[0].Flags.isZExt();
1471 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1478 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1479 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1481 // Add register to return instruction.
1482 RetRegs.push_back(VA.getLocReg());
1484 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1485 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1486 MIB.addReg(RetRegs[i], RegState::Implicit);
1490 bool MipsFastISel::selectTrunc(const Instruction *I) {
1491 // The high bits for a type smaller than the register size are assumed to be
1493 Value *Op = I->getOperand(0);
1496 SrcVT = TLI.getValueType(Op->getType(), true);
1497 DestVT = TLI.getValueType(I->getType(), true);
1499 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1501 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1504 unsigned SrcReg = getRegForValue(Op);
1508 // Because the high bits are undefined, a truncate doesn't generate
1510 updateValueMap(I, SrcReg);
1513 bool MipsFastISel::selectIntExt(const Instruction *I) {
1514 Type *DestTy = I->getType();
1515 Value *Src = I->getOperand(0);
1516 Type *SrcTy = Src->getType();
1518 bool isZExt = isa<ZExtInst>(I);
1519 unsigned SrcReg = getRegForValue(Src);
1523 EVT SrcEVT, DestEVT;
1524 SrcEVT = TLI.getValueType(SrcTy, true);
1525 DestEVT = TLI.getValueType(DestTy, true);
1526 if (!SrcEVT.isSimple())
1528 if (!DestEVT.isSimple())
1531 MVT SrcVT = SrcEVT.getSimpleVT();
1532 MVT DestVT = DestEVT.getSimpleVT();
1533 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1535 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1537 updateValueMap(I, ResultReg);
1540 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1543 switch (SrcVT.SimpleTy) {
1553 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1554 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1555 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1559 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1561 switch (SrcVT.SimpleTy) {
1565 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1568 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1574 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1576 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1578 if (Subtarget->hasMips32r2())
1579 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1580 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1583 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1585 switch (SrcVT.SimpleTy) {
1589 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1592 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1595 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1601 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1602 unsigned DestReg, bool IsZExt) {
1603 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1604 // DestVT are odd things, so test to make sure that they are both types we can
1605 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1606 // bail out to SelectionDAG.
1607 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1608 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1611 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1612 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1615 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1617 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1618 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1619 return Success ? DestReg : 0;
1622 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1623 EVT DestEVT = TLI.getValueType(I->getType(), true);
1624 if (!DestEVT.isSimple())
1627 MVT DestVT = DestEVT.getSimpleVT();
1628 if (DestVT != MVT::i32)
1632 switch (ISDOpcode) {
1637 DivOpc = Mips::SDIV;
1641 DivOpc = Mips::UDIV;
1645 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1646 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1647 if (!Src0Reg || !Src1Reg)
1650 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1651 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1653 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1657 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1660 emitInst(MFOpc, ResultReg);
1662 updateValueMap(I, ResultReg);
1666 bool MipsFastISel::selectShift(const Instruction *I) {
1669 if (!isTypeSupported(I->getType(), RetVT))
1672 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1676 unsigned Opcode = I->getOpcode();
1677 const Value *Op0 = I->getOperand(0);
1678 unsigned Op0Reg = getRegForValue(Op0);
1682 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1683 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1684 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1688 MVT Op0MVT = TLI.getValueType(Op0->getType(), true).getSimpleVT();
1689 bool IsZExt = Opcode == Instruction::LShr;
1690 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1696 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1697 uint64_t ShiftVal = C->getZExtValue();
1701 llvm_unreachable("Unexpected instruction.");
1702 case Instruction::Shl:
1705 case Instruction::AShr:
1708 case Instruction::LShr:
1713 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1714 updateValueMap(I, ResultReg);
1718 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1724 llvm_unreachable("Unexpected instruction.");
1725 case Instruction::Shl:
1726 Opcode = Mips::SLLV;
1728 case Instruction::AShr:
1729 Opcode = Mips::SRAV;
1731 case Instruction::LShr:
1732 Opcode = Mips::SRLV;
1736 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1737 updateValueMap(I, ResultReg);
1741 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1742 if (!TargetSupported)
1744 switch (I->getOpcode()) {
1747 case Instruction::Load:
1748 return selectLoad(I);
1749 case Instruction::Store:
1750 return selectStore(I);
1751 case Instruction::SDiv:
1752 if (!selectBinaryOp(I, ISD::SDIV))
1753 return selectDivRem(I, ISD::SDIV);
1755 case Instruction::UDiv:
1756 if (!selectBinaryOp(I, ISD::UDIV))
1757 return selectDivRem(I, ISD::UDIV);
1759 case Instruction::SRem:
1760 if (!selectBinaryOp(I, ISD::SREM))
1761 return selectDivRem(I, ISD::SREM);
1763 case Instruction::URem:
1764 if (!selectBinaryOp(I, ISD::UREM))
1765 return selectDivRem(I, ISD::UREM);
1767 case Instruction::Shl:
1768 case Instruction::LShr:
1769 case Instruction::AShr:
1770 return selectShift(I);
1771 case Instruction::And:
1772 case Instruction::Or:
1773 case Instruction::Xor:
1774 return selectLogicalOp(I);
1775 case Instruction::Br:
1776 return selectBranch(I);
1777 case Instruction::Ret:
1778 return selectRet(I);
1779 case Instruction::Trunc:
1780 return selectTrunc(I);
1781 case Instruction::ZExt:
1782 case Instruction::SExt:
1783 return selectIntExt(I);
1784 case Instruction::FPTrunc:
1785 return selectFPTrunc(I);
1786 case Instruction::FPExt:
1787 return selectFPExt(I);
1788 case Instruction::FPToSI:
1789 return selectFPToInt(I, /*isSigned*/ true);
1790 case Instruction::FPToUI:
1791 return selectFPToInt(I, /*isSigned*/ false);
1792 case Instruction::ICmp:
1793 case Instruction::FCmp:
1794 return selectCmp(I);
1795 case Instruction::Select:
1796 return selectSelect(I);
1801 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1803 unsigned VReg = getRegForValue(V);
1806 MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1807 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1808 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1809 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1816 void MipsFastISel::simplifyAddress(Address &Addr) {
1817 if (!isInt<16>(Addr.getOffset())) {
1819 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1820 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1821 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1822 Addr.setReg(DestReg);
1827 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1828 const TargetRegisterClass *RC,
1829 unsigned Op0, bool Op0IsKill,
1830 unsigned Op1, bool Op1IsKill) {
1831 // We treat the MUL instruction in a special way because it clobbers
1832 // the HI0 & LO0 registers. The TableGen definition of this instruction can
1833 // mark these registers only as implicitly defined. As a result, the
1834 // register allocator runs out of registers when this instruction is
1835 // followed by another instruction that defines the same registers too.
1836 // We can fix this by explicitly marking those registers as dead.
1837 if (MachineInstOpcode == Mips::MUL) {
1838 unsigned ResultReg = createResultReg(RC);
1839 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1840 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1841 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1843 .addReg(Op0, getKillRegState(Op0IsKill))
1844 .addReg(Op1, getKillRegState(Op1IsKill))
1845 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1846 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1850 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1855 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1856 const TargetLibraryInfo *libInfo) {
1857 return new MipsFastISel(funcInfo, libInfo);