1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
21 // All possible address modes.
22 typedef struct Address {
23 enum { RegBase, FrameIndexBase } BaseType;
32 // Innocuous defaults for our address.
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
36 class MipsFastISel final : public FastISel {
38 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39 /// make the right decision when generating code for different targets.
41 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
44 const MipsSubtarget *Subtarget;
45 MipsFunctionInfo *MFI;
47 // Convenience variables to avoid some queries.
53 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo)
55 : FastISel(funcInfo, libInfo),
56 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57 TM(funcInfo.MF->getTarget()),
58 TII(*TM.getSubtargetImpl()->getInstrInfo()),
59 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
60 Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
61 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
62 Context = &funcInfo.Fn->getContext();
63 TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
64 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
65 (Subtarget->isABI_O32())));
68 bool fastSelectInstruction(const Instruction *I) override;
69 unsigned fastMaterializeConstant(const Constant *C) override;
71 bool ComputeAddress(const Value *Obj, Address &Addr);
74 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
75 unsigned Alignment = 0);
76 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
77 unsigned Alignment = 0);
78 bool SelectLoad(const Instruction *I);
79 bool SelectRet(const Instruction *I);
80 bool SelectStore(const Instruction *I);
82 bool isTypeLegal(Type *Ty, MVT &VT);
83 bool isLoadTypeLegal(Type *Ty, MVT &VT);
85 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
86 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
87 unsigned MaterializeInt(const Constant *C, MVT VT);
88 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
90 // for some reason, this default is not generated by tablegen
91 // so we explicitly generate it here.
93 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
94 unsigned Op0, bool Op0IsKill, uint64_t imm1,
95 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
99 MachineInstrBuilder EmitInst(unsigned Opc) {
100 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
103 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
104 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
108 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
109 unsigned MemReg, int64_t MemOffset) {
110 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
113 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
114 unsigned MemReg, int64_t MemOffset) {
115 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
118 #include "MipsGenFastISel.inc"
121 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
122 EVT evt = TLI.getValueType(Ty, true);
123 // Only handle simple types.
124 if (evt == MVT::Other || !evt.isSimple())
126 VT = evt.getSimpleVT();
128 // Handle all legal types, i.e. a register that will directly hold this
130 return TLI.isTypeLegal(VT);
133 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
134 if (isTypeLegal(Ty, VT))
136 // We will extend this in a later patch:
137 // If this is a type than can be sign or zero-extended to a basic operation
138 // go ahead and accept it now.
139 if (VT == MVT::i8 || VT == MVT::i16)
144 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
145 // This construct looks a big awkward but it is how other ports handle this
146 // and as this function is more fully completed, these cases which
147 // return false will have additional code in them.
149 if (isa<Instruction>(Obj))
151 else if (isa<ConstantExpr>(Obj))
153 Addr.Base.Reg = getRegForValue(Obj);
154 return Addr.Base.Reg != 0;
157 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
158 unsigned Alignment) {
160 // more cases will be handled here in following patches.
163 switch (VT.SimpleTy) {
165 ResultReg = createResultReg(&Mips::GPR32RegClass);
170 ResultReg = createResultReg(&Mips::GPR32RegClass);
175 ResultReg = createResultReg(&Mips::GPR32RegClass);
180 ResultReg = createResultReg(&Mips::FGR32RegClass);
185 ResultReg = createResultReg(&Mips::AFGR64RegClass);
192 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
196 // Materialize a constant into a register, and return the register
197 // number (or zero if we failed to handle it).
198 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
199 EVT CEVT = TLI.getValueType(C->getType(), true);
201 // Only handle simple types.
202 if (!CEVT.isSimple())
204 MVT VT = CEVT.getSimpleVT();
206 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
207 return MaterializeFP(CFP, VT);
208 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
209 return MaterializeGV(GV, VT);
210 else if (isa<ConstantInt>(C))
211 return MaterializeInt(C, VT);
216 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
217 unsigned Alignment) {
219 // more cases will be handled here in following patches.
222 switch (VT.SimpleTy) {
241 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
245 bool MipsFastISel::SelectLoad(const Instruction *I) {
246 // Atomic loads need special handling.
247 if (cast<LoadInst>(I)->isAtomic())
250 // Verify we have a legal type before going any further.
252 if (!isLoadTypeLegal(I->getType(), VT))
255 // See if we can handle this address.
257 if (!ComputeAddress(I->getOperand(0), Addr))
261 if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
263 updateValueMap(I, ResultReg);
267 bool MipsFastISel::SelectStore(const Instruction *I) {
268 Value *Op0 = I->getOperand(0);
271 // Atomic stores need special handling.
272 if (cast<StoreInst>(I)->isAtomic())
275 // Verify we have a legal type before going any further.
277 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
280 // Get the value to be stored into a register.
281 SrcReg = getRegForValue(Op0);
285 // See if we can handle this address.
287 if (!ComputeAddress(I->getOperand(1), Addr))
290 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
295 bool MipsFastISel::SelectRet(const Instruction *I) {
296 const ReturnInst *Ret = cast<ReturnInst>(I);
298 if (!FuncInfo.CanLowerReturn)
300 if (Ret->getNumOperands() > 0) {
303 EmitInst(Mips::RetRA);
307 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
308 if (!TargetSupported)
310 switch (I->getOpcode()) {
313 case Instruction::Load:
314 return SelectLoad(I);
315 case Instruction::Store:
316 return SelectStore(I);
317 case Instruction::Ret:
324 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
325 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
326 if (VT == MVT::f32) {
327 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
328 unsigned DestReg = createResultReg(RC);
329 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
330 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
332 } else if (VT == MVT::f64) {
333 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
334 unsigned DestReg = createResultReg(RC);
335 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
337 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
338 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
344 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
345 // For now 32-bit only.
348 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
349 unsigned DestReg = createResultReg(RC);
350 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
351 bool IsThreadLocal = GVar && GVar->isThreadLocal();
352 // TLS not supported at this time.
355 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
356 GV, 0, MipsII::MO_GOT);
357 if ((GV->hasInternalLinkage() ||
358 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
359 unsigned TempReg = createResultReg(RC);
360 EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
361 GV, 0, MipsII::MO_ABS_LO);
367 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
368 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
370 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
371 const ConstantInt *CI = cast<ConstantInt>(C);
373 if ((VT != MVT::i1) && CI->isNegative())
374 Imm = CI->getSExtValue();
376 Imm = CI->getZExtValue();
377 return Materialize32BitInt(Imm, RC);
380 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
381 const TargetRegisterClass *RC) {
382 unsigned ResultReg = createResultReg(RC);
384 if (isInt<16>(Imm)) {
385 unsigned Opc = Mips::ADDiu;
386 EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
388 } else if (isUInt<16>(Imm)) {
389 EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
392 unsigned Lo = Imm & 0xFFFF;
393 unsigned Hi = (Imm >> 16) & 0xFFFF;
395 // Both Lo and Hi have nonzero bits.
396 unsigned TmpReg = createResultReg(RC);
397 EmitInst(Mips::LUi, TmpReg).addImm(Hi);
398 EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
400 EmitInst(Mips::LUi, ResultReg).addImm(Hi);
406 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
407 const TargetLibraryInfo *libInfo) {
408 return new MipsFastISel(funcInfo, libInfo);