1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Target/TargetInstrInfo.h"
26 class MipsFastISel final : public FastISel {
28 // All possible address modes.
31 typedef enum { RegBase, FrameIndexBase } BaseKind;
42 const GlobalValue *GV;
45 // Innocuous defaults for our address.
46 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
47 void setKind(BaseKind K) { Kind = K; }
48 BaseKind getKind() const { return Kind; }
49 bool isRegBase() const { return Kind == RegBase; }
50 bool isFIBase() const { return Kind == FrameIndexBase; }
51 void setReg(unsigned Reg) {
52 assert(isRegBase() && "Invalid base register access!");
55 unsigned getReg() const {
56 assert(isRegBase() && "Invalid base register access!");
59 void setFI(unsigned FI) {
60 assert(isFIBase() && "Invalid base frame index access!");
63 unsigned getFI() const {
64 assert(isFIBase() && "Invalid base frame index access!");
68 void setOffset(int64_t Offset_) { Offset = Offset_; }
69 int64_t getOffset() const { return Offset; }
70 void setGlobalValue(const GlobalValue *G) { GV = G; }
71 const GlobalValue *getGlobalValue() { return GV; }
74 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
75 /// make the right decision when generating code for different targets.
76 const TargetMachine &TM;
77 const MipsSubtarget *Subtarget;
78 const TargetInstrInfo &TII;
79 const TargetLowering &TLI;
80 MipsFunctionInfo *MFI;
82 // Convenience variables to avoid some queries.
85 bool fastLowerCall(CallLoweringInfo &CLI) override;
86 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
89 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
90 // floating point but not reject doing fast-isel in other
94 // Selection routines.
95 bool selectLogicalOp(const Instruction *I);
96 bool selectLoad(const Instruction *I);
97 bool selectStore(const Instruction *I);
98 bool selectBranch(const Instruction *I);
99 bool selectSelect(const Instruction *I);
100 bool selectCmp(const Instruction *I);
101 bool selectFPExt(const Instruction *I);
102 bool selectFPTrunc(const Instruction *I);
103 bool selectFPToInt(const Instruction *I, bool IsSigned);
104 bool selectRet(const Instruction *I);
105 bool selectTrunc(const Instruction *I);
106 bool selectIntExt(const Instruction *I);
107 bool selectShift(const Instruction *I);
108 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
110 // Utility helper routines.
111 bool isTypeLegal(Type *Ty, MVT &VT);
112 bool isTypeSupported(Type *Ty, MVT &VT);
113 bool isLoadTypeLegal(Type *Ty, MVT &VT);
114 bool computeAddress(const Value *Obj, Address &Addr);
115 bool computeCallAddress(const Value *V, Address &Addr);
116 void simplifyAddress(Address &Addr);
118 // Emit helper routines.
119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
120 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
121 unsigned Alignment = 0);
122 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
123 MachineMemOperand *MMO = nullptr);
124 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
125 unsigned Alignment = 0);
126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
138 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
140 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
143 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
144 unsigned materializeGV(const GlobalValue *GV, MVT VT);
145 unsigned materializeInt(const Constant *C, MVT VT);
146 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
147 unsigned materializeExternalCallSym(MCSymbol *Syn);
149 MachineInstrBuilder emitInst(unsigned Opc) {
150 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
153 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
156 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
157 unsigned MemReg, int64_t MemOffset) {
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
160 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
161 unsigned MemReg, int64_t MemOffset) {
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
165 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
166 const TargetRegisterClass *RC,
167 unsigned Op0, bool Op0IsKill,
168 unsigned Op1, bool Op1IsKill);
170 // for some reason, this default is not generated by tablegen
171 // so we explicitly generate it here.
173 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
174 unsigned Op0, bool Op0IsKill, uint64_t imm1,
175 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
179 // Call handling routines.
181 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
182 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
184 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
187 // Backend specific FastISel code.
188 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
189 const TargetLibraryInfo *libInfo)
190 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
191 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
193 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
194 Context = &funcInfo.Fn->getContext();
196 ((TM.getRelocationModel() == Reloc::PIC_) &&
197 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
198 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
199 UnsupportedFPMode = Subtarget->isFP64bit();
202 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
203 unsigned fastMaterializeConstant(const Constant *C) override;
204 bool fastSelectInstruction(const Instruction *I) override;
206 #include "MipsGenFastISel.inc"
208 } // end anonymous namespace.
210 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
211 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
212 CCState &State) LLVM_ATTRIBUTE_UNUSED;
214 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
215 CCValAssign::LocInfo LocInfo,
216 ISD::ArgFlagsTy ArgFlags, CCState &State) {
217 llvm_unreachable("should not be called");
220 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
221 CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
223 llvm_unreachable("should not be called");
226 #include "MipsGenCallingConv.inc"
228 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
232 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
233 const Value *LHS, const Value *RHS) {
234 // Canonicalize immediates to the RHS first.
235 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
239 if (ISDOpc == ISD::AND) {
241 } else if (ISDOpc == ISD::OR) {
243 } else if (ISDOpc == ISD::XOR) {
246 llvm_unreachable("unexpected opcode");
248 unsigned LHSReg = getRegForValue(LHS);
249 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
257 if (const auto *C = dyn_cast<ConstantInt>(RHS))
258 RHSReg = materializeInt(C, MVT::i32);
260 RHSReg = getRegForValue(RHS);
265 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
269 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
270 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
271 "Alloca should always return a pointer.");
273 DenseMap<const AllocaInst *, int>::iterator SI =
274 FuncInfo.StaticAllocaMap.find(AI);
276 if (SI != FuncInfo.StaticAllocaMap.end()) {
277 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
280 .addFrameIndex(SI->second)
288 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
289 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
291 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
292 const ConstantInt *CI = cast<ConstantInt>(C);
293 return materialize32BitInt(CI->getZExtValue(), RC);
296 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
297 const TargetRegisterClass *RC) {
298 unsigned ResultReg = createResultReg(RC);
300 if (isInt<16>(Imm)) {
301 unsigned Opc = Mips::ADDiu;
302 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
304 } else if (isUInt<16>(Imm)) {
305 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
308 unsigned Lo = Imm & 0xFFFF;
309 unsigned Hi = (Imm >> 16) & 0xFFFF;
311 // Both Lo and Hi have nonzero bits.
312 unsigned TmpReg = createResultReg(RC);
313 emitInst(Mips::LUi, TmpReg).addImm(Hi);
314 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
316 emitInst(Mips::LUi, ResultReg).addImm(Hi);
321 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
322 if (UnsupportedFPMode)
324 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
325 if (VT == MVT::f32) {
326 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
327 unsigned DestReg = createResultReg(RC);
328 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
329 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
331 } else if (VT == MVT::f64) {
332 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
333 unsigned DestReg = createResultReg(RC);
334 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
336 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
337 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
343 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
344 // For now 32-bit only.
347 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
348 unsigned DestReg = createResultReg(RC);
349 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
350 bool IsThreadLocal = GVar && GVar->isThreadLocal();
351 // TLS not supported at this time.
354 emitInst(Mips::LW, DestReg)
355 .addReg(MFI->getGlobalBaseReg())
356 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
357 if ((GV->hasInternalLinkage() ||
358 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
359 unsigned TempReg = createResultReg(RC);
360 emitInst(Mips::ADDiu, TempReg)
362 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
368 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
369 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
370 unsigned DestReg = createResultReg(RC);
371 emitInst(Mips::LW, DestReg)
372 .addReg(MFI->getGlobalBaseReg())
373 .addSym(Sym, MipsII::MO_GOT);
377 // Materialize a constant into a register, and return the register
378 // number (or zero if we failed to handle it).
379 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
380 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
382 // Only handle simple types.
383 if (!CEVT.isSimple())
385 MVT VT = CEVT.getSimpleVT();
387 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
388 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
389 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
390 return materializeGV(GV, VT);
391 else if (isa<ConstantInt>(C))
392 return materializeInt(C, VT);
397 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
399 const User *U = nullptr;
400 unsigned Opcode = Instruction::UserOp1;
401 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
402 // Don't walk into other basic blocks unless the object is an alloca from
403 // another block, otherwise it may not have a virtual register assigned.
404 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
405 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
406 Opcode = I->getOpcode();
409 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
410 Opcode = C->getOpcode();
416 case Instruction::BitCast: {
417 // Look through bitcasts.
418 return computeAddress(U->getOperand(0), Addr);
420 case Instruction::GetElementPtr: {
421 Address SavedAddr = Addr;
422 uint64_t TmpOffset = Addr.getOffset();
423 // Iterate through the GEP folding the constants into offsets where
425 gep_type_iterator GTI = gep_type_begin(U);
426 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
428 const Value *Op = *i;
429 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
430 const StructLayout *SL = DL.getStructLayout(STy);
431 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
432 TmpOffset += SL->getElementOffset(Idx);
434 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
436 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
437 // Constant-offset addressing.
438 TmpOffset += CI->getSExtValue() * S;
441 if (canFoldAddIntoGEP(U, Op)) {
442 // A compatible add with a constant operand. Fold the constant.
444 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
445 TmpOffset += CI->getSExtValue() * S;
446 // Iterate on the other operand.
447 Op = cast<AddOperator>(Op)->getOperand(0);
451 goto unsupported_gep;
455 // Try to grab the base operand now.
456 Addr.setOffset(TmpOffset);
457 if (computeAddress(U->getOperand(0), Addr))
459 // We failed, restore everything and try the other options.
464 case Instruction::Alloca: {
465 const AllocaInst *AI = cast<AllocaInst>(Obj);
466 DenseMap<const AllocaInst *, int>::iterator SI =
467 FuncInfo.StaticAllocaMap.find(AI);
468 if (SI != FuncInfo.StaticAllocaMap.end()) {
469 Addr.setKind(Address::FrameIndexBase);
470 Addr.setFI(SI->second);
476 Addr.setReg(getRegForValue(Obj));
477 return Addr.getReg() != 0;
480 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
481 const User *U = nullptr;
482 unsigned Opcode = Instruction::UserOp1;
484 if (const auto *I = dyn_cast<Instruction>(V)) {
485 // Check if the value is defined in the same basic block. This information
486 // is crucial to know whether or not folding an operand is valid.
487 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
488 Opcode = I->getOpcode();
491 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
492 Opcode = C->getOpcode();
499 case Instruction::BitCast:
500 // Look past bitcasts if its operand is in the same BB.
501 return computeCallAddress(U->getOperand(0), Addr);
503 case Instruction::IntToPtr:
504 // Look past no-op inttoptrs if its operand is in the same BB.
505 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
506 TLI.getPointerTy(DL))
507 return computeCallAddress(U->getOperand(0), Addr);
509 case Instruction::PtrToInt:
510 // Look past no-op ptrtoints if its operand is in the same BB.
511 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
512 return computeCallAddress(U->getOperand(0), Addr);
516 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
517 Addr.setGlobalValue(GV);
521 // If all else fails, try to materialize the value in a register.
522 if (!Addr.getGlobalValue()) {
523 Addr.setReg(getRegForValue(V));
524 return Addr.getReg() != 0;
530 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
531 EVT evt = TLI.getValueType(DL, Ty, true);
532 // Only handle simple types.
533 if (evt == MVT::Other || !evt.isSimple())
535 VT = evt.getSimpleVT();
537 // Handle all legal types, i.e. a register that will directly hold this
539 return TLI.isTypeLegal(VT);
542 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
543 if (Ty->isVectorTy())
546 if (isTypeLegal(Ty, VT))
549 // If this is a type than can be sign or zero-extended to a basic operation
550 // go ahead and accept it now.
551 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
557 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
558 if (isTypeLegal(Ty, VT))
560 // We will extend this in a later patch:
561 // If this is a type than can be sign or zero-extended to a basic operation
562 // go ahead and accept it now.
563 if (VT == MVT::i8 || VT == MVT::i16)
567 // Because of how EmitCmp is called with fast-isel, you can
568 // end up with redundant "andi" instructions after the sequences emitted below.
569 // We should try and solve this issue in the future.
571 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
572 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
573 bool IsUnsigned = CI->isUnsigned();
574 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
577 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
580 CmpInst::Predicate P = CI->getPredicate();
585 case CmpInst::ICMP_EQ: {
586 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
587 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
588 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
591 case CmpInst::ICMP_NE: {
592 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
593 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
594 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
597 case CmpInst::ICMP_UGT: {
598 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
601 case CmpInst::ICMP_ULT: {
602 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
605 case CmpInst::ICMP_UGE: {
606 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
607 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
608 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
611 case CmpInst::ICMP_ULE: {
612 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
613 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
614 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
617 case CmpInst::ICMP_SGT: {
618 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
621 case CmpInst::ICMP_SLT: {
622 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
625 case CmpInst::ICMP_SGE: {
626 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
627 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
628 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
631 case CmpInst::ICMP_SLE: {
632 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
633 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
634 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
637 case CmpInst::FCMP_OEQ:
638 case CmpInst::FCMP_UNE:
639 case CmpInst::FCMP_OLT:
640 case CmpInst::FCMP_OLE:
641 case CmpInst::FCMP_OGT:
642 case CmpInst::FCMP_OGE: {
643 if (UnsupportedFPMode)
645 bool IsFloat = Left->getType()->isFloatTy();
646 bool IsDouble = Left->getType()->isDoubleTy();
647 if (!IsFloat && !IsDouble)
649 unsigned Opc, CondMovOpc;
651 case CmpInst::FCMP_OEQ:
652 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
653 CondMovOpc = Mips::MOVT_I;
655 case CmpInst::FCMP_UNE:
656 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
657 CondMovOpc = Mips::MOVF_I;
659 case CmpInst::FCMP_OLT:
660 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
661 CondMovOpc = Mips::MOVT_I;
663 case CmpInst::FCMP_OLE:
664 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
665 CondMovOpc = Mips::MOVT_I;
667 case CmpInst::FCMP_OGT:
668 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
669 CondMovOpc = Mips::MOVF_I;
671 case CmpInst::FCMP_OGE:
672 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
673 CondMovOpc = Mips::MOVF_I;
676 llvm_unreachable("Only switching of a subset of CCs.");
678 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
679 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
680 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
681 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
682 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
683 Mips::FCC0, RegState::ImplicitDefine);
684 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
687 .addReg(RegWithZero, RegState::Implicit);
688 MI->tieOperands(0, 3);
694 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
695 unsigned Alignment) {
697 // more cases will be handled here in following patches.
700 switch (VT.SimpleTy) {
702 ResultReg = createResultReg(&Mips::GPR32RegClass);
707 ResultReg = createResultReg(&Mips::GPR32RegClass);
712 ResultReg = createResultReg(&Mips::GPR32RegClass);
717 if (UnsupportedFPMode)
719 ResultReg = createResultReg(&Mips::FGR32RegClass);
724 if (UnsupportedFPMode)
726 ResultReg = createResultReg(&Mips::AFGR64RegClass);
733 if (Addr.isRegBase()) {
734 simplifyAddress(Addr);
735 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
738 if (Addr.isFIBase()) {
739 unsigned FI = Addr.getFI();
741 unsigned Offset = Addr.getOffset();
742 MachineFrameInfo &MFI = *MF->getFrameInfo();
743 MachineMemOperand *MMO = MF->getMachineMemOperand(
744 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
745 MFI.getObjectSize(FI), Align);
746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
755 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
756 unsigned Alignment) {
758 // more cases will be handled here in following patches.
761 switch (VT.SimpleTy) {
772 if (UnsupportedFPMode)
777 if (UnsupportedFPMode)
784 if (Addr.isRegBase()) {
785 simplifyAddress(Addr);
786 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
789 if (Addr.isFIBase()) {
790 unsigned FI = Addr.getFI();
792 unsigned Offset = Addr.getOffset();
793 MachineFrameInfo &MFI = *MF->getFrameInfo();
794 MachineMemOperand *MMO = MF->getMachineMemOperand(
795 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
796 MFI.getObjectSize(FI), Align);
797 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
807 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
809 if (!isTypeSupported(I->getType(), VT))
813 switch (I->getOpcode()) {
815 llvm_unreachable("Unexpected instruction.");
816 case Instruction::And:
817 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
819 case Instruction::Or:
820 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
822 case Instruction::Xor:
823 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
830 updateValueMap(I, ResultReg);
834 bool MipsFastISel::selectLoad(const Instruction *I) {
835 // Atomic loads need special handling.
836 if (cast<LoadInst>(I)->isAtomic())
839 // Verify we have a legal type before going any further.
841 if (!isLoadTypeLegal(I->getType(), VT))
844 // See if we can handle this address.
846 if (!computeAddress(I->getOperand(0), Addr))
850 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
852 updateValueMap(I, ResultReg);
856 bool MipsFastISel::selectStore(const Instruction *I) {
857 Value *Op0 = I->getOperand(0);
860 // Atomic stores need special handling.
861 if (cast<StoreInst>(I)->isAtomic())
864 // Verify we have a legal type before going any further.
866 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
869 // Get the value to be stored into a register.
870 SrcReg = getRegForValue(Op0);
874 // See if we can handle this address.
876 if (!computeAddress(I->getOperand(1), Addr))
879 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
885 // This can cause a redundant sltiu to be generated.
886 // FIXME: try and eliminate this in a future patch.
888 bool MipsFastISel::selectBranch(const Instruction *I) {
889 const BranchInst *BI = cast<BranchInst>(I);
890 MachineBasicBlock *BrBB = FuncInfo.MBB;
892 // TBB is the basic block for the case where the comparison is true.
893 // FBB is the basic block for the case where the comparison is false.
894 // if (cond) goto TBB
898 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
899 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
901 // For now, just try the simplest case where it's fed by a compare.
902 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
903 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
904 if (!emitCmp(CondReg, CI))
906 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
909 fastEmitBranch(FBB, DbgLoc);
910 FuncInfo.MBB->addSuccessor(TBB);
916 bool MipsFastISel::selectCmp(const Instruction *I) {
917 const CmpInst *CI = cast<CmpInst>(I);
918 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
919 if (!emitCmp(ResultReg, CI))
921 updateValueMap(I, ResultReg);
925 // Attempt to fast-select a floating-point extend instruction.
926 bool MipsFastISel::selectFPExt(const Instruction *I) {
927 if (UnsupportedFPMode)
929 Value *Src = I->getOperand(0);
930 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
931 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
933 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
937 getRegForValue(Src); // his must be a 32 bit floating point register class
938 // maybe we should handle this differently
942 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
943 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
944 updateValueMap(I, DestReg);
948 bool MipsFastISel::selectSelect(const Instruction *I) {
949 assert(isa<SelectInst>(I) && "Expected a select instruction.");
952 if (!isTypeSupported(I->getType(), VT))
956 const TargetRegisterClass *RC;
958 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
959 CondMovOpc = Mips::MOVN_I_I;
960 RC = &Mips::GPR32RegClass;
961 } else if (VT == MVT::f32) {
962 CondMovOpc = Mips::MOVN_I_S;
963 RC = &Mips::FGR32RegClass;
964 } else if (VT == MVT::f64) {
965 CondMovOpc = Mips::MOVN_I_D32;
966 RC = &Mips::AFGR64RegClass;
970 const SelectInst *SI = cast<SelectInst>(I);
971 const Value *Cond = SI->getCondition();
972 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
973 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
974 unsigned CondReg = getRegForValue(Cond);
976 if (!Src1Reg || !Src2Reg || !CondReg)
979 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
983 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
986 unsigned ResultReg = createResultReg(RC);
987 unsigned TempReg = createResultReg(RC);
989 if (!ResultReg || !TempReg)
992 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
993 emitInst(CondMovOpc, ResultReg)
994 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
995 updateValueMap(I, ResultReg);
999 // Attempt to fast-select a floating-point truncate instruction.
1000 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1001 if (UnsupportedFPMode)
1003 Value *Src = I->getOperand(0);
1004 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1005 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1007 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1010 unsigned SrcReg = getRegForValue(Src);
1014 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1018 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1019 updateValueMap(I, DestReg);
1023 // Attempt to fast-select a floating-point-to-integer conversion.
1024 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1025 if (UnsupportedFPMode)
1029 return false; // We don't handle this case yet. There is no native
1030 // instruction for this but it can be synthesized.
1031 Type *DstTy = I->getType();
1032 if (!isTypeLegal(DstTy, DstVT))
1035 if (DstVT != MVT::i32)
1038 Value *Src = I->getOperand(0);
1039 Type *SrcTy = Src->getType();
1040 if (!isTypeLegal(SrcTy, SrcVT))
1043 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1046 unsigned SrcReg = getRegForValue(Src);
1050 // Determine the opcode for the conversion, which takes place
1051 // entirely within FPRs.
1052 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1053 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1056 if (SrcVT == MVT::f32)
1057 Opc = Mips::TRUNC_W_S;
1059 Opc = Mips::TRUNC_W_D32;
1061 // Generate the convert.
1062 emitInst(Opc, TempReg).addReg(SrcReg);
1064 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1066 updateValueMap(I, DestReg);
1070 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1071 SmallVectorImpl<MVT> &OutVTs,
1072 unsigned &NumBytes) {
1073 CallingConv::ID CC = CLI.CallConv;
1074 SmallVector<CCValAssign, 16> ArgLocs;
1075 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1076 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1077 // Get a count of how many bytes are to be pushed on the stack.
1078 NumBytes = CCInfo.getNextStackOffset();
1079 // This is the minimum argument area used for A0-A3.
1083 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1084 // Process the args.
1086 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1087 CCValAssign &VA = ArgLocs[i];
1088 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1089 MVT ArgVT = OutVTs[VA.getValNo()];
1093 if (ArgVT == MVT::f32) {
1094 VA.convertToReg(Mips::F12);
1095 } else if (ArgVT == MVT::f64) {
1096 VA.convertToReg(Mips::D6);
1098 } else if (i == 1) {
1099 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1100 if (ArgVT == MVT::f32) {
1101 VA.convertToReg(Mips::F14);
1102 } else if (ArgVT == MVT::f64) {
1103 VA.convertToReg(Mips::D7);
1107 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1108 (ArgVT == MVT::i8)) &&
1110 switch (VA.getLocMemOffset()) {
1112 VA.convertToReg(Mips::A0);
1115 VA.convertToReg(Mips::A1);
1118 VA.convertToReg(Mips::A2);
1121 VA.convertToReg(Mips::A3);
1127 unsigned ArgReg = getRegForValue(ArgVal);
1131 // Handle arg promotion: SExt, ZExt, AExt.
1132 switch (VA.getLocInfo()) {
1133 case CCValAssign::Full:
1135 case CCValAssign::AExt:
1136 case CCValAssign::SExt: {
1137 MVT DestVT = VA.getLocVT();
1139 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1144 case CCValAssign::ZExt: {
1145 MVT DestVT = VA.getLocVT();
1147 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1153 llvm_unreachable("Unknown arg promotion!");
1156 // Now copy/store arg to correct locations.
1157 if (VA.isRegLoc() && !VA.needsCustom()) {
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1159 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1160 CLI.OutRegs.push_back(VA.getLocReg());
1161 } else if (VA.needsCustom()) {
1162 llvm_unreachable("Mips does not use custom args.");
1166 // FIXME: This path will currently return false. It was copied
1167 // from the AArch64 port and should be essentially fine for Mips too.
1168 // The work to finish up this path will be done in a follow-on patch.
1170 assert(VA.isMemLoc() && "Assuming store on stack.");
1171 // Don't emit stores for undef values.
1172 if (isa<UndefValue>(ArgVal))
1175 // Need to store on the stack.
1176 // FIXME: This alignment is incorrect but this path is disabled
1177 // for now (will return false). We need to determine the right alignment
1178 // based on the normal alignment for the underlying machine type.
1180 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1182 unsigned BEAlign = 0;
1183 if (ArgSize < 8 && !Subtarget->isLittle())
1184 BEAlign = 8 - ArgSize;
1187 Addr.setKind(Address::RegBase);
1188 Addr.setReg(Mips::SP);
1189 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1191 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1192 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1193 MachinePointerInfo::getStack(Addr.getOffset()),
1194 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1196 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1197 return false; // can't store on the stack yet.
1204 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1205 unsigned NumBytes) {
1206 CallingConv::ID CC = CLI.CallConv;
1207 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1208 if (RetVT != MVT::isVoid) {
1209 SmallVector<CCValAssign, 16> RVLocs;
1210 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1211 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1213 // Only handle a single return value.
1214 if (RVLocs.size() != 1)
1216 // Copy all of the result registers out of their specified physreg.
1217 MVT CopyVT = RVLocs[0].getValVT();
1218 // Special handling for extended integers.
1219 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1222 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1226 TII.get(TargetOpcode::COPY),
1227 ResultReg).addReg(RVLocs[0].getLocReg());
1228 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1230 CLI.ResultReg = ResultReg;
1231 CLI.NumResultRegs = 1;
1236 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1237 CallingConv::ID CC = CLI.CallConv;
1238 bool IsTailCall = CLI.IsTailCall;
1239 bool IsVarArg = CLI.IsVarArg;
1240 const Value *Callee = CLI.Callee;
1241 MCSymbol *Symbol = CLI.Symbol;
1243 // Do not handle FastCC.
1244 if (CC == CallingConv::Fast)
1247 // Allow SelectionDAG isel to handle tail calls.
1251 // Let SDISel handle vararg functions.
1255 // FIXME: Only handle *simple* calls for now.
1257 if (CLI.RetTy->isVoidTy())
1258 RetVT = MVT::isVoid;
1259 else if (!isTypeSupported(CLI.RetTy, RetVT))
1262 for (auto Flag : CLI.OutFlags)
1263 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1266 // Set up the argument vectors.
1267 SmallVector<MVT, 16> OutVTs;
1268 OutVTs.reserve(CLI.OutVals.size());
1270 for (auto *Val : CLI.OutVals) {
1272 if (!isTypeLegal(Val->getType(), VT) &&
1273 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1276 // We don't handle vector parameters yet.
1277 if (VT.isVector() || VT.getSizeInBits() > 64)
1280 OutVTs.push_back(VT);
1284 if (!computeCallAddress(Callee, Addr))
1287 // Handle the arguments now that we've gotten them.
1289 if (!processCallArgs(CLI, OutVTs, NumBytes))
1292 if (!Addr.getGlobalValue())
1296 unsigned DestAddress;
1298 DestAddress = materializeExternalCallSym(Symbol);
1300 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1301 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1302 MachineInstrBuilder MIB =
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1304 Mips::RA).addReg(Mips::T9);
1306 // Add implicit physical register uses to the call.
1307 for (auto Reg : CLI.OutRegs)
1308 MIB.addReg(Reg, RegState::Implicit);
1310 // Add a register mask with the call-preserved registers.
1311 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1312 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1316 // Finish off the call including any return values.
1317 return finishCall(CLI, RetVT, NumBytes);
1320 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1321 switch (II->getIntrinsicID()) {
1324 case Intrinsic::bswap: {
1325 Type *RetTy = II->getCalledFunction()->getReturnType();
1328 if (!isTypeSupported(RetTy, VT))
1331 unsigned SrcReg = getRegForValue(II->getOperand(0));
1334 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1337 if (VT == MVT::i16) {
1338 if (Subtarget->hasMips32r2()) {
1339 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1340 updateValueMap(II, DestReg);
1343 unsigned TempReg[3];
1344 for (int i = 0; i < 3; i++) {
1345 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1346 if (TempReg[i] == 0)
1349 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1350 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1351 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1352 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1353 updateValueMap(II, DestReg);
1356 } else if (VT == MVT::i32) {
1357 if (Subtarget->hasMips32r2()) {
1358 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1359 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1360 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1361 updateValueMap(II, DestReg);
1364 unsigned TempReg[8];
1365 for (int i = 0; i < 8; i++) {
1366 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1367 if (TempReg[i] == 0)
1371 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1372 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1373 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1374 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1376 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1377 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1379 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1380 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1381 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1382 updateValueMap(II, DestReg);
1388 case Intrinsic::memcpy:
1389 case Intrinsic::memmove: {
1390 const auto *MTI = cast<MemTransferInst>(II);
1391 // Don't handle volatile.
1392 if (MTI->isVolatile())
1394 if (!MTI->getLength()->getType()->isIntegerTy(32))
1396 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1397 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1399 case Intrinsic::memset: {
1400 const MemSetInst *MSI = cast<MemSetInst>(II);
1401 // Don't handle volatile.
1402 if (MSI->isVolatile())
1404 if (!MSI->getLength()->getType()->isIntegerTy(32))
1406 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1412 bool MipsFastISel::selectRet(const Instruction *I) {
1413 const Function &F = *I->getParent()->getParent();
1414 const ReturnInst *Ret = cast<ReturnInst>(I);
1416 if (!FuncInfo.CanLowerReturn)
1419 // Build a list of return value registers.
1420 SmallVector<unsigned, 4> RetRegs;
1422 if (Ret->getNumOperands() > 0) {
1423 CallingConv::ID CC = F.getCallingConv();
1425 // Do not handle FastCC.
1426 if (CC == CallingConv::Fast)
1429 SmallVector<ISD::OutputArg, 4> Outs;
1430 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1432 // Analyze operands of the call, assigning locations to each operand.
1433 SmallVector<CCValAssign, 16> ValLocs;
1434 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1436 CCAssignFn *RetCC = RetCC_Mips;
1437 CCInfo.AnalyzeReturn(Outs, RetCC);
1439 // Only handle a single return value for now.
1440 if (ValLocs.size() != 1)
1443 CCValAssign &VA = ValLocs[0];
1444 const Value *RV = Ret->getOperand(0);
1446 // Don't bother handling odd stuff for now.
1447 if ((VA.getLocInfo() != CCValAssign::Full) &&
1448 (VA.getLocInfo() != CCValAssign::BCvt))
1451 // Only handle register returns for now.
1455 unsigned Reg = getRegForValue(RV);
1459 unsigned SrcReg = Reg + VA.getValNo();
1460 unsigned DestReg = VA.getLocReg();
1461 // Avoid a cross-class copy. This is very unlikely.
1462 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1465 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1466 if (!RVEVT.isSimple())
1469 if (RVEVT.isVector())
1472 MVT RVVT = RVEVT.getSimpleVT();
1473 if (RVVT == MVT::f128)
1476 MVT DestVT = VA.getValVT();
1477 // Special handling for extended integers.
1478 if (RVVT != DestVT) {
1479 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1482 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1483 bool IsZExt = Outs[0].Flags.isZExt();
1484 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1492 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1494 // Add register to return instruction.
1495 RetRegs.push_back(VA.getLocReg());
1497 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1498 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1499 MIB.addReg(RetRegs[i], RegState::Implicit);
1503 bool MipsFastISel::selectTrunc(const Instruction *I) {
1504 // The high bits for a type smaller than the register size are assumed to be
1506 Value *Op = I->getOperand(0);
1509 SrcVT = TLI.getValueType(DL, Op->getType(), true);
1510 DestVT = TLI.getValueType(DL, I->getType(), true);
1512 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1514 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1517 unsigned SrcReg = getRegForValue(Op);
1521 // Because the high bits are undefined, a truncate doesn't generate
1523 updateValueMap(I, SrcReg);
1526 bool MipsFastISel::selectIntExt(const Instruction *I) {
1527 Type *DestTy = I->getType();
1528 Value *Src = I->getOperand(0);
1529 Type *SrcTy = Src->getType();
1531 bool isZExt = isa<ZExtInst>(I);
1532 unsigned SrcReg = getRegForValue(Src);
1536 EVT SrcEVT, DestEVT;
1537 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1538 DestEVT = TLI.getValueType(DL, DestTy, true);
1539 if (!SrcEVT.isSimple())
1541 if (!DestEVT.isSimple())
1544 MVT SrcVT = SrcEVT.getSimpleVT();
1545 MVT DestVT = DestEVT.getSimpleVT();
1546 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1548 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1550 updateValueMap(I, ResultReg);
1553 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1556 switch (SrcVT.SimpleTy) {
1566 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1567 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1568 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1572 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1574 switch (SrcVT.SimpleTy) {
1578 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1581 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1587 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1589 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1591 if (Subtarget->hasMips32r2())
1592 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1593 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1596 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1598 switch (SrcVT.SimpleTy) {
1602 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1605 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1608 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1614 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1615 unsigned DestReg, bool IsZExt) {
1616 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1617 // DestVT are odd things, so test to make sure that they are both types we can
1618 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1619 // bail out to SelectionDAG.
1620 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1621 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1624 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1625 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1628 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1630 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1631 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1632 return Success ? DestReg : 0;
1635 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1636 EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1637 if (!DestEVT.isSimple())
1640 MVT DestVT = DestEVT.getSimpleVT();
1641 if (DestVT != MVT::i32)
1645 switch (ISDOpcode) {
1650 DivOpc = Mips::SDIV;
1654 DivOpc = Mips::UDIV;
1658 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1659 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1660 if (!Src0Reg || !Src1Reg)
1663 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1664 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1666 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1670 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1673 emitInst(MFOpc, ResultReg);
1675 updateValueMap(I, ResultReg);
1679 bool MipsFastISel::selectShift(const Instruction *I) {
1682 if (!isTypeSupported(I->getType(), RetVT))
1685 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1689 unsigned Opcode = I->getOpcode();
1690 const Value *Op0 = I->getOperand(0);
1691 unsigned Op0Reg = getRegForValue(Op0);
1695 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1696 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1697 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1701 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1702 bool IsZExt = Opcode == Instruction::LShr;
1703 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1709 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1710 uint64_t ShiftVal = C->getZExtValue();
1714 llvm_unreachable("Unexpected instruction.");
1715 case Instruction::Shl:
1718 case Instruction::AShr:
1721 case Instruction::LShr:
1726 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1727 updateValueMap(I, ResultReg);
1731 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1737 llvm_unreachable("Unexpected instruction.");
1738 case Instruction::Shl:
1739 Opcode = Mips::SLLV;
1741 case Instruction::AShr:
1742 Opcode = Mips::SRAV;
1744 case Instruction::LShr:
1745 Opcode = Mips::SRLV;
1749 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1750 updateValueMap(I, ResultReg);
1754 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1755 if (!TargetSupported)
1757 switch (I->getOpcode()) {
1760 case Instruction::Load:
1761 return selectLoad(I);
1762 case Instruction::Store:
1763 return selectStore(I);
1764 case Instruction::SDiv:
1765 if (!selectBinaryOp(I, ISD::SDIV))
1766 return selectDivRem(I, ISD::SDIV);
1768 case Instruction::UDiv:
1769 if (!selectBinaryOp(I, ISD::UDIV))
1770 return selectDivRem(I, ISD::UDIV);
1772 case Instruction::SRem:
1773 if (!selectBinaryOp(I, ISD::SREM))
1774 return selectDivRem(I, ISD::SREM);
1776 case Instruction::URem:
1777 if (!selectBinaryOp(I, ISD::UREM))
1778 return selectDivRem(I, ISD::UREM);
1780 case Instruction::Shl:
1781 case Instruction::LShr:
1782 case Instruction::AShr:
1783 return selectShift(I);
1784 case Instruction::And:
1785 case Instruction::Or:
1786 case Instruction::Xor:
1787 return selectLogicalOp(I);
1788 case Instruction::Br:
1789 return selectBranch(I);
1790 case Instruction::Ret:
1791 return selectRet(I);
1792 case Instruction::Trunc:
1793 return selectTrunc(I);
1794 case Instruction::ZExt:
1795 case Instruction::SExt:
1796 return selectIntExt(I);
1797 case Instruction::FPTrunc:
1798 return selectFPTrunc(I);
1799 case Instruction::FPExt:
1800 return selectFPExt(I);
1801 case Instruction::FPToSI:
1802 return selectFPToInt(I, /*isSigned*/ true);
1803 case Instruction::FPToUI:
1804 return selectFPToInt(I, /*isSigned*/ false);
1805 case Instruction::ICmp:
1806 case Instruction::FCmp:
1807 return selectCmp(I);
1808 case Instruction::Select:
1809 return selectSelect(I);
1814 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1816 unsigned VReg = getRegForValue(V);
1819 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
1820 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1821 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1822 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1829 void MipsFastISel::simplifyAddress(Address &Addr) {
1830 if (!isInt<16>(Addr.getOffset())) {
1832 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1833 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1834 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1835 Addr.setReg(DestReg);
1840 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1841 const TargetRegisterClass *RC,
1842 unsigned Op0, bool Op0IsKill,
1843 unsigned Op1, bool Op1IsKill) {
1844 // We treat the MUL instruction in a special way because it clobbers
1845 // the HI0 & LO0 registers. The TableGen definition of this instruction can
1846 // mark these registers only as implicitly defined. As a result, the
1847 // register allocator runs out of registers when this instruction is
1848 // followed by another instruction that defines the same registers too.
1849 // We can fix this by explicitly marking those registers as dead.
1850 if (MachineInstOpcode == Mips::MUL) {
1851 unsigned ResultReg = createResultReg(RC);
1852 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1853 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1854 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1856 .addReg(Op0, getKillRegState(Op0IsKill))
1857 .addReg(Op1, getKillRegState(Op1IsKill))
1858 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1859 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1863 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1868 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1869 const TargetLibraryInfo *libInfo) {
1870 return new MipsFastISel(funcInfo, libInfo);