1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
85 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
86 EVT Ty, bool HasLo, bool HasHi);
88 SDNode *Select(SDNode *N);
91 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
93 // getImm - Return a target constant with the specified value.
94 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
98 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
100 std::vector<SDValue> &OutOps);
106 /// getGlobalBaseReg - Output the instructions required to put the
107 /// GOT address into a register.
108 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
109 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
110 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
113 /// ComplexPattern used on MipsInstrInfo
114 /// Used on Mips Load/Store instructions
115 bool MipsDAGToDAGISel::
116 SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
117 EVT ValTy = Addr.getValueType();
118 unsigned GPReg = ValTy == MVT::i32 ? Mips::GP : Mips::GP_64;
120 // if Address is FI, get the TargetFrameIndex.
121 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
122 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
123 Offset = CurDAG->getTargetConstant(0, ValTy);
127 // on PIC code Load GA
128 if (Addr.getOpcode() == MipsISD::Wrapper) {
129 Base = CurDAG->getRegister(GPReg, ValTy);
130 Offset = Addr.getOperand(0);
134 if (TM.getRelocationModel() != Reloc::PIC_) {
135 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
136 Addr.getOpcode() == ISD::TargetGlobalAddress))
140 // Addresses of the form FI+const or FI|const
141 if (CurDAG->isBaseWithConstantOffset(Addr)) {
142 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
143 if (isInt<16>(CN->getSExtValue())) {
145 // If the first operand is a FI, get the TargetFI Node
146 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
147 (Addr.getOperand(0)))
148 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
150 Base = Addr.getOperand(0);
152 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
157 // Operand is a result from an ADD.
158 if (Addr.getOpcode() == ISD::ADD) {
159 // When loading from constant pools, load the lower address part in
160 // the instruction itself. Example, instead of:
161 // lui $2, %hi($CPI1_0)
162 // addiu $2, $2, %lo($CPI1_0)
165 // lui $2, %hi($CPI1_0)
166 // lwc1 $f0, %lo($CPI1_0)($2)
167 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
168 SDValue LoVal = Addr.getOperand(1);
169 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
170 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
171 Base = Addr.getOperand(0);
172 Offset = LoVal.getOperand(0);
179 Offset = CurDAG->getTargetConstant(0, ValTy);
183 /// Select multiply instructions.
184 std::pair<SDNode*, SDNode*>
185 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
186 bool HasLo, bool HasHi) {
187 SDNode *Lo = 0, *Hi = 0;
188 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
190 SDValue InFlag = SDValue(Mul, 0);
193 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
194 Ty, MVT::Glue, InFlag);
195 InFlag = SDValue(Lo, 1);
198 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
201 return std::make_pair(Lo, Hi);
205 /// Select instructions not customized! Used for
206 /// expanded, promoted and normal instructions
207 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
208 unsigned Opcode = Node->getOpcode();
209 DebugLoc dl = Node->getDebugLoc();
211 // Dump information about the Node being selected
212 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
214 // If we have a custom node, we already have selected!
215 if (Node->isMachineOpcode()) {
216 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
221 // Instruction Selection not handled by the auto-generated
222 // tablegen selection should be handled here.
224 EVT NodeTy = Node->getValueType(0);
232 SDValue InFlag = Node->getOperand(2), CmpLHS;
233 unsigned Opc = InFlag.getOpcode(); (void)Opc;
234 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
235 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
236 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239 if (Opcode == ISD::ADDE) {
240 CmpLHS = InFlag.getValue(0);
243 CmpLHS = InFlag.getOperand(0);
247 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
249 SDValue LHS = Node->getOperand(0);
250 SDValue RHS = Node->getOperand(1);
252 EVT VT = LHS.getValueType();
253 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
254 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
255 SDValue(Carry,0), RHS);
257 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
258 LHS, SDValue(AddCarry,0));
261 /// Mul with two results
263 case ISD::UMUL_LOHI: {
264 if (NodeTy == MVT::i32)
265 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
267 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
269 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
272 if (!SDValue(Node, 0).use_empty())
273 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
275 if (!SDValue(Node, 1).use_empty())
276 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
283 // Mips32 has a 32-bit three operand mul instruction.
284 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
286 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
287 dl, NodeTy, true, false).first;
291 if (NodeTy == MVT::i32)
292 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
294 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
296 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
299 // Get target GOT address.
300 case ISD::GLOBAL_OFFSET_TABLE:
301 return getGlobalBaseReg();
303 case ISD::ConstantFP: {
304 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
305 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
306 if (Subtarget.hasMips64()) {
307 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
308 Mips::ZERO_64, MVT::i64);
309 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
312 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
313 Mips::ZERO, MVT::i32);
314 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
320 case MipsISD::ThreadPointer: {
321 EVT PtrVT = TLI.getPointerTy();
322 unsigned RdhwrOpc, SrcReg, DestReg;
324 if (PtrVT == MVT::i32) {
325 RdhwrOpc = Mips::RDHWR;
326 SrcReg = Mips::HWR29;
329 RdhwrOpc = Mips::RDHWR64;
330 SrcReg = Mips::HWR29_64;
331 DestReg = Mips::V1_64;
335 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
336 Node->getValueType(0),
337 CurDAG->getRegister(SrcReg, PtrVT));
338 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
340 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
341 ReplaceUses(SDValue(Node, 0), ResNode);
342 return ResNode.getNode();
346 // Select the default instruction
347 SDNode *ResNode = SelectCode(Node);
349 DEBUG(errs() << "=> ");
350 if (ResNode == NULL || ResNode == Node)
351 DEBUG(Node->dump(CurDAG));
353 DEBUG(ResNode->dump(CurDAG));
354 DEBUG(errs() << "\n");
358 bool MipsDAGToDAGISel::
359 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
360 std::vector<SDValue> &OutOps) {
361 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
362 OutOps.push_back(Op);
366 /// createMipsISelDag - This pass converts a legalized DAG into a
367 /// MIPS-specific DAG, ready for instruction scheduling.
368 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
369 return new MipsDAGToDAGISel(TM);