1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 SDNode *SelectLoadFp64(SDNode *N);
90 SDNode *SelectStoreFp64(SDNode *N);
92 // getI32Imm - Return a target constant with the specified
93 // value, of type i32.
94 inline SDValue getI32Imm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113 // if Address is FI, get the TargetFrameIndex.
114 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
120 // on PIC code Load GA
121 if (TM.getRelocationModel() == Reloc::PIC_) {
122 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
123 (Addr.getOpcode() == ISD::TargetConstantPool) ||
124 (Addr.getOpcode() == ISD::TargetJumpTable) ||
125 (Addr.getOpcode() == ISD::TargetBlockAddress) ||
126 (Addr.getOpcode() == ISD::TargetExternalSymbol)) {
127 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
132 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
133 Addr.getOpcode() == ISD::TargetGlobalAddress))
137 // Operand is a result from an ADD.
138 if (Addr.getOpcode() == ISD::ADD) {
139 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
140 if (isInt<16>(CN->getSExtValue())) {
142 // If the first operand is a FI, get the TargetFI Node
143 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
144 (Addr.getOperand(0))) {
145 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147 Base = Addr.getOperand(0);
150 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
155 // When loading from constant pools, load the lower address part in
156 // the instruction itself. Example, instead of:
157 // lui $2, %hi($CPI1_0)
158 // addiu $2, $2, %lo($CPI1_0)
161 // lui $2, %hi($CPI1_0)
162 // lwc1 $f0, %lo($CPI1_0)($2)
163 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
164 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
165 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
166 SDValue LoVal = Addr.getOperand(1);
167 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
168 Base = Addr.getOperand(0);
169 Offset = LoVal.getOperand(0);
176 Offset = CurDAG->getTargetConstant(0, MVT::i32);
180 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
181 MVT::SimpleValueType NVT =
182 N->getValueType(0).getSimpleVT().SimpleTy;
184 if (!Subtarget.isMips1() || NVT != MVT::f64)
187 LoadSDNode *LN = cast<LoadSDNode>(N);
188 if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
189 LN->getAddressingMode() != ISD::UNINDEXED)
192 SDValue Chain = N->getOperand(0);
193 SDValue N1 = N->getOperand(1);
194 SDValue Offset0, Offset1, Base;
196 if (!SelectAddr(N1, Offset0, Base) ||
197 N1.getValueType() != MVT::i32)
200 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
201 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
202 DebugLoc dl = N->getDebugLoc();
204 // The second load should start after for 4 bytes.
205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
206 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
207 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
208 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
212 CP->getTargetFlags());
216 // Choose the offsets depending on the endianess
217 if (TM.getTargetData()->isBigEndian())
218 std::swap(Offset0, Offset1);
225 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
226 MVT::Other, Offset0, Base, Chain);
227 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
229 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
230 MVT::f64, Undef, SDValue(LD0, 0));
232 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
233 MVT::Other, Offset1, Base, SDValue(LD0, 1));
234 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
235 MVT::f64, I0, SDValue(LD1, 0));
237 ReplaceUses(SDValue(N, 0), I1);
238 ReplaceUses(SDValue(N, 1), Chain);
239 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
240 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
244 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
246 if (!Subtarget.isMips1() ||
247 N->getOperand(1).getValueType() != MVT::f64)
250 SDValue Chain = N->getOperand(0);
252 StoreSDNode *SN = cast<StoreSDNode>(N);
253 if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
256 SDValue N1 = N->getOperand(1);
257 SDValue N2 = N->getOperand(2);
258 SDValue Offset0, Offset1, Base;
260 if (!SelectAddr(N2, Offset0, Base) ||
261 N1.getValueType() != MVT::f64 ||
262 N2.getValueType() != MVT::i32)
265 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
266 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
267 DebugLoc dl = N->getDebugLoc();
269 // Get the even and odd part from the f64 register
270 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
272 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
275 // The second store should start after for 4 bytes.
276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
277 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
281 // Choose the offsets depending on the endianess
282 if (TM.getTargetData()->isBigEndian())
283 std::swap(Offset0, Offset1);
290 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
291 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
292 MVT::Other, Ops0, 4), 0);
293 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
295 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
296 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
297 MVT::Other, Ops1, 4), 0);
298 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
300 ReplaceUses(SDValue(N, 0), Chain);
301 return Chain.getNode();
304 /// Select instructions not customized! Used for
305 /// expanded, promoted and normal instructions
306 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
307 unsigned Opcode = Node->getOpcode();
308 DebugLoc dl = Node->getDebugLoc();
310 // Dump information about the Node being selected
311 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
313 // If we have a custom node, we already have selected!
314 if (Node->isMachineOpcode()) {
315 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
320 // Instruction Selection not handled by the auto-generated
321 // tablegen selection should be handled here.
329 SDValue InFlag = Node->getOperand(2), CmpLHS;
330 unsigned Opc = InFlag.getOpcode(); (void)Opc;
331 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
332 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
333 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
336 if (Opcode == ISD::ADDE) {
337 CmpLHS = InFlag.getValue(0);
340 CmpLHS = InFlag.getOperand(0);
344 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
346 SDValue LHS = Node->getOperand(0);
347 SDValue RHS = Node->getOperand(1);
349 EVT VT = LHS.getValueType();
350 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
351 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
352 SDValue(Carry,0), RHS);
354 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
355 LHS, SDValue(AddCarry,0));
358 /// Mul/Div with two results
363 case ISD::UMUL_LOHI: {
364 SDValue Op1 = Node->getOperand(0);
365 SDValue Op2 = Node->getOperand(1);
368 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
370 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
372 SDValue InFlag = SDValue(Mul, 0);
373 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
375 InFlag = SDValue(Lo,1);
376 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
378 if (!SDValue(Node, 0).use_empty())
379 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
381 if (!SDValue(Node, 1).use_empty())
382 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
389 if (Subtarget.isMips32())
393 SDValue MulOp1 = Node->getOperand(0);
394 SDValue MulOp2 = Node->getOperand(1);
396 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
397 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
398 MVT::Glue, MulOp1, MulOp2);
400 SDValue InFlag = SDValue(MulNode, 0);
402 if (Opcode == ISD::MUL)
403 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
405 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
408 /// Div/Rem operations
415 // Get target GOT address.
416 case ISD::GLOBAL_OFFSET_TABLE:
417 return getGlobalBaseReg();
419 case ISD::ConstantFP: {
420 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
421 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
422 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
423 Mips::ZERO, MVT::i32);
424 SDValue Undef = SDValue(
425 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
426 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
427 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
428 MVT::f64, Undef, SDValue(MTC, 0));
429 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
430 MVT::f64, I0, SDValue(MTC, 0));
431 ReplaceUses(SDValue(Node, 0), I1);
438 if (SDNode *ResNode = SelectLoadFp64(Node))
440 // Other cases are autogenerated.
444 if (SDNode *ResNode = SelectStoreFp64(Node))
446 // Other cases are autogenerated.
450 // Select the default instruction
451 SDNode *ResNode = SelectCode(Node);
453 DEBUG(errs() << "=> ");
454 if (ResNode == NULL || ResNode == Node)
455 DEBUG(Node->dump(CurDAG));
457 DEBUG(ResNode->dump(CurDAG));
458 DEBUG(errs() << "\n");
462 /// createMipsISelDag - This pass converts a legalized DAG into a
463 /// MIPS-specific DAG, ready for instruction scheduling.
464 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
465 return new MipsDAGToDAGISel(TM);