1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// MipsLowering - This object fully describes how to lower LLVM code to an
56 /// Mips-specific SelectionDAG.
57 MipsTargetLowering MipsLowering;
59 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
60 /// make the right decision when generating code for different targets.
61 //TODO: add initialization on constructor
62 //const MipsSubtarget *Subtarget;
65 MipsDAGToDAGISel(MipsTargetMachine &tm) :
66 SelectionDAGISel(MipsLowering),
67 TM(tm), MipsLowering(*TM.getTargetLowering()) {}
69 virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
72 virtual const char *getPassName() const {
73 return "MIPS DAG->DAG Pattern Instruction Selection";
78 // Include the pieces autogenerated from the target description.
79 #include "MipsGenDAGISel.inc"
81 SDOperand getGlobalBaseReg();
82 SDNode *Select(SDOperand N);
85 bool SelectAddr(SDOperand Op, SDOperand N,
86 SDOperand &Base, SDOperand &Offset);
89 // getI32Imm - Return a target constant with the specified
90 // value, of type i32.
91 inline SDOperand getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
103 /// InstructionSelectBasicBlock - This callback is invoked by
104 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
105 void MipsDAGToDAGISel::
106 InstructionSelectBasicBlock(SelectionDAG &SD)
109 // Codegen the basic block.
111 DOUT << "===== Instruction selection begins:\n";
115 // Select target instructions for the DAG.
116 SD.setRoot(SelectRoot(SD.getRoot()));
119 DOUT << "===== Instruction selection ends:\n";
122 SD.RemoveDeadNodes();
124 // Emit machine code to BB.
125 ScheduleAndEmitDAG(SD);
128 /// getGlobalBaseReg - Output the instructions required to put the
129 /// GOT address into a register.
130 SDOperand MipsDAGToDAGISel::getGlobalBaseReg()
132 MachineFunction* MF = BB->getParent();
134 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
135 ee = MF->livein_end(); ii != ee; ++ii)
136 if (ii->first == Mips::GP) {
140 assert(GP && "GOT PTR not in liveins");
141 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
145 /// ComplexPattern used on MipsInstrInfo
146 /// Used on Mips Load/Store instructions
147 bool MipsDAGToDAGISel::
148 SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
150 // if Address is FI, get the TargetFrameIndex.
151 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
152 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
153 Offset = CurDAG->getTargetConstant(0, MVT::i32);
157 // on PIC code Load GA
158 if (TM.getRelocationModel() == Reloc::PIC_) {
159 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
160 (Addr.getOpcode() == ISD::TargetJumpTable)){
161 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
166 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
167 Addr.getOpcode() == ISD::TargetGlobalAddress))
171 // Operand is a result from an ADD.
172 if (Addr.getOpcode() == ISD::ADD) {
173 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
174 if (Predicate_immSExt16(CN)) {
176 // If the first operand is a FI, get the TargetFI Node
177 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
178 (Addr.getOperand(0))) {
179 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
181 Base = Addr.getOperand(0);
184 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
191 Offset = CurDAG->getTargetConstant(0, MVT::i32);
195 /// Select instructions not customized! Used for
196 /// expanded, promoted and normal instructions
197 SDNode* MipsDAGToDAGISel::
200 SDNode *Node = N.Val;
201 unsigned Opcode = Node->getOpcode();
203 // Dump information about the Node being selected
205 DOUT << std::string(Indent, ' ') << "Selecting: ";
206 DEBUG(Node->dump(CurDAG));
211 // If we have a custom node, we already have selected!
212 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < MipsISD::FIRST_NUMBER) {
214 DOUT << std::string(Indent-2, ' ') << "== ";
215 DEBUG(Node->dump(CurDAG));
223 // Instruction Selection not handled by the auto-generated
224 // tablegen selection should be handled here.
230 /// Special Mul operations
233 SDOperand MulOp1 = Node->getOperand(0);
234 SDOperand MulOp2 = Node->getOperand(1);
235 AddToISelQueue(MulOp1);
236 AddToISelQueue(MulOp2);
238 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
239 SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
241 SDOperand MFInFlag = SDOperand(MulNode, 0);
242 return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
248 SDOperand DivOp1 = Node->getOperand(0);
249 SDOperand DivOp2 = Node->getOperand(1);
250 AddToISelQueue(DivOp1);
251 AddToISelQueue(DivOp2);
253 unsigned DivOp = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
254 SDNode *DivNode = CurDAG->getTargetNode(DivOp, MVT::Flag, DivOp1, DivOp2);
256 SDOperand MFInFlag = SDOperand(DivNode, 0);
257 return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MFInFlag);
263 SDOperand RemOp1 = Node->getOperand(0);
264 SDOperand RemOp2 = Node->getOperand(1);
265 AddToISelQueue(RemOp1);
266 AddToISelQueue(RemOp2);
268 unsigned RemOp = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
269 SDNode *RemNode = CurDAG->getTargetNode(RemOp, MVT::Flag, RemOp1, RemOp2);
271 SDOperand MFInFlag = SDOperand(RemNode, 0);
272 return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
275 // Get target GOT address.
276 case ISD::GLOBAL_OFFSET_TABLE: {
277 SDOperand Result = getGlobalBaseReg();
278 ReplaceUses(N, Result);
282 /// Handle direct and indirect calls when using PIC. On PIC, when
283 /// GOT is smaller than about 64k (small code) the GA target is
284 /// loaded with only one instruction. Otherwise GA's target must
285 /// be loaded with 3 instructions.
286 case MipsISD::JmpLink: {
287 if (TM.getRelocationModel() == Reloc::PIC_) {
288 //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
289 SDOperand Chain = Node->getOperand(0);
290 SDOperand Callee = Node->getOperand(1);
291 AddToISelQueue(Chain);
292 SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
293 SDOperand InFlag(0, 0);
295 if ( (isa<GlobalAddressSDNode>(Callee)) ||
296 (isa<ExternalSymbolSDNode>(Callee)) )
298 /// Direct call for global addresses and external symbols
299 SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
301 // Use load to get GOT target
302 SDOperand Ops[] = { Callee, GPReg, Chain };
303 SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
304 MVT::Other, Ops, 3), 0);
305 Chain = Load.getValue(1);
306 AddToISelQueue(Chain);
308 // Call target must be on T9
309 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
312 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
314 AddToISelQueue(Chain);
316 // Emit Jump and Link Register
317 SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
318 MVT::Flag, T9Reg, Chain);
319 Chain = SDOperand(ResNode, 0);
320 InFlag = SDOperand(ResNode, 1);
321 ReplaceUses(SDOperand(Node, 0), Chain);
322 ReplaceUses(SDOperand(Node, 1), InFlag);
328 // Select the default instruction
329 SDNode *ResNode = SelectCode(N);
332 DOUT << std::string(Indent-2, ' ') << "=> ";
333 if (ResNode == NULL || ResNode == N.Val)
334 DEBUG(N.Val->dump(CurDAG));
336 DEBUG(ResNode->dump(CurDAG));
344 /// createMipsISelDag - This pass converts a legalized DAG into a
345 /// MIPS-specific DAG, ready for instruction scheduling.
346 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
347 return new MipsDAGToDAGISel(TM);