1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDNode *Op, SDValue N,
88 SDValue &Base, SDValue &Offset);
90 SDNode *SelectLoadFp64(SDNode *N);
91 SDNode *SelectStoreFp64(SDNode *N);
93 // getI32Imm - Return a target constant with the specified
94 // value, of type i32.
95 inline SDValue getI32Imm(unsigned Imm) {
96 return CurDAG->getTargetConstant(Imm, MVT::i32);
103 /// getGlobalBaseReg - Output the instructions required to put the
104 /// GOT address into a register.
105 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
106 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
107 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
110 /// ComplexPattern used on MipsInstrInfo
111 /// Used on Mips Load/Store instructions
112 bool MipsDAGToDAGISel::
113 SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
115 // if Address is FI, get the TargetFrameIndex.
116 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
117 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
118 Offset = CurDAG->getTargetConstant(0, MVT::i32);
122 // on PIC code Load GA
123 if (TM.getRelocationModel() == Reloc::PIC_) {
124 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
125 (Addr.getOpcode() == ISD::TargetConstantPool) ||
126 (Addr.getOpcode() == ISD::TargetJumpTable)){
127 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
132 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
133 Addr.getOpcode() == ISD::TargetGlobalAddress))
137 // Operand is a result from an ADD.
138 if (Addr.getOpcode() == ISD::ADD) {
139 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
140 if (Predicate_immSExt16(CN)) {
142 // If the first operand is a FI, get the TargetFI Node
143 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
144 (Addr.getOperand(0))) {
145 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147 Base = Addr.getOperand(0);
150 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
155 // When loading from constant pools, load the lower address part in
156 // the instruction itself. Example, instead of:
157 // lui $2, %hi($CPI1_0)
158 // addiu $2, $2, %lo($CPI1_0)
161 // lui $2, %hi($CPI1_0)
162 // lwc1 $f0, %lo($CPI1_0)($2)
163 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
164 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
165 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
166 SDValue LoVal = Addr.getOperand(1);
167 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
168 Base = Addr.getOperand(0);
169 Offset = LoVal.getOperand(0);
176 Offset = CurDAG->getTargetConstant(0, MVT::i32);
180 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
181 MVT::SimpleValueType NVT =
182 N->getValueType(0).getSimpleVT().SimpleTy;
184 if (!Subtarget.isMips1() || NVT != MVT::f64)
187 if (!Predicate_unindexedload(N) ||
191 SDValue Chain = N->getOperand(0);
192 SDValue N1 = N->getOperand(1);
193 SDValue Offset0, Offset1, Base;
195 if (!SelectAddr(N, N1, Offset0, Base) ||
196 N1.getValueType() != MVT::i32)
199 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
200 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
201 DebugLoc dl = N->getDebugLoc();
203 // The second load should start after for 4 bytes.
204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
205 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
206 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
207 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
211 CP->getTargetFlags());
215 // Choose the offsets depending on the endianess
216 if (TM.getTargetData()->isBigEndian())
217 std::swap(Offset0, Offset1);
224 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
225 MVT::Other, Offset0, Base, Chain);
226 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
228 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
229 MVT::f64, Undef, SDValue(LD0, 0));
231 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
232 MVT::Other, Offset1, Base, SDValue(LD0, 1));
233 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
234 MVT::f64, I0, SDValue(LD1, 0));
236 ReplaceUses(SDValue(N, 0), I1);
237 ReplaceUses(SDValue(N, 1), Chain);
238 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
239 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
243 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
245 if (!Subtarget.isMips1() ||
246 N->getOperand(1).getValueType() != MVT::f64)
249 SDValue Chain = N->getOperand(0);
251 if (!Predicate_unindexedstore(N) ||
255 SDValue N1 = N->getOperand(1);
256 SDValue N2 = N->getOperand(2);
257 SDValue Offset0, Offset1, Base;
259 if (!SelectAddr(N, N2, Offset0, Base) ||
260 N1.getValueType() != MVT::f64 ||
261 N2.getValueType() != MVT::i32)
264 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
265 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
266 DebugLoc dl = N->getDebugLoc();
268 // Get the even and odd part from the f64 register
269 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
271 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
274 // The second store should start after for 4 bytes.
275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
276 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
280 // Choose the offsets depending on the endianess
281 if (TM.getTargetData()->isBigEndian())
282 std::swap(Offset0, Offset1);
289 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
290 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
291 MVT::Other, Ops0, 4), 0);
292 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
294 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
295 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
296 MVT::Other, Ops1, 4), 0);
297 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
299 ReplaceUses(SDValue(N, 0), Chain);
300 return Chain.getNode();
303 /// Select instructions not customized! Used for
304 /// expanded, promoted and normal instructions
305 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
306 unsigned Opcode = Node->getOpcode();
307 DebugLoc dl = Node->getDebugLoc();
309 // Dump information about the Node being selected
310 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
312 // If we have a custom node, we already have selected!
313 if (Node->isMachineOpcode()) {
314 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
319 // Instruction Selection not handled by the auto-generated
320 // tablegen selection should be handled here.
328 SDValue InFlag = Node->getOperand(2), CmpLHS;
329 unsigned Opc = InFlag.getOpcode(); Opc=Opc;
330 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
331 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
332 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
335 if (Opcode == ISD::ADDE) {
336 CmpLHS = InFlag.getValue(0);
339 CmpLHS = InFlag.getOperand(0);
343 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
345 SDValue LHS = Node->getOperand(0);
346 SDValue RHS = Node->getOperand(1);
348 EVT VT = LHS.getValueType();
349 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
350 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
351 SDValue(Carry,0), RHS);
353 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
354 LHS, SDValue(AddCarry,0));
357 /// Mul/Div with two results
361 case ISD::UMUL_LOHI: {
362 SDValue Op1 = Node->getOperand(0);
363 SDValue Op2 = Node->getOperand(1);
366 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
367 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
369 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
371 SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
373 SDValue InFlag = SDValue(MulDiv, 0);
374 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
376 InFlag = SDValue(Lo,1);
377 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
379 if (!SDValue(Node, 0).use_empty())
380 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
382 if (!SDValue(Node, 1).use_empty())
383 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
392 SDValue MulOp1 = Node->getOperand(0);
393 SDValue MulOp2 = Node->getOperand(1);
395 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
396 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
397 MVT::Flag, MulOp1, MulOp2);
399 SDValue InFlag = SDValue(MulNode, 0);
401 if (Opcode == ISD::MUL)
402 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
404 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
407 /// Div/Rem operations
412 SDValue Op1 = Node->getOperand(0);
413 SDValue Op2 = Node->getOperand(1);
416 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
417 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
420 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
423 SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
425 SDValue InFlag = SDValue(Node, 0);
426 return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
429 // Get target GOT address.
430 case ISD::GLOBAL_OFFSET_TABLE:
431 return getGlobalBaseReg();
433 case ISD::ConstantFP: {
434 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
435 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
436 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
437 Mips::ZERO, MVT::i32);
438 SDValue Undef = SDValue(
439 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
440 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
441 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
442 MVT::f64, Undef, SDValue(MTC, 0));
443 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
444 MVT::f64, I0, SDValue(MTC, 0));
445 ReplaceUses(SDValue(Node, 0), I1);
452 if (SDNode *ResNode = SelectLoadFp64(Node))
454 // Other cases are autogenerated.
458 if (SDNode *ResNode = SelectStoreFp64(Node))
460 // Other cases are autogenerated.
463 /// Handle direct and indirect calls when using PIC. On PIC, when
464 /// GOT is smaller than about 64k (small code) the GA target is
465 /// loaded with only one instruction. Otherwise GA's target must
466 /// be loaded with 3 instructions.
467 case MipsISD::JmpLink: {
468 if (TM.getRelocationModel() == Reloc::PIC_) {
469 unsigned LastOpNum = Node->getNumOperands()-1;
471 SDValue Chain = Node->getOperand(0);
472 SDValue Callee = Node->getOperand(1);
475 // Skip the incomming flag if present
476 if (Node->getOperand(LastOpNum).getValueType() == MVT::Flag)
479 if ( (isa<GlobalAddressSDNode>(Callee)) ||
480 (isa<ExternalSymbolSDNode>(Callee)) )
482 /// Direct call for global addresses and external symbols
483 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
485 // Use load to get GOT target
486 SDValue Ops[] = { Callee, GPReg, Chain };
487 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
488 MVT::Other, Ops, 3), 0);
489 Chain = Load.getValue(1);
491 // Call target must be on T9
492 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
495 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
497 // Map the JmpLink operands to JALR
498 SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Flag);
499 SmallVector<SDValue, 8> Ops;
500 Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
502 for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
503 Ops.push_back(Node->getOperand(i));
504 Ops.push_back(Chain);
505 Ops.push_back(Chain.getValue(1));
507 // Emit Jump and Link Register
508 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
509 &Ops[0], Ops.size());
511 // Replace Chain and InFlag
512 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
513 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
519 // Select the default instruction
520 SDNode *ResNode = SelectCode(Node);
522 DEBUG(errs() << "=> ");
523 if (ResNode == NULL || ResNode == Node)
524 DEBUG(Node->dump(CurDAG));
526 DEBUG(ResNode->dump(CurDAG));
527 DEBUG(errs() << "\n");
531 /// createMipsISelDag - This pass converts a legalized DAG into a
532 /// MIPS-specific DAG, ready for instruction scheduling.
533 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
534 return new MipsDAGToDAGISel(TM);