1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MCTargetDesc/MipsBaseInfo.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
69 virtual bool runOnMachineFunction(MachineFunction &MF);
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90 EVT Ty, bool HasLo, bool HasHi);
92 SDNode *Select(SDNode *N);
95 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
97 // getImm - Return a target constant with the specified value.
98 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
102 void ProcessFunctionAfterISel(MachineFunction &MF);
103 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104 void InitGlobalBaseReg(MachineFunction &MF);
106 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
108 std::vector<SDValue> &OutOps);
113 // Insert instructions to initialize the global base register in the
114 // first MBB of the function. When the ABI is O32 and the relocation model is
115 // PIC, the necessary instructions are emitted later to prevent optimization
116 // passes from moving them.
117 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
120 if (!MipsFI->globalBaseRegSet())
123 MachineBasicBlock &MBB = MF.front();
124 MachineBasicBlock::iterator I = MBB.begin();
125 MachineRegisterInfo &RegInfo = MF.getRegInfo();
126 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
127 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
128 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
130 const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
131 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
132 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
134 V0 = RegInfo.createVirtualRegister(RC);
135 V1 = RegInfo.createVirtualRegister(RC);
137 if (Subtarget.isABI_N64()) {
138 MF.getRegInfo().addLiveIn(Mips::T9_64);
139 MBB.addLiveIn(Mips::T9_64);
141 // lui $v0, %hi(%neg(%gp_rel(fname)))
142 // daddu $v1, $v0, $t9
143 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
144 const GlobalValue *FName = MF.getFunction();
145 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
146 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
147 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
148 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
149 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
153 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
154 // Set global register to __gnu_local_gp.
156 // lui $v0, %hi(__gnu_local_gp)
157 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
158 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
159 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
160 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
161 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
165 MF.getRegInfo().addLiveIn(Mips::T9);
166 MBB.addLiveIn(Mips::T9);
168 if (Subtarget.isABI_N32()) {
169 // lui $v0, %hi(%neg(%gp_rel(fname)))
170 // addu $v1, $v0, $t9
171 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
172 const GlobalValue *FName = MF.getFunction();
173 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
174 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
175 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
176 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
177 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
181 assert(Subtarget.isABI_O32());
183 // For O32 ABI, the following instruction sequence is emitted to initialize
184 // the global base register:
186 // 0. lui $2, %hi(_gp_disp)
187 // 1. addiu $2, $2, %lo(_gp_disp)
188 // 2. addu $globalbasereg, $2, $t9
190 // We emit only the last instruction here.
192 // GNU linker requires that the first two instructions appear at the beginning
193 // of a funtion and no instructions be inserted before or between them.
194 // The two instructions are emitted during lowering to MC layer in order to
195 // avoid any reordering.
197 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
198 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
200 MF.getRegInfo().addLiveIn(Mips::V0);
201 MBB.addLiveIn(Mips::V0);
202 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
203 .addReg(Mips::V0).addReg(Mips::T9);
206 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
207 const MachineInstr& MI) {
208 unsigned DstReg = 0, ZeroReg = 0;
210 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
211 if ((MI.getOpcode() == Mips::ADDiu) &&
212 (MI.getOperand(1).getReg() == Mips::ZERO) &&
213 (MI.getOperand(2).getImm() == 0)) {
214 DstReg = MI.getOperand(0).getReg();
215 ZeroReg = Mips::ZERO;
216 } else if ((MI.getOpcode() == Mips::DADDiu) &&
217 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
218 (MI.getOperand(2).getImm() == 0)) {
219 DstReg = MI.getOperand(0).getReg();
220 ZeroReg = Mips::ZERO_64;
226 // Replace uses with ZeroReg.
227 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
228 E = MRI->use_end(); U != E; ++U) {
229 MachineOperand &MO = U.getOperand();
230 MachineInstr *MI = MO.getParent();
232 // Do not replace if it is a phi's operand or is tied to def operand.
233 if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
243 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
244 InitGlobalBaseReg(MF);
246 MachineRegisterInfo *MRI = &MF.getRegInfo();
248 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
250 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
251 ReplaceUsesWithZeroReg(MRI, *I);
254 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
255 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
257 ProcessFunctionAfterISel(MF);
262 /// getGlobalBaseReg - Output the instructions required to put the
263 /// GOT address into a register.
264 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
265 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
266 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
269 /// ComplexPattern used on MipsInstrInfo
270 /// Used on Mips Load/Store instructions
271 bool MipsDAGToDAGISel::
272 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
273 EVT ValTy = Addr.getValueType();
275 // If Parent is an unaligned f32 load or store, select a (base + index)
276 // floating point load/store instruction (luxc1 or suxc1).
277 const LSBaseSDNode* LS = 0;
279 if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
280 EVT VT = LS->getMemoryVT();
282 if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
283 assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
284 "Unaligned loads/stores not supported for this type.");
290 // if Address is FI, get the TargetFrameIndex.
291 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
292 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
293 Offset = CurDAG->getTargetConstant(0, ValTy);
297 // on PIC code Load GA
298 if (Addr.getOpcode() == MipsISD::Wrapper) {
299 Base = Addr.getOperand(0);
300 Offset = Addr.getOperand(1);
304 if (TM.getRelocationModel() != Reloc::PIC_) {
305 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
306 Addr.getOpcode() == ISD::TargetGlobalAddress))
310 // Addresses of the form FI+const or FI|const
311 if (CurDAG->isBaseWithConstantOffset(Addr)) {
312 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
313 if (isInt<16>(CN->getSExtValue())) {
315 // If the first operand is a FI, get the TargetFI Node
316 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
317 (Addr.getOperand(0)))
318 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
320 Base = Addr.getOperand(0);
322 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
327 // Operand is a result from an ADD.
328 if (Addr.getOpcode() == ISD::ADD) {
329 // When loading from constant pools, load the lower address part in
330 // the instruction itself. Example, instead of:
331 // lui $2, %hi($CPI1_0)
332 // addiu $2, $2, %lo($CPI1_0)
335 // lui $2, %hi($CPI1_0)
336 // lwc1 $f0, %lo($CPI1_0)($2)
337 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
338 SDValue LoVal = Addr.getOperand(1);
339 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
340 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
341 Base = Addr.getOperand(0);
342 Offset = LoVal.getOperand(0);
347 // If an indexed floating point load/store can be emitted, return false.
348 if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
349 Subtarget.hasMips32r2Or64())
354 Offset = CurDAG->getTargetConstant(0, ValTy);
358 /// Select multiply instructions.
359 std::pair<SDNode*, SDNode*>
360 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
361 bool HasLo, bool HasHi) {
362 SDNode *Lo = 0, *Hi = 0;
363 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
365 SDValue InFlag = SDValue(Mul, 0);
368 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
369 Ty, MVT::Glue, InFlag);
370 InFlag = SDValue(Lo, 1);
373 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
376 return std::make_pair(Lo, Hi);
380 /// Select instructions not customized! Used for
381 /// expanded, promoted and normal instructions
382 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
383 unsigned Opcode = Node->getOpcode();
384 DebugLoc dl = Node->getDebugLoc();
386 // Dump information about the Node being selected
387 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
389 // If we have a custom node, we already have selected!
390 if (Node->isMachineOpcode()) {
391 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
396 // Instruction Selection not handled by the auto-generated
397 // tablegen selection should be handled here.
399 EVT NodeTy = Node->getValueType(0);
407 SDValue InFlag = Node->getOperand(2), CmpLHS;
408 unsigned Opc = InFlag.getOpcode(); (void)Opc;
409 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
410 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
411 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
414 if (Opcode == ISD::ADDE) {
415 CmpLHS = InFlag.getValue(0);
418 CmpLHS = InFlag.getOperand(0);
422 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
424 SDValue LHS = Node->getOperand(0);
425 SDValue RHS = Node->getOperand(1);
427 EVT VT = LHS.getValueType();
428 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
429 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
430 SDValue(Carry,0), RHS);
432 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
433 LHS, SDValue(AddCarry,0));
436 /// Mul with two results
438 case ISD::UMUL_LOHI: {
439 if (NodeTy == MVT::i32)
440 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
442 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
444 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
447 if (!SDValue(Node, 0).use_empty())
448 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
450 if (!SDValue(Node, 1).use_empty())
451 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
458 // Mips32 has a 32-bit three operand mul instruction.
459 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
461 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
462 dl, NodeTy, true, false).first;
466 if (NodeTy == MVT::i32)
467 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
469 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
471 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
474 // Get target GOT address.
475 case ISD::GLOBAL_OFFSET_TABLE:
476 return getGlobalBaseReg();
478 case ISD::ConstantFP: {
479 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
480 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
481 if (Subtarget.hasMips64()) {
482 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
483 Mips::ZERO_64, MVT::i64);
484 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
487 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
488 Mips::ZERO, MVT::i32);
489 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
495 case ISD::Constant: {
496 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
497 unsigned Size = CN->getValueSizeInBits(0);
502 MipsAnalyzeImmediate AnalyzeImm;
503 int64_t Imm = CN->getSExtValue();
505 const MipsAnalyzeImmediate::InstSeq &Seq =
506 AnalyzeImm.Analyze(Imm, Size, false);
508 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
509 DebugLoc DL = CN->getDebugLoc();
511 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
514 // The first instruction can be a LUi which is different from other
515 // instructions (ADDiu, ORI and SLL) in that it does not have a register
517 if (Inst->Opc == Mips::LUi64)
518 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
521 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
522 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
525 // The remaining instructions in the sequence are handled here.
526 for (++Inst; Inst != Seq.end(); ++Inst) {
527 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
529 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
530 SDValue(RegOpnd, 0), ImmOpnd);
536 case MipsISD::ThreadPointer: {
537 EVT PtrVT = TLI.getPointerTy();
538 unsigned RdhwrOpc, SrcReg, DestReg;
540 if (PtrVT == MVT::i32) {
541 RdhwrOpc = Mips::RDHWR;
542 SrcReg = Mips::HWR29;
545 RdhwrOpc = Mips::RDHWR64;
546 SrcReg = Mips::HWR29_64;
547 DestReg = Mips::V1_64;
551 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
552 Node->getValueType(0),
553 CurDAG->getRegister(SrcReg, PtrVT));
554 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
556 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
557 ReplaceUses(SDValue(Node, 0), ResNode);
558 return ResNode.getNode();
562 // Select the default instruction
563 SDNode *ResNode = SelectCode(Node);
565 DEBUG(errs() << "=> ");
566 if (ResNode == NULL || ResNode == Node)
567 DEBUG(Node->dump(CurDAG));
569 DEBUG(ResNode->dump(CurDAG));
570 DEBUG(errs() << "\n");
574 bool MipsDAGToDAGISel::
575 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
576 std::vector<SDValue> &OutOps) {
577 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
578 OutOps.push_back(Op);
582 /// createMipsISelDag - This pass converts a legalized DAG into a
583 /// MIPS-specific DAG, ready for instruction scheduling.
584 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
585 return new MipsDAGToDAGISel(TM);