1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MCTargetDesc/MipsBaseInfo.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
69 virtual bool runOnMachineFunction(MachineFunction &MF);
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
89 SDValue getMips16SPAliasReg();
91 void getMips16SPRefReg(SDNode *parent, SDValue &AliasReg);
93 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
94 EVT Ty, bool HasLo, bool HasHi);
96 SDNode *Select(SDNode *N);
99 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
101 bool SelectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset,
104 // getImm - Return a target constant with the specified value.
105 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
106 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
109 void ProcessFunctionAfterISel(MachineFunction &MF);
110 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
111 void InitGlobalBaseReg(MachineFunction &MF);
112 void InitMips16SPAliasReg(MachineFunction &MF);
114 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
116 std::vector<SDValue> &OutOps);
121 // Insert instructions to initialize the global base register in the
122 // first MBB of the function. When the ABI is O32 and the relocation model is
123 // PIC, the necessary instructions are emitted later to prevent optimization
124 // passes from moving them.
125 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
126 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
128 if (!MipsFI->globalBaseRegSet())
131 MachineBasicBlock &MBB = MF.front();
132 MachineBasicBlock::iterator I = MBB.begin();
133 MachineRegisterInfo &RegInfo = MF.getRegInfo();
134 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
135 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
136 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
137 const TargetRegisterClass *RC;
139 if (Subtarget.isABI_N64())
140 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
141 else if (Subtarget.inMips16Mode())
142 RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
144 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
146 V0 = RegInfo.createVirtualRegister(RC);
147 V1 = RegInfo.createVirtualRegister(RC);
148 V2 = RegInfo.createVirtualRegister(RC);
150 if (Subtarget.isABI_N64()) {
151 MF.getRegInfo().addLiveIn(Mips::T9_64);
152 MBB.addLiveIn(Mips::T9_64);
154 // lui $v0, %hi(%neg(%gp_rel(fname)))
155 // daddu $v1, $v0, $t9
156 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
157 const GlobalValue *FName = MF.getFunction();
158 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
159 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
160 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
161 .addReg(Mips::T9_64);
162 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
163 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
167 if (Subtarget.inMips16Mode()) {
168 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
169 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
170 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
171 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
172 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
173 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
174 .addReg(V1).addReg(V2);
178 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
179 // Set global register to __gnu_local_gp.
181 // lui $v0, %hi(__gnu_local_gp)
182 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
183 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
185 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
186 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
190 MF.getRegInfo().addLiveIn(Mips::T9);
191 MBB.addLiveIn(Mips::T9);
193 if (Subtarget.isABI_N32()) {
194 // lui $v0, %hi(%neg(%gp_rel(fname)))
195 // addu $v1, $v0, $t9
196 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
197 const GlobalValue *FName = MF.getFunction();
198 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
199 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
200 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
201 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
202 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
206 assert(Subtarget.isABI_O32());
208 // For O32 ABI, the following instruction sequence is emitted to initialize
209 // the global base register:
211 // 0. lui $2, %hi(_gp_disp)
212 // 1. addiu $2, $2, %lo(_gp_disp)
213 // 2. addu $globalbasereg, $2, $t9
215 // We emit only the last instruction here.
217 // GNU linker requires that the first two instructions appear at the beginning
218 // of a function and no instructions be inserted before or between them.
219 // The two instructions are emitted during lowering to MC layer in order to
220 // avoid any reordering.
222 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
223 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
225 MF.getRegInfo().addLiveIn(Mips::V0);
226 MBB.addLiveIn(Mips::V0);
227 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
228 .addReg(Mips::V0).addReg(Mips::T9);
231 // Insert instructions to initialize the Mips16 SP Alias register in the
232 // first MBB of the function.
234 void MipsDAGToDAGISel::InitMips16SPAliasReg(MachineFunction &MF) {
235 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
237 if (!MipsFI->mips16SPAliasRegSet())
240 MachineBasicBlock &MBB = MF.front();
241 MachineBasicBlock::iterator I = MBB.begin();
242 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
243 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
244 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
246 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
251 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
252 const MachineInstr& MI) {
253 unsigned DstReg = 0, ZeroReg = 0;
255 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
256 if ((MI.getOpcode() == Mips::ADDiu) &&
257 (MI.getOperand(1).getReg() == Mips::ZERO) &&
258 (MI.getOperand(2).getImm() == 0)) {
259 DstReg = MI.getOperand(0).getReg();
260 ZeroReg = Mips::ZERO;
261 } else if ((MI.getOpcode() == Mips::DADDiu) &&
262 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
263 (MI.getOperand(2).getImm() == 0)) {
264 DstReg = MI.getOperand(0).getReg();
265 ZeroReg = Mips::ZERO_64;
271 // Replace uses with ZeroReg.
272 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
273 E = MRI->use_end(); U != E;) {
274 MachineOperand &MO = U.getOperand();
275 unsigned OpNo = U.getOperandNo();
276 MachineInstr *MI = MO.getParent();
279 // Do not replace if it is a phi's operand or is tied to def operand.
280 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
289 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
290 InitGlobalBaseReg(MF);
291 InitMips16SPAliasReg(MF);
293 MachineRegisterInfo *MRI = &MF.getRegInfo();
295 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
297 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
298 ReplaceUsesWithZeroReg(MRI, *I);
301 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
302 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
304 ProcessFunctionAfterISel(MF);
309 /// getGlobalBaseReg - Output the instructions required to put the
310 /// GOT address into a register.
311 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
312 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
313 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
316 /// getMips16SPAliasReg - Output the instructions required to put the
317 /// SP into a Mips16 accessible aliased register.
318 SDValue MipsDAGToDAGISel::getMips16SPAliasReg() {
319 unsigned Mips16SPAliasReg =
320 MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
321 return CurDAG->getRegister(Mips16SPAliasReg, TLI.getPointerTy());
324 /// ComplexPattern used on MipsInstrInfo
325 /// Used on Mips Load/Store instructions
326 bool MipsDAGToDAGISel::
327 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
328 EVT ValTy = Addr.getValueType();
330 // if Address is FI, get the TargetFrameIndex.
331 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
332 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
333 Offset = CurDAG->getTargetConstant(0, ValTy);
337 // on PIC code Load GA
338 if (Addr.getOpcode() == MipsISD::Wrapper) {
339 Base = Addr.getOperand(0);
340 Offset = Addr.getOperand(1);
344 if (TM.getRelocationModel() != Reloc::PIC_) {
345 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
346 Addr.getOpcode() == ISD::TargetGlobalAddress))
350 // Addresses of the form FI+const or FI|const
351 if (CurDAG->isBaseWithConstantOffset(Addr)) {
352 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
353 if (isInt<16>(CN->getSExtValue())) {
355 // If the first operand is a FI, get the TargetFI Node
356 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
357 (Addr.getOperand(0)))
358 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
360 Base = Addr.getOperand(0);
362 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
367 // Operand is a result from an ADD.
368 if (Addr.getOpcode() == ISD::ADD) {
369 // When loading from constant pools, load the lower address part in
370 // the instruction itself. Example, instead of:
371 // lui $2, %hi($CPI1_0)
372 // addiu $2, $2, %lo($CPI1_0)
375 // lui $2, %hi($CPI1_0)
376 // lwc1 $f0, %lo($CPI1_0)($2)
377 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
378 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
379 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
380 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
381 isa<JumpTableSDNode>(Opnd0)) {
382 Base = Addr.getOperand(0);
388 // If an indexed floating point load/store can be emitted, return false.
389 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
392 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
393 Subtarget.hasFPIdx())
398 Offset = CurDAG->getTargetConstant(0, ValTy);
402 void MipsDAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
403 SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy());
405 switch (Parent->getOpcode()) {
407 LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
408 switch (SD->getMemoryVT().getSizeInBits()) {
411 AliasReg = TM.getFrameLowering()->hasFP(*MF)?
412 AliasFPReg: getMips16SPAliasReg();
418 StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
419 switch (SD->getMemoryVT().getSizeInBits()) {
422 AliasReg = TM.getFrameLowering()->hasFP(*MF)?
423 AliasFPReg: getMips16SPAliasReg();
430 AliasReg = CurDAG->getRegister(Mips::SP, TLI.getPointerTy());
434 bool MipsDAGToDAGISel::SelectAddr16(
435 SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
437 EVT ValTy = Addr.getValueType();
439 Alias = CurDAG->getTargetConstant(0, ValTy);
441 // if Address is FI, get the TargetFrameIndex.
442 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
443 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
444 Offset = CurDAG->getTargetConstant(0, ValTy);
445 getMips16SPRefReg(Parent, Alias);
448 // on PIC code Load GA
449 if (Addr.getOpcode() == MipsISD::Wrapper) {
450 Base = Addr.getOperand(0);
451 Offset = Addr.getOperand(1);
454 if (TM.getRelocationModel() != Reloc::PIC_) {
455 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
456 Addr.getOpcode() == ISD::TargetGlobalAddress))
459 // Addresses of the form FI+const or FI|const
460 if (CurDAG->isBaseWithConstantOffset(Addr)) {
461 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
462 if (isInt<16>(CN->getSExtValue())) {
464 // If the first operand is a FI, get the TargetFI Node
465 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
466 (Addr.getOperand(0))) {
467 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
468 getMips16SPRefReg(Parent, Alias);
471 Base = Addr.getOperand(0);
473 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
477 // Operand is a result from an ADD.
478 if (Addr.getOpcode() == ISD::ADD) {
479 // When loading from constant pools, load the lower address part in
480 // the instruction itself. Example, instead of:
481 // lui $2, %hi($CPI1_0)
482 // addiu $2, $2, %lo($CPI1_0)
485 // lui $2, %hi($CPI1_0)
486 // lwc1 $f0, %lo($CPI1_0)($2)
487 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
488 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
489 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
490 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
491 isa<JumpTableSDNode>(Opnd0)) {
492 Base = Addr.getOperand(0);
498 // If an indexed floating point load/store can be emitted, return false.
499 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
502 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
503 Subtarget.hasFPIdx())
507 Offset = CurDAG->getTargetConstant(0, ValTy);
511 /// Select multiply instructions.
512 std::pair<SDNode*, SDNode*>
513 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
514 bool HasLo, bool HasHi) {
515 SDNode *Lo = 0, *Hi = 0;
516 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
518 SDValue InFlag = SDValue(Mul, 0);
521 unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mflo16 :
522 (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
523 Lo = CurDAG->getMachineNode(Opcode, dl, Ty, MVT::Glue, InFlag);
524 InFlag = SDValue(Lo, 1);
527 unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mfhi16 :
528 (Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
529 Hi = CurDAG->getMachineNode(Opcode, dl, Ty, InFlag);
531 return std::make_pair(Lo, Hi);
535 /// Select instructions not customized! Used for
536 /// expanded, promoted and normal instructions
537 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
538 unsigned Opcode = Node->getOpcode();
539 DebugLoc dl = Node->getDebugLoc();
541 // Dump information about the Node being selected
542 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
544 // If we have a custom node, we already have selected!
545 if (Node->isMachineOpcode()) {
546 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
551 // Instruction Selection not handled by the auto-generated
552 // tablegen selection should be handled here.
554 EVT NodeTy = Node->getValueType(0);
562 bool inMips16Mode = Subtarget.inMips16Mode();
563 SDValue InFlag = Node->getOperand(2), CmpLHS;
564 unsigned Opc = InFlag.getOpcode(); (void)Opc;
565 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
566 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
567 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
570 if (Opcode == ISD::ADDE) {
571 CmpLHS = InFlag.getValue(0);
573 MOp = Mips::AdduRxRyRz16;
577 CmpLHS = InFlag.getOperand(0);
579 MOp = Mips::SubuRxRyRz16;
584 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
586 SDValue LHS = Node->getOperand(0);
587 SDValue RHS = Node->getOperand(1);
589 EVT VT = LHS.getValueType();
591 unsigned Sltu_op = inMips16Mode? Mips::SltuRxRyRz16: Mips::SLTu;
592 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, dl, VT, Ops, 2);
593 unsigned Addu_op = inMips16Mode? Mips::AdduRxRyRz16 : Mips::ADDu;
594 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, dl, VT,
595 SDValue(Carry,0), RHS);
597 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
598 LHS, SDValue(AddCarry,0));
601 /// Mul with two results
603 case ISD::UMUL_LOHI: {
604 if (NodeTy == MVT::i32) {
605 if (Subtarget.inMips16Mode())
606 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 :
609 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
612 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
614 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
617 if (!SDValue(Node, 0).use_empty())
618 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
620 if (!SDValue(Node, 1).use_empty())
621 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
628 // Mips32 has a 32-bit three operand mul instruction.
629 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
631 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
632 dl, NodeTy, true, false).first;
636 if (NodeTy == MVT::i32) {
637 if (Subtarget.inMips16Mode())
638 MultOpc = (Opcode == ISD::MULHU ?
639 Mips::MultuRxRy16 : Mips::MultRxRy16);
641 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
644 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
646 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
649 // Get target GOT address.
650 case ISD::GLOBAL_OFFSET_TABLE:
651 return getGlobalBaseReg();
653 case ISD::ConstantFP: {
654 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
655 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
656 if (Subtarget.hasMips64()) {
657 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
658 Mips::ZERO_64, MVT::i64);
659 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
662 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
663 Mips::ZERO, MVT::i32);
664 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
670 case ISD::Constant: {
671 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
672 unsigned Size = CN->getValueSizeInBits(0);
677 MipsAnalyzeImmediate AnalyzeImm;
678 int64_t Imm = CN->getSExtValue();
680 const MipsAnalyzeImmediate::InstSeq &Seq =
681 AnalyzeImm.Analyze(Imm, Size, false);
683 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
684 DebugLoc DL = CN->getDebugLoc();
686 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
689 // The first instruction can be a LUi which is different from other
690 // instructions (ADDiu, ORI and SLL) in that it does not have a register
692 if (Inst->Opc == Mips::LUi64)
693 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
696 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
697 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
700 // The remaining instructions in the sequence are handled here.
701 for (++Inst; Inst != Seq.end(); ++Inst) {
702 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
704 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
705 SDValue(RegOpnd, 0), ImmOpnd);
714 assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
715 cast<MemSDNode>(Node)->getAlignment() &&
716 "Unexpected unaligned loads/stores.");
720 case MipsISD::ThreadPointer: {
721 EVT PtrVT = TLI.getPointerTy();
722 unsigned RdhwrOpc, SrcReg, DestReg;
724 if (PtrVT == MVT::i32) {
725 RdhwrOpc = Mips::RDHWR;
726 SrcReg = Mips::HWR29;
729 RdhwrOpc = Mips::RDHWR64;
730 SrcReg = Mips::HWR29_64;
731 DestReg = Mips::V1_64;
735 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
736 Node->getValueType(0),
737 CurDAG->getRegister(SrcReg, PtrVT));
738 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
740 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
741 ReplaceUses(SDValue(Node, 0), ResNode);
742 return ResNode.getNode();
746 // Select the default instruction
747 SDNode *ResNode = SelectCode(Node);
749 DEBUG(errs() << "=> ");
750 if (ResNode == NULL || ResNode == Node)
751 DEBUG(Node->dump(CurDAG));
753 DEBUG(ResNode->dump(CurDAG));
754 DEBUG(errs() << "\n");
758 bool MipsDAGToDAGISel::
759 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
760 std::vector<SDValue> &OutOps) {
761 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
762 OutOps.push_back(Op);
766 /// createMipsISelDag - This pass converts a legalized DAG into a
767 /// MIPS-specific DAG, ready for instruction scheduling.
768 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
769 return new MipsDAGToDAGISel(TM);