1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// MipsLowering - This object fully describes how to lower LLVM code to an
56 /// Mips-specific SelectionDAG.
57 MipsTargetLowering MipsLowering;
59 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
60 /// make the right decision when generating code for different targets.
61 //TODO: add initialization on constructor
62 //const MipsSubtarget *Subtarget;
65 MipsDAGToDAGISel(MipsTargetMachine &tm) :
66 SelectionDAGISel(MipsLowering),
67 TM(tm), MipsLowering(*TM.getTargetLowering()) {}
69 virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
72 virtual const char *getPassName() const {
73 return "MIPS DAG->DAG Pattern Instruction Selection";
78 // Include the pieces autogenerated from the target description.
79 #include "MipsGenDAGISel.inc"
81 SDOperand getGlobalBaseReg();
82 SDNode *Select(SDOperand N);
85 bool SelectAddr(SDOperand Op, SDOperand N,
86 SDOperand &Base, SDOperand &Offset);
89 // getI32Imm - Return a target constant with the specified
90 // value, of type i32.
91 inline SDOperand getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
103 /// InstructionSelectBasicBlock - This callback is invoked by
104 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
105 void MipsDAGToDAGISel::
106 InstructionSelectBasicBlock(SelectionDAG &SD)
109 // Codegen the basic block.
111 DOUT << "===== Instruction selection begins:\n";
115 // Select target instructions for the DAG.
116 SD.setRoot(SelectRoot(SD.getRoot()));
119 DOUT << "===== Instruction selection ends:\n";
122 SD.RemoveDeadNodes();
124 // Emit machine code to BB.
125 ScheduleAndEmitDAG(SD);
128 /// getGlobalBaseReg - Output the instructions required to put the
129 /// GOT address into a register.
130 SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
131 MachineFunction* MF = BB->getParent();
133 for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
134 ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
135 if (ii->first == Mips::GP) {
139 assert(GP && "GOT PTR not in liveins");
140 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
144 /// ComplexPattern used on MipsInstrInfo
145 /// Used on Mips Load/Store instructions
146 bool MipsDAGToDAGISel::
147 SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
149 // if Address is FI, get the TargetFrameIndex.
150 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
151 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
152 Offset = CurDAG->getTargetConstant(0, MVT::i32);
156 // on PIC code Load GA
157 if (TM.getRelocationModel() == Reloc::PIC_) {
158 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
159 (Addr.getOpcode() == ISD::TargetJumpTable)){
160 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
165 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
166 Addr.getOpcode() == ISD::TargetGlobalAddress))
170 // Operand is a result from an ADD.
171 if (Addr.getOpcode() == ISD::ADD) {
172 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
173 if (Predicate_immSExt16(CN)) {
175 // If the first operand is a FI, get the TargetFI Node
176 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
177 (Addr.getOperand(0))) {
178 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
180 Base = Addr.getOperand(0);
183 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
190 Offset = CurDAG->getTargetConstant(0, MVT::i32);
194 /// Select instructions not customized! Used for
195 /// expanded, promoted and normal instructions
196 SDNode* MipsDAGToDAGISel::
199 SDNode *Node = N.Val;
200 unsigned Opcode = Node->getOpcode();
202 // Dump information about the Node being selected
204 DOUT << std::string(Indent, ' ') << "Selecting: ";
205 DEBUG(Node->dump(CurDAG));
210 // If we have a custom node, we already have selected!
211 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < MipsISD::FIRST_NUMBER) {
213 DOUT << std::string(Indent-2, ' ') << "== ";
214 DEBUG(Node->dump(CurDAG));
222 // Instruction Selection not handled by the auto-generated
223 // tablegen selection should be handled here.
229 /// Special Mul operations
232 SDOperand MulOp1 = Node->getOperand(0);
233 SDOperand MulOp2 = Node->getOperand(1);
234 AddToISelQueue(MulOp1);
235 AddToISelQueue(MulOp2);
237 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
238 SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
240 SDOperand MFInFlag = SDOperand(MulNode, 0);
241 return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
247 SDOperand DivOp1 = Node->getOperand(0);
248 SDOperand DivOp2 = Node->getOperand(1);
249 AddToISelQueue(DivOp1);
250 AddToISelQueue(DivOp2);
252 unsigned DivOp = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
253 SDNode *DivNode = CurDAG->getTargetNode(DivOp, MVT::Flag, DivOp1, DivOp2);
255 SDOperand MFInFlag = SDOperand(DivNode, 0);
256 return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MFInFlag);
262 SDOperand RemOp1 = Node->getOperand(0);
263 SDOperand RemOp2 = Node->getOperand(1);
264 AddToISelQueue(RemOp1);
265 AddToISelQueue(RemOp2);
267 unsigned RemOp = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
268 SDNode *RemNode = CurDAG->getTargetNode(RemOp, MVT::Flag, RemOp1, RemOp2);
270 SDOperand MFInFlag = SDOperand(RemNode, 0);
271 return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
274 // Get target GOT address.
275 case ISD::GLOBAL_OFFSET_TABLE: {
276 SDOperand Result = getGlobalBaseReg();
277 ReplaceUses(N, Result);
281 /// Handle direct and indirect calls when using PIC. On PIC, when
282 /// GOT is smaller than about 64k (small code) the GA target is
283 /// loaded with only one instruction. Otherwise GA's target must
284 /// be loaded with 3 instructions.
285 case MipsISD::JmpLink: {
286 if (TM.getRelocationModel() == Reloc::PIC_) {
287 //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
288 SDOperand Chain = Node->getOperand(0);
289 SDOperand Callee = Node->getOperand(1);
290 AddToISelQueue(Chain);
291 SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
292 SDOperand InFlag(0, 0);
294 if ( (isa<GlobalAddressSDNode>(Callee)) ||
295 (isa<ExternalSymbolSDNode>(Callee)) )
297 /// Direct call for global addresses and external symbols
298 SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
300 // Use load to get GOT target
301 SDOperand Ops[] = { Callee, GPReg, Chain };
302 SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
303 MVT::Other, Ops, 3), 0);
304 Chain = Load.getValue(1);
305 AddToISelQueue(Chain);
307 // Call target must be on T9
308 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
311 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
313 AddToISelQueue(Chain);
315 // Emit Jump and Link Register
316 SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
317 MVT::Flag, T9Reg, Chain);
318 Chain = SDOperand(ResNode, 0);
319 InFlag = SDOperand(ResNode, 1);
320 ReplaceUses(SDOperand(Node, 0), Chain);
321 ReplaceUses(SDOperand(Node, 1), InFlag);
327 // Select the default instruction
328 SDNode *ResNode = SelectCode(N);
331 DOUT << std::string(Indent-2, ' ') << "=> ";
332 if (ResNode == NULL || ResNode == N.Val)
333 DEBUG(N.Val->dump(CurDAG));
335 DEBUG(ResNode->dump(CurDAG));
343 /// createMipsISelDag - This pass converts a legalized DAG into a
344 /// MIPS-specific DAG, ready for instruction scheduling.
345 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
346 return new MipsDAGToDAGISel(TM);