1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 //===----------------------------------------------------------------------===//
39 // Instruction Selector Implementation
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
43 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
44 // instructions for SelectionDAG operations.
45 //===----------------------------------------------------------------------===//
48 class MipsDAGToDAGISel : public SelectionDAGISel {
50 /// TM - Keep a reference to MipsTargetMachine.
51 MipsTargetMachine &TM;
53 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
54 /// make the right decision when generating code for different targets.
55 const MipsSubtarget &Subtarget;
58 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
60 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63 virtual const char *getPassName() const {
64 return "MIPS DAG->DAG Pattern Instruction Selection";
69 // Include the pieces autogenerated from the target description.
70 #include "MipsGenDAGISel.inc"
72 /// getTargetMachine - Return a reference to the TargetMachine, casted
73 /// to the target-specific type.
74 const MipsTargetMachine &getTargetMachine() {
75 return static_cast<const MipsTargetMachine &>(TM);
78 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
79 /// to the target-specific type.
80 const MipsInstrInfo *getInstrInfo() {
81 return getTargetMachine().getInstrInfo();
84 SDNode *getGlobalBaseReg();
86 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
87 EVT Ty, bool HasLo, bool HasHi);
89 SDNode *Select(SDNode *N);
92 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
94 // getImm - Return a target constant with the specified value.
95 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
96 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
99 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
101 std::vector<SDValue> &OutOps);
107 /// getGlobalBaseReg - Output the instructions required to put the
108 /// GOT address into a register.
109 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
110 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
111 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
114 /// ComplexPattern used on MipsInstrInfo
115 /// Used on Mips Load/Store instructions
116 bool MipsDAGToDAGISel::
117 SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
118 EVT ValTy = Addr.getValueType();
119 unsigned GPReg = ValTy == MVT::i32 ? Mips::GP : Mips::GP_64;
121 // if Address is FI, get the TargetFrameIndex.
122 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
123 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
124 Offset = CurDAG->getTargetConstant(0, ValTy);
128 // on PIC code Load GA
129 if (Addr.getOpcode() == MipsISD::Wrapper) {
130 Base = CurDAG->getRegister(GPReg, ValTy);
131 Offset = Addr.getOperand(0);
135 if (TM.getRelocationModel() != Reloc::PIC_) {
136 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
137 Addr.getOpcode() == ISD::TargetGlobalAddress))
141 // Addresses of the form FI+const or FI|const
142 if (CurDAG->isBaseWithConstantOffset(Addr)) {
143 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
144 if (isInt<16>(CN->getSExtValue())) {
146 // If the first operand is a FI, get the TargetFI Node
147 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
148 (Addr.getOperand(0)))
149 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
151 Base = Addr.getOperand(0);
153 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
158 // Operand is a result from an ADD.
159 if (Addr.getOpcode() == ISD::ADD) {
160 // When loading from constant pools, load the lower address part in
161 // the instruction itself. Example, instead of:
162 // lui $2, %hi($CPI1_0)
163 // addiu $2, $2, %lo($CPI1_0)
166 // lui $2, %hi($CPI1_0)
167 // lwc1 $f0, %lo($CPI1_0)($2)
168 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
169 SDValue LoVal = Addr.getOperand(1);
170 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
171 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
172 Base = Addr.getOperand(0);
173 Offset = LoVal.getOperand(0);
180 Offset = CurDAG->getTargetConstant(0, ValTy);
184 /// Select multiply instructions.
185 std::pair<SDNode*, SDNode*>
186 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
187 bool HasLo, bool HasHi) {
188 SDNode *Lo = 0, *Hi = 0;
189 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
191 SDValue InFlag = SDValue(Mul, 0);
194 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
195 Ty, MVT::Glue, InFlag);
196 InFlag = SDValue(Lo, 1);
199 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
202 return std::make_pair(Lo, Hi);
206 /// Select instructions not customized! Used for
207 /// expanded, promoted and normal instructions
208 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
209 unsigned Opcode = Node->getOpcode();
210 DebugLoc dl = Node->getDebugLoc();
212 // Dump information about the Node being selected
213 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
215 // If we have a custom node, we already have selected!
216 if (Node->isMachineOpcode()) {
217 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
222 // Instruction Selection not handled by the auto-generated
223 // tablegen selection should be handled here.
225 EVT NodeTy = Node->getValueType(0);
233 SDValue InFlag = Node->getOperand(2), CmpLHS;
234 unsigned Opc = InFlag.getOpcode(); (void)Opc;
235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
240 if (Opcode == ISD::ADDE) {
241 CmpLHS = InFlag.getValue(0);
244 CmpLHS = InFlag.getOperand(0);
248 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
250 SDValue LHS = Node->getOperand(0);
251 SDValue RHS = Node->getOperand(1);
253 EVT VT = LHS.getValueType();
254 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
255 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
256 SDValue(Carry,0), RHS);
258 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
259 LHS, SDValue(AddCarry,0));
262 /// Mul with two results
264 case ISD::UMUL_LOHI: {
265 if (NodeTy == MVT::i32)
266 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
268 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
270 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
273 if (!SDValue(Node, 0).use_empty())
274 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
276 if (!SDValue(Node, 1).use_empty())
277 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
284 // Mips32 has a 32-bit three operand mul instruction.
285 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
287 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
288 dl, NodeTy, true, false).first;
292 if (NodeTy == MVT::i32)
293 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
295 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
297 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
300 // Get target GOT address.
301 case ISD::GLOBAL_OFFSET_TABLE:
302 return getGlobalBaseReg();
304 case ISD::ConstantFP: {
305 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
306 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
307 if (Subtarget.hasMips64()) {
308 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
309 Mips::ZERO_64, MVT::i64);
310 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
313 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
314 Mips::ZERO, MVT::i32);
315 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
321 case ISD::Constant: {
322 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
323 unsigned Size = CN->getValueSizeInBits(0);
328 MipsAnalyzeImmediate AnalyzeImm;
329 int64_t Imm = CN->getSExtValue();
331 const MipsAnalyzeImmediate::InstSeq &Seq =
332 AnalyzeImm.Analyze(Imm, Size, false);
334 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
335 DebugLoc DL = CN->getDebugLoc();
337 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
340 // The first instruction can be a LUi which is different from other
341 // instructions (ADDiu, ORI and SLL) in that it does not have a register
343 if (Inst->Opc == Mips::LUi64)
344 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
347 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
348 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
351 // The remaining instructions in the sequence are handled here.
352 for (++Inst; Inst != Seq.end(); ++Inst) {
353 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
355 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
356 SDValue(RegOpnd, 0), ImmOpnd);
362 case MipsISD::ThreadPointer: {
363 EVT PtrVT = TLI.getPointerTy();
364 unsigned RdhwrOpc, SrcReg, DestReg;
366 if (PtrVT == MVT::i32) {
367 RdhwrOpc = Mips::RDHWR;
368 SrcReg = Mips::HWR29;
371 RdhwrOpc = Mips::RDHWR64;
372 SrcReg = Mips::HWR29_64;
373 DestReg = Mips::V1_64;
377 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
378 Node->getValueType(0),
379 CurDAG->getRegister(SrcReg, PtrVT));
380 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
382 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
383 ReplaceUses(SDValue(Node, 0), ResNode);
384 return ResNode.getNode();
388 // Select the default instruction
389 SDNode *ResNode = SelectCode(Node);
391 DEBUG(errs() << "=> ");
392 if (ResNode == NULL || ResNode == Node)
393 DEBUG(Node->dump(CurDAG));
395 DEBUG(ResNode->dump(CurDAG));
396 DEBUG(errs() << "\n");
400 bool MipsDAGToDAGISel::
401 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
402 std::vector<SDValue> &OutOps) {
403 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
404 OutOps.push_back(Op);
408 /// createMipsISelDag - This pass converts a legalized DAG into a
409 /// MIPS-specific DAG, ready for instruction scheduling.
410 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
411 return new MipsDAGToDAGISel(TM);