1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 SDNode *SelectLoadFp64(SDNode *N);
90 SDNode *SelectStoreFp64(SDNode *N);
92 // getI32Imm - Return a target constant with the specified
93 // value, of type i32.
94 inline SDValue getI32Imm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113 // if Address is FI, get the TargetFrameIndex.
114 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
120 // on PIC code Load GA
121 if (TM.getRelocationModel() == Reloc::PIC_) {
122 if (Addr.getOpcode() == MipsISD::WrapperPIC) {
123 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
124 Offset = Addr.getOperand(0);
128 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
129 Addr.getOpcode() == ISD::TargetGlobalAddress))
131 else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
132 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
138 // Addresses of the form FI+const or FI|const
139 if (CurDAG->isBaseWithConstantOffset(Addr)) {
140 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
141 if (isInt<16>(CN->getSExtValue())) {
143 // If the first operand is a FI, get the TargetFI Node
144 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
145 (Addr.getOperand(0)))
146 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
148 Base = Addr.getOperand(0);
150 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
155 // Operand is a result from an ADD.
156 if (Addr.getOpcode() == ISD::ADD) {
157 // When loading from constant pools, load the lower address part in
158 // the instruction itself. Example, instead of:
159 // lui $2, %hi($CPI1_0)
160 // addiu $2, $2, %lo($CPI1_0)
163 // lui $2, %hi($CPI1_0)
164 // lwc1 $f0, %lo($CPI1_0)($2)
165 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
166 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
167 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
168 SDValue LoVal = Addr.getOperand(1);
169 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
170 Base = Addr.getOperand(0);
171 Offset = LoVal.getOperand(0);
178 Offset = CurDAG->getTargetConstant(0, MVT::i32);
182 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
183 MVT::SimpleValueType NVT =
184 N->getValueType(0).getSimpleVT().SimpleTy;
186 if (!Subtarget.isMips1() || NVT != MVT::f64)
189 LoadSDNode *LN = cast<LoadSDNode>(N);
190 if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
191 LN->getAddressingMode() != ISD::UNINDEXED)
194 SDValue Chain = N->getOperand(0);
195 SDValue N1 = N->getOperand(1);
196 SDValue Offset0, Offset1, Base;
198 if (!SelectAddr(N1, Offset0, Base) ||
199 N1.getValueType() != MVT::i32)
202 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
203 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
204 DebugLoc dl = N->getDebugLoc();
206 // The second load should start after for 4 bytes.
207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
208 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
209 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
210 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
214 CP->getTargetFlags());
218 // Choose the offsets depending on the endianess
219 if (TM.getTargetData()->isBigEndian())
220 std::swap(Offset0, Offset1);
227 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
228 MVT::Other, Offset0, Base, Chain);
229 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
231 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
232 MVT::f64, Undef, SDValue(LD0, 0));
234 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
235 MVT::Other, Offset1, Base, SDValue(LD0, 1));
236 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
237 MVT::f64, I0, SDValue(LD1, 0));
239 ReplaceUses(SDValue(N, 0), I1);
240 ReplaceUses(SDValue(N, 1), Chain);
241 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
242 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
246 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
248 if (!Subtarget.isMips1() ||
249 N->getOperand(1).getValueType() != MVT::f64)
252 SDValue Chain = N->getOperand(0);
254 StoreSDNode *SN = cast<StoreSDNode>(N);
255 if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
258 SDValue N1 = N->getOperand(1);
259 SDValue N2 = N->getOperand(2);
260 SDValue Offset0, Offset1, Base;
262 if (!SelectAddr(N2, Offset0, Base) ||
263 N1.getValueType() != MVT::f64 ||
264 N2.getValueType() != MVT::i32)
267 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
268 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
269 DebugLoc dl = N->getDebugLoc();
271 // Get the even and odd part from the f64 register
272 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
274 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
277 // The second store should start after for 4 bytes.
278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
279 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
283 // Choose the offsets depending on the endianess
284 if (TM.getTargetData()->isBigEndian())
285 std::swap(Offset0, Offset1);
292 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
293 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
294 MVT::Other, Ops0, 4), 0);
295 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
297 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
298 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
299 MVT::Other, Ops1, 4), 0);
300 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
302 ReplaceUses(SDValue(N, 0), Chain);
303 return Chain.getNode();
306 /// Select instructions not customized! Used for
307 /// expanded, promoted and normal instructions
308 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
309 unsigned Opcode = Node->getOpcode();
310 DebugLoc dl = Node->getDebugLoc();
312 // Dump information about the Node being selected
313 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
315 // If we have a custom node, we already have selected!
316 if (Node->isMachineOpcode()) {
317 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
322 // Instruction Selection not handled by the auto-generated
323 // tablegen selection should be handled here.
331 SDValue InFlag = Node->getOperand(2), CmpLHS;
332 unsigned Opc = InFlag.getOpcode(); (void)Opc;
333 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
334 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
335 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
338 if (Opcode == ISD::ADDE) {
339 CmpLHS = InFlag.getValue(0);
342 CmpLHS = InFlag.getOperand(0);
346 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
348 SDValue LHS = Node->getOperand(0);
349 SDValue RHS = Node->getOperand(1);
351 EVT VT = LHS.getValueType();
352 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
353 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
354 SDValue(Carry,0), RHS);
356 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
357 LHS, SDValue(AddCarry,0));
360 /// Mul/Div with two results
365 case ISD::UMUL_LOHI: {
366 SDValue Op1 = Node->getOperand(0);
367 SDValue Op2 = Node->getOperand(1);
370 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
372 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
374 SDValue InFlag = SDValue(Mul, 0);
375 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
377 InFlag = SDValue(Lo,1);
378 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
380 if (!SDValue(Node, 0).use_empty())
381 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
383 if (!SDValue(Node, 1).use_empty())
384 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
391 if (Subtarget.isMips32())
395 SDValue MulOp1 = Node->getOperand(0);
396 SDValue MulOp2 = Node->getOperand(1);
398 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
399 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
400 MVT::Glue, MulOp1, MulOp2);
402 SDValue InFlag = SDValue(MulNode, 0);
404 if (Opcode == ISD::MUL)
405 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
407 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
410 /// Div/Rem operations
417 // Get target GOT address.
418 case ISD::GLOBAL_OFFSET_TABLE:
419 return getGlobalBaseReg();
421 case ISD::ConstantFP: {
422 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
423 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
424 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
425 Mips::ZERO, MVT::i32);
426 SDValue Undef = SDValue(
427 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
428 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
429 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
430 MVT::f64, Undef, SDValue(MTC, 0));
431 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
432 MVT::f64, I0, SDValue(MTC, 0));
433 ReplaceUses(SDValue(Node, 0), I1);
440 if (SDNode *ResNode = SelectLoadFp64(Node))
442 // Other cases are autogenerated.
446 if (SDNode *ResNode = SelectStoreFp64(Node))
448 // Other cases are autogenerated.
451 case MipsISD::ThreadPointer: {
452 unsigned SrcReg = Mips::HWR29;
453 unsigned DestReg = Mips::V1;
454 SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
455 Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
456 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
458 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
459 ReplaceUses(SDValue(Node, 0), ResNode);
460 return ResNode.getNode();
464 // Select the default instruction
465 SDNode *ResNode = SelectCode(Node);
467 DEBUG(errs() << "=> ");
468 if (ResNode == NULL || ResNode == Node)
469 DEBUG(Node->dump(CurDAG));
471 DEBUG(ResNode->dump(CurDAG));
472 DEBUG(errs() << "\n");
476 /// createMipsISelDag - This pass converts a legalized DAG into a
477 /// MIPS-specific DAG, ready for instruction scheduling.
478 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
479 return new MipsDAGToDAGISel(TM);