1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsISelDAGToDAG.h"
16 #include "Mips16ISelDAGToDAG.h"
17 #include "MipsSEISelDAGToDAG.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CFG.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetMachine.h"
39 //===----------------------------------------------------------------------===//
40 // Instruction Selector Implementation
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
44 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
45 // instructions for SelectionDAG operations.
46 //===----------------------------------------------------------------------===//
48 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
49 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
51 processFunctionAfterISel(MF);
56 /// getGlobalBaseReg - Output the instructions required to put the
57 /// GOT address into a register.
58 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
59 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
60 return CurDAG->getRegister(GlobalBaseReg,
61 getTargetLowering()->getPointerTy()).getNode();
64 /// ComplexPattern used on MipsInstrInfo
65 /// Used on Mips Load/Store instructions
66 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const {
68 llvm_unreachable("Unimplemented function.");
72 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
73 SDValue &Offset) const {
74 llvm_unreachable("Unimplemented function.");
78 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
79 SDValue &Offset) const {
80 llvm_unreachable("Unimplemented function.");
84 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
85 SDValue &Offset) const {
86 llvm_unreachable("Unimplemented function.");
90 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
91 SDValue &Offset) const {
92 llvm_unreachable("Unimplemented function.");
96 bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
97 SDValue &Offset, SDValue &Alias) {
98 llvm_unreachable("Unimplemented function.");
102 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
103 llvm_unreachable("Unimplemented function.");
107 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
108 llvm_unreachable("Unimplemented function.");
112 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
113 llvm_unreachable("Unimplemented function.");
117 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
118 llvm_unreachable("Unimplemented function.");
122 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
123 llvm_unreachable("Unimplemented function.");
127 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
128 llvm_unreachable("Unimplemented function.");
132 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
133 llvm_unreachable("Unimplemented function.");
137 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
138 llvm_unreachable("Unimplemented function.");
142 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
143 llvm_unreachable("Unimplemented function.");
147 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
148 llvm_unreachable("Unimplemented function.");
152 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const {
153 llvm_unreachable("Unimplemented function.");
157 bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
158 llvm_unreachable("Unimplemented function.");
162 bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
163 llvm_unreachable("Unimplemented function.");
167 /// Select instructions not customized! Used for
168 /// expanded, promoted and normal instructions
169 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
170 unsigned Opcode = Node->getOpcode();
172 // Dump information about the Node being selected
173 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
175 // If we have a custom node, we already have selected!
176 if (Node->isMachineOpcode()) {
177 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
182 // See if subclasses can handle this node.
183 std::pair<bool, SDNode*> Ret = selectNode(Node);
191 // Get target GOT address.
192 case ISD::GLOBAL_OFFSET_TABLE:
193 return getGlobalBaseReg();
198 assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
199 cast<MemSDNode>(Node)->getAlignment() &&
200 "Unexpected unaligned loads/stores.");
205 // Select the default instruction
206 SDNode *ResNode = SelectCode(Node);
208 DEBUG(errs() << "=> ");
209 if (ResNode == NULL || ResNode == Node)
210 DEBUG(Node->dump(CurDAG));
212 DEBUG(ResNode->dump(CurDAG));
213 DEBUG(errs() << "\n");
217 bool MipsDAGToDAGISel::
218 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
219 std::vector<SDValue> &OutOps) {
220 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
221 OutOps.push_back(Op);
225 /// createMipsISelDag - This pass converts a legalized DAG into a
226 /// MIPS-specific DAG, ready for instruction scheduling.
227 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
228 if (TM.getSubtargetImpl()->inMips16Mode())
229 return llvm::createMips16ISelDag(TM);
231 return llvm::createMipsSEISelDag(TM);