1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 //===----------------------------------------------------------------------===//
39 // Instruction Selector Implementation
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
43 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
44 // instructions for SelectionDAG operations.
45 //===----------------------------------------------------------------------===//
48 class MipsDAGToDAGISel : public SelectionDAGISel {
50 /// TM - Keep a reference to MipsTargetMachine.
51 MipsTargetMachine &TM;
53 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
54 /// make the right decision when generating code for different targets.
55 const MipsSubtarget &Subtarget;
58 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
60 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual void InstructionSelect();
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
71 // Include the pieces autogenerated from the target description.
72 #include "MipsGenDAGISel.inc"
74 /// getTargetMachine - Return a reference to the TargetMachine, casted
75 /// to the target-specific type.
76 const MipsTargetMachine &getTargetMachine() {
77 return static_cast<const MipsTargetMachine &>(TM);
80 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
81 /// to the target-specific type.
82 const MipsInstrInfo *getInstrInfo() {
83 return getTargetMachine().getInstrInfo();
86 SDNode *getGlobalBaseReg();
87 SDNode *Select(SDNode *N);
90 bool SelectAddr(SDNode *Op, SDValue N,
91 SDValue &Base, SDValue &Offset);
93 SDNode *SelectLoadFp64(SDNode *N);
94 SDNode *SelectStoreFp64(SDNode *N);
96 // getI32Imm - Return a target constant with the specified
97 // value, of type i32.
98 inline SDValue getI32Imm(unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, MVT::i32);
110 /// InstructionSelect - This callback is invoked by
111 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
112 void MipsDAGToDAGISel::InstructionSelect() {
113 // Codegen the basic block.
114 DEBUG(errs() << "===== Instruction selection begins:\n");
117 // Select target instructions for the DAG.
120 DEBUG(errs() << "===== Instruction selection ends:\n");
122 CurDAG->RemoveDeadNodes();
125 /// getGlobalBaseReg - Output the instructions required to put the
126 /// GOT address into a register.
127 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
128 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
129 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
132 /// ComplexPattern used on MipsInstrInfo
133 /// Used on Mips Load/Store instructions
134 bool MipsDAGToDAGISel::
135 SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
137 // if Address is FI, get the TargetFrameIndex.
138 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
139 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
140 Offset = CurDAG->getTargetConstant(0, MVT::i32);
144 // on PIC code Load GA
145 if (TM.getRelocationModel() == Reloc::PIC_) {
146 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
147 (Addr.getOpcode() == ISD::TargetConstantPool) ||
148 (Addr.getOpcode() == ISD::TargetJumpTable)){
149 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
154 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
155 Addr.getOpcode() == ISD::TargetGlobalAddress))
159 // Operand is a result from an ADD.
160 if (Addr.getOpcode() == ISD::ADD) {
161 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
162 if (Predicate_immSExt16(CN)) {
164 // If the first operand is a FI, get the TargetFI Node
165 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
166 (Addr.getOperand(0))) {
167 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
169 Base = Addr.getOperand(0);
172 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
177 // When loading from constant pools, load the lower address part in
178 // the instruction itself. Example, instead of:
179 // lui $2, %hi($CPI1_0)
180 // addiu $2, $2, %lo($CPI1_0)
183 // lui $2, %hi($CPI1_0)
184 // lwc1 $f0, %lo($CPI1_0)($2)
185 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
186 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
187 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
188 SDValue LoVal = Addr.getOperand(1);
189 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
190 Base = Addr.getOperand(0);
191 Offset = LoVal.getOperand(0);
198 Offset = CurDAG->getTargetConstant(0, MVT::i32);
202 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
203 MVT::SimpleValueType NVT =
204 N->getValueType(0).getSimpleVT().SimpleTy;
206 if (!Subtarget.isMips1() || NVT != MVT::f64)
209 if (!Predicate_unindexedload(N) ||
213 SDValue Chain = N->getOperand(0);
214 SDValue N1 = N->getOperand(1);
215 SDValue Offset0, Offset1, Base;
217 if (!SelectAddr(N, N1, Offset0, Base) ||
218 N1.getValueType() != MVT::i32)
221 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
222 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
223 DebugLoc dl = N->getDebugLoc();
225 // The second load should start after for 4 bytes.
226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
227 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
228 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
229 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
233 CP->getTargetFlags());
237 // Choose the offsets depending on the endianess
238 if (TM.getTargetData()->isBigEndian())
239 std::swap(Offset0, Offset1);
246 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
247 MVT::Other, Offset0, Base, Chain);
248 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
250 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
251 MVT::f64, Undef, SDValue(LD0, 0));
253 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
254 MVT::Other, Offset1, Base, SDValue(LD0, 1));
255 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
256 MVT::f64, I0, SDValue(LD1, 0));
258 ReplaceUses(SDValue(N, 0), I1);
259 ReplaceUses(SDValue(N, 1), Chain);
260 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
261 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
265 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
267 if (!Subtarget.isMips1() ||
268 N->getOperand(1).getValueType() != MVT::f64)
271 SDValue Chain = N->getOperand(0);
273 if (!Predicate_unindexedstore(N) ||
277 SDValue N1 = N->getOperand(1);
278 SDValue N2 = N->getOperand(2);
279 SDValue Offset0, Offset1, Base;
281 if (!SelectAddr(N, N2, Offset0, Base) ||
282 N1.getValueType() != MVT::f64 ||
283 N2.getValueType() != MVT::i32)
286 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
287 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
288 DebugLoc dl = N->getDebugLoc();
290 // Get the even and odd part from the f64 register
291 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD,
293 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN,
296 // The second store should start after for 4 bytes.
297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
298 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
302 // Choose the offsets depending on the endianess
303 if (TM.getTargetData()->isBigEndian())
304 std::swap(Offset0, Offset1);
311 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
312 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
313 MVT::Other, Ops0, 4), 0);
314 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
316 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
317 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
318 MVT::Other, Ops1, 4), 0);
319 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
321 ReplaceUses(SDValue(N, 0), Chain);
322 return Chain.getNode();
325 /// Select instructions not customized! Used for
326 /// expanded, promoted and normal instructions
327 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
328 unsigned Opcode = Node->getOpcode();
329 DebugLoc dl = Node->getDebugLoc();
331 // Dump information about the Node being selected
332 DEBUG(errs().indent(Indent) << "Selecting: ";
337 // If we have a custom node, we already have selected!
338 if (Node->isMachineOpcode()) {
339 DEBUG(errs().indent(Indent-2) << "== ";
347 // Instruction Selection not handled by the auto-generated
348 // tablegen selection should be handled here.
356 SDValue InFlag = Node->getOperand(2), CmpLHS;
357 unsigned Opc = InFlag.getOpcode(); Opc=Opc;
358 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
359 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
360 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
363 if (Opcode == ISD::ADDE) {
364 CmpLHS = InFlag.getValue(0);
367 CmpLHS = InFlag.getOperand(0);
371 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
373 SDValue LHS = Node->getOperand(0);
374 SDValue RHS = Node->getOperand(1);
376 EVT VT = LHS.getValueType();
377 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
378 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
379 SDValue(Carry,0), RHS);
381 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
382 LHS, SDValue(AddCarry,0));
385 /// Mul/Div with two results
389 case ISD::UMUL_LOHI: {
390 SDValue Op1 = Node->getOperand(0);
391 SDValue Op2 = Node->getOperand(1);
394 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
395 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
397 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
399 SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
401 SDValue InFlag = SDValue(MulDiv, 0);
402 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
404 InFlag = SDValue(Lo,1);
405 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
407 if (!SDValue(Node, 0).use_empty())
408 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
410 if (!SDValue(Node, 1).use_empty())
411 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
420 SDValue MulOp1 = Node->getOperand(0);
421 SDValue MulOp2 = Node->getOperand(1);
423 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
424 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
425 MVT::Flag, MulOp1, MulOp2);
427 SDValue InFlag = SDValue(MulNode, 0);
429 if (MulOp == ISD::MUL)
430 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
432 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
435 /// Div/Rem operations
440 SDValue Op1 = Node->getOperand(0);
441 SDValue Op2 = Node->getOperand(1);
444 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
445 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
448 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
451 SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
453 SDValue InFlag = SDValue(Node, 0);
454 return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
457 // Get target GOT address.
458 case ISD::GLOBAL_OFFSET_TABLE:
459 return getGlobalBaseReg();
461 case ISD::ConstantFP: {
462 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
463 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
464 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
465 Mips::ZERO, MVT::i32);
466 SDValue Undef = SDValue(
467 CurDAG->getMachineNode(
468 TargetInstrInfo::IMPLICIT_DEF, dl, MVT::f64), 0);
469 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
470 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
471 MVT::f64, Undef, SDValue(MTC, 0));
472 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
473 MVT::f64, I0, SDValue(MTC, 0));
474 ReplaceUses(SDValue(Node, 0), I1);
481 if (SDNode *ResNode = SelectLoadFp64(Node))
483 // Other cases are autogenerated.
487 if (SDNode *ResNode = SelectStoreFp64(Node))
489 // Other cases are autogenerated.
492 /// Handle direct and indirect calls when using PIC. On PIC, when
493 /// GOT is smaller than about 64k (small code) the GA target is
494 /// loaded with only one instruction. Otherwise GA's target must
495 /// be loaded with 3 instructions.
496 case MipsISD::JmpLink: {
497 if (TM.getRelocationModel() == Reloc::PIC_) {
498 unsigned LastOpNum = Node->getNumOperands()-1;
500 SDValue Chain = Node->getOperand(0);
501 SDValue Callee = Node->getOperand(1);
504 // Skip the incomming flag if present
505 if (Node->getOperand(LastOpNum).getValueType() == MVT::Flag)
508 if ( (isa<GlobalAddressSDNode>(Callee)) ||
509 (isa<ExternalSymbolSDNode>(Callee)) )
511 /// Direct call for global addresses and external symbols
512 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
514 // Use load to get GOT target
515 SDValue Ops[] = { Callee, GPReg, Chain };
516 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
517 MVT::Other, Ops, 3), 0);
518 Chain = Load.getValue(1);
520 // Call target must be on T9
521 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
524 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
526 // Map the JmpLink operands to JALR
527 SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Flag);
528 SmallVector<SDValue, 8> Ops;
529 Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
531 for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
532 Ops.push_back(Node->getOperand(i));
533 Ops.push_back(Chain);
534 Ops.push_back(Chain.getValue(1));
536 // Emit Jump and Link Register
537 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
538 &Ops[0], Ops.size());
540 // Replace Chain and InFlag
541 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
542 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
548 // Select the default instruction
549 SDNode *ResNode = SelectCode(Node);
551 DEBUG(errs().indent(Indent-2) << "=> ");
552 if (ResNode == NULL || ResNode == Node)
553 DEBUG(Node->dump(CurDAG));
555 DEBUG(ResNode->dump(CurDAG));
556 DEBUG(errs() << "\n");
562 /// createMipsISelDag - This pass converts a legalized DAG into a
563 /// MIPS-specific DAG, ready for instruction scheduling.
564 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
565 return new MipsDAGToDAGISel(TM);