1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 //===----------------------------------------------------------------------===//
39 // Instruction Selector Implementation
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
43 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
44 // instructions for SelectionDAG operations.
45 //===----------------------------------------------------------------------===//
48 class MipsDAGToDAGISel : public SelectionDAGISel {
50 /// TM - Keep a reference to MipsTargetMachine.
51 MipsTargetMachine &TM;
53 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
54 /// make the right decision when generating code for different targets.
55 const MipsSubtarget &Subtarget;
58 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
60 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual void InstructionSelect();
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
71 // Include the pieces autogenerated from the target description.
72 #include "MipsGenDAGISel.inc"
74 /// getTargetMachine - Return a reference to the TargetMachine, casted
75 /// to the target-specific type.
76 const MipsTargetMachine &getTargetMachine() {
77 return static_cast<const MipsTargetMachine &>(TM);
80 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
81 /// to the target-specific type.
82 const MipsInstrInfo *getInstrInfo() {
83 return getTargetMachine().getInstrInfo();
86 SDNode *getGlobalBaseReg();
87 SDNode *Select(SDValue N);
90 bool SelectAddr(SDValue Op, SDValue N,
91 SDValue &Base, SDValue &Offset);
93 SDNode *SelectLoadFp64(SDValue N);
94 SDNode *SelectStoreFp64(SDValue N);
96 // getI32Imm - Return a target constant with the specified
97 // value, of type i32.
98 inline SDValue getI32Imm(unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, MVT::i32);
110 /// InstructionSelect - This callback is invoked by
111 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
112 void MipsDAGToDAGISel::InstructionSelect() {
113 // Codegen the basic block.
114 DEBUG(errs() << "===== Instruction selection begins:\n");
117 // Select target instructions for the DAG.
120 DEBUG(errs() << "===== Instruction selection ends:\n");
122 CurDAG->RemoveDeadNodes();
125 /// getGlobalBaseReg - Output the instructions required to put the
126 /// GOT address into a register.
127 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
128 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
129 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
132 /// ComplexPattern used on MipsInstrInfo
133 /// Used on Mips Load/Store instructions
134 bool MipsDAGToDAGISel::
135 SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
137 // if Address is FI, get the TargetFrameIndex.
138 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
139 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
140 Offset = CurDAG->getTargetConstant(0, MVT::i32);
144 // on PIC code Load GA
145 if (TM.getRelocationModel() == Reloc::PIC_) {
146 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
147 (Addr.getOpcode() == ISD::TargetJumpTable)){
148 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
153 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
154 Addr.getOpcode() == ISD::TargetGlobalAddress))
158 // Operand is a result from an ADD.
159 if (Addr.getOpcode() == ISD::ADD) {
160 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
161 if (Predicate_immSExt16(CN)) {
163 // If the first operand is a FI, get the TargetFI Node
164 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
165 (Addr.getOperand(0))) {
166 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
168 Base = Addr.getOperand(0);
171 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
176 // When loading from constant pools, load the lower address part in
177 // the instruction itself. Instead of:
178 // lui $2, %hi($CPI1_0)
179 // addiu $2, $2, %lo($CPI1_0)
182 // lui $2, %hi($CPI1_0)
183 // lwc1 $f0, %lo($CPI1_0)($2)
184 if (Addr.getOperand(0).getOpcode() == MipsISD::Hi &&
185 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
186 SDValue LoVal = Addr.getOperand(1);
187 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(
188 LoVal.getOperand(0))) {
189 if (!CP->getOffset()) {
190 Base = Addr.getOperand(0);
191 Offset = LoVal.getOperand(0);
199 Offset = CurDAG->getTargetConstant(0, MVT::i32);
203 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDValue N) {
204 MVT::SimpleValueType NVT =
205 N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
207 if (!Subtarget.isMips1() || NVT != MVT::f64)
210 if (!Predicate_unindexedload(N.getNode()) ||
211 !Predicate_load(N.getNode()))
214 SDValue Chain = N.getOperand(0);
215 SDValue N1 = N.getOperand(1);
216 SDValue Offset0, Offset1, Base;
218 if (!SelectAddr(N, N1, Offset0, Base) ||
219 N1.getValueType() != MVT::i32)
222 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
223 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
224 DebugLoc dl = N.getDebugLoc();
226 // The second load should start after for 4 bytes.
227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
228 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
229 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
230 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
234 CP->getTargetFlags());
243 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
244 MVT::Other, Offset0, Base, Chain);
245 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
247 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
248 MVT::f64, Undef, SDValue(LD0, 0));
250 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
251 MVT::Other, Offset1, Base, SDValue(LD0, 1));
252 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
253 MVT::f64, I0, SDValue(LD1, 0));
256 ReplaceUses(N.getValue(1), Chain);
257 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
258 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
262 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDValue N) {
264 if (!Subtarget.isMips1() ||
265 N.getOperand(1).getValueType() != MVT::f64)
268 SDValue Chain = N.getOperand(0);
270 if (!Predicate_unindexedstore(N.getNode()) ||
271 !Predicate_store(N.getNode()))
274 SDValue N1 = N.getOperand(1);
275 SDValue N2 = N.getOperand(2);
276 SDValue Offset0, Offset1, Base;
278 if (!SelectAddr(N, N2, Offset0, Base) ||
279 N1.getValueType() != MVT::f64 ||
280 N2.getValueType() != MVT::i32)
283 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
284 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
285 DebugLoc dl = N.getDebugLoc();
287 // Get the even and odd part from the f64 register
288 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD,
290 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN,
293 // The second store should start after for 4 bytes.
294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
295 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
304 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
305 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
306 MVT::Other, Ops0, 4), 0);
307 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
309 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
310 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
311 MVT::Other, Ops1, 4), 0);
312 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
314 ReplaceUses(N.getValue(0), Chain);
315 return Chain.getNode();
318 /// Select instructions not customized! Used for
319 /// expanded, promoted and normal instructions
320 SDNode* MipsDAGToDAGISel::Select(SDValue N) {
321 SDNode *Node = N.getNode();
322 unsigned Opcode = Node->getOpcode();
323 DebugLoc dl = Node->getDebugLoc();
325 // Dump information about the Node being selected
326 DEBUG(errs().indent(Indent) << "Selecting: ";
331 // If we have a custom node, we already have selected!
332 if (Node->isMachineOpcode()) {
333 DEBUG(errs().indent(Indent-2) << "== ";
341 // Instruction Selection not handled by the auto-generated
342 // tablegen selection should be handled here.
350 SDValue InFlag = Node->getOperand(2), CmpLHS;
351 unsigned Opc = InFlag.getOpcode(); Opc=Opc;
352 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
353 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
354 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
357 if (Opcode == ISD::ADDE) {
358 CmpLHS = InFlag.getValue(0);
361 CmpLHS = InFlag.getOperand(0);
365 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
367 SDValue LHS = Node->getOperand(0);
368 SDValue RHS = Node->getOperand(1);
370 EVT VT = LHS.getValueType();
371 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
372 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
373 SDValue(Carry,0), RHS);
375 return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
376 LHS, SDValue(AddCarry,0));
379 /// Mul/Div with two results
383 case ISD::UMUL_LOHI: {
384 SDValue Op1 = Node->getOperand(0);
385 SDValue Op2 = Node->getOperand(1);
388 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
389 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
391 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
393 SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
395 SDValue InFlag = SDValue(Node, 0);
396 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
398 InFlag = SDValue(Lo,1);
399 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
401 if (!N.getValue(0).use_empty())
402 ReplaceUses(N.getValue(0), SDValue(Lo,0));
404 if (!N.getValue(1).use_empty())
405 ReplaceUses(N.getValue(1), SDValue(Hi,0));
414 SDValue MulOp1 = Node->getOperand(0);
415 SDValue MulOp2 = Node->getOperand(1);
417 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
418 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
419 MVT::Flag, MulOp1, MulOp2);
421 SDValue InFlag = SDValue(MulNode, 0);
423 if (MulOp == ISD::MUL)
424 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
426 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
429 /// Div/Rem operations
434 SDValue Op1 = Node->getOperand(0);
435 SDValue Op2 = Node->getOperand(1);
438 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
439 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
442 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
445 SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
447 SDValue InFlag = SDValue(Node, 0);
448 return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
451 // Get target GOT address.
452 case ISD::GLOBAL_OFFSET_TABLE:
453 return getGlobalBaseReg();
455 case ISD::ConstantFP: {
456 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
457 if (N.getValueType() == MVT::f64 && CN->isExactlyValue(+0.0)) {
458 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
459 ReplaceUses(N, Zero);
460 return Zero.getNode();
466 if (SDNode *ResNode = SelectLoadFp64(N))
468 // Other cases are autogenerated.
472 if (SDNode *ResNode = SelectStoreFp64(N))
474 // Other cases are autogenerated.
477 /// Handle direct and indirect calls when using PIC. On PIC, when
478 /// GOT is smaller than about 64k (small code) the GA target is
479 /// loaded with only one instruction. Otherwise GA's target must
480 /// be loaded with 3 instructions.
481 case MipsISD::JmpLink: {
482 if (TM.getRelocationModel() == Reloc::PIC_) {
483 SDValue Chain = Node->getOperand(0);
484 SDValue Callee = Node->getOperand(1);
485 SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
486 SDValue InFlag(0, 0);
488 if ( (isa<GlobalAddressSDNode>(Callee)) ||
489 (isa<ExternalSymbolSDNode>(Callee)) )
491 /// Direct call for global addresses and external symbols
492 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
494 // Use load to get GOT target
495 SDValue Ops[] = { Callee, GPReg, Chain };
496 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
497 MVT::Other, Ops, 3), 0);
498 Chain = Load.getValue(1);
500 // Call target must be on T9
501 Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Load, InFlag);
504 Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
506 // Emit Jump and Link Register
507 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, MVT::Other,
508 MVT::Flag, T9Reg, Chain);
509 Chain = SDValue(ResNode, 0);
510 InFlag = SDValue(ResNode, 1);
511 ReplaceUses(SDValue(Node, 0), Chain);
512 ReplaceUses(SDValue(Node, 1), InFlag);
518 // Select the default instruction
519 SDNode *ResNode = SelectCode(N);
521 DEBUG(errs().indent(Indent-2) << "=> ");
522 if (ResNode == NULL || ResNode == N.getNode())
523 DEBUG(N.getNode()->dump(CurDAG));
525 DEBUG(ResNode->dump(CurDAG));
526 DEBUG(errs() << "\n");
532 /// createMipsISelDag - This pass converts a legalized DAG into a
533 /// MIPS-specific DAG, ready for instruction scheduling.
534 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
535 return new MipsDAGToDAGISel(TM);