1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MCTargetDesc/MipsBaseInfo.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
69 virtual bool runOnMachineFunction(MachineFunction &MF);
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90 EVT Ty, bool HasLo, bool HasHi);
92 SDNode *Select(SDNode *N);
95 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
97 // getImm - Return a target constant with the specified value.
98 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
102 void ProcessFunctionAfterISel(MachineFunction &MF);
103 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104 void InitGlobalBaseReg(MachineFunction &MF);
106 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
108 std::vector<SDValue> &OutOps);
113 // Insert instructions to initialize the global base register in the
114 // first MBB of the function. When the ABI is O32 and the relocation model is
115 // PIC, the necessary instructions are emitted later to prevent optimization
116 // passes from moving them.
117 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
120 if (((MF.getTarget().getRelocationModel() == Reloc::Static) ||
121 Subtarget.inMips16Mode()) && !MipsFI->globalBaseRegSet())
124 MachineBasicBlock &MBB = MF.front();
125 MachineBasicBlock::iterator I = MBB.begin();
126 MachineRegisterInfo &RegInfo = MF.getRegInfo();
127 const MipsRegisterInfo *TargetRegInfo = TM.getRegisterInfo();
128 const MipsInstrInfo *MII = TM.getInstrInfo();
129 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
130 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
131 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134 FI= MipsFI->initGlobalRegFI();
136 const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
137 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
138 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
140 if (Subtarget.inMips16Mode())
141 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
143 V0 = RegInfo.createVirtualRegister(RC);
144 V1 = RegInfo.createVirtualRegister(RC);
145 V2 = RegInfo.createVirtualRegister(RC);
147 if (Subtarget.isABI_N64()) {
148 MF.getRegInfo().addLiveIn(Mips::T9_64);
149 MBB.addLiveIn(Mips::T9_64);
151 // lui $v0, %hi(%neg(%gp_rel(fname)))
152 // daddu $v1, $v0, $t9
153 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
154 const GlobalValue *FName = MF.getFunction();
155 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
157 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
158 .addReg(Mips::T9_64);
159 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
160 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
161 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
166 if (Subtarget.inMips16Mode()) {
167 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
168 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
169 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16),
171 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
172 BuildMI(MBB, I, DL, TII.get(Mips::SllX16),
173 V2 ).addReg(V0).addImm(16);
174 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
175 .addReg(V1).addReg(V2);
181 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
182 // Set global register to __gnu_local_gp.
184 // lui $v0, %hi(__gnu_local_gp)
185 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
186 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
187 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
188 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
189 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
193 MF.getRegInfo().addLiveIn(Mips::T9);
194 MBB.addLiveIn(Mips::T9);
196 if (Subtarget.isABI_N32()) {
197 // lui $v0, %hi(%neg(%gp_rel(fname)))
198 // addu $v1, $v0, $t9
199 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
200 const GlobalValue *FName = MF.getFunction();
201 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
202 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
203 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
204 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
205 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
206 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
211 assert(Subtarget.isABI_O32());
214 //if (Subtarget.inMips16Mode())
215 // return; // no need to load GP. It can be calculated anywhere
219 // For O32 ABI, the following instruction sequence is emitted to initialize
220 // the global base register:
222 // 0. lui $2, %hi(_gp_disp)
223 // 1. addiu $2, $2, %lo(_gp_disp)
224 // 2. addu $globalbasereg, $2, $t9
226 // We emit only the last instruction here.
228 // GNU linker requires that the first two instructions appear at the beginning
229 // of a function and no instructions be inserted before or between them.
230 // The two instructions are emitted during lowering to MC layer in order to
231 // avoid any reordering.
233 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
234 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
236 MF.getRegInfo().addLiveIn(Mips::V0);
237 MBB.addLiveIn(Mips::V0);
238 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
239 .addReg(Mips::V0).addReg(Mips::T9);
240 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, TargetRegInfo);
243 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
244 const MachineInstr& MI) {
245 unsigned DstReg = 0, ZeroReg = 0;
247 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
248 if ((MI.getOpcode() == Mips::ADDiu) &&
249 (MI.getOperand(1).getReg() == Mips::ZERO) &&
250 (MI.getOperand(2).getImm() == 0)) {
251 DstReg = MI.getOperand(0).getReg();
252 ZeroReg = Mips::ZERO;
253 } else if ((MI.getOpcode() == Mips::DADDiu) &&
254 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
255 (MI.getOperand(2).getImm() == 0)) {
256 DstReg = MI.getOperand(0).getReg();
257 ZeroReg = Mips::ZERO_64;
263 // Replace uses with ZeroReg.
264 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
265 E = MRI->use_end(); U != E; ++U) {
266 MachineOperand &MO = U.getOperand();
267 MachineInstr *MI = MO.getParent();
269 // Do not replace if it is a phi's operand or is tied to def operand.
270 if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
280 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
281 InitGlobalBaseReg(MF);
283 MachineRegisterInfo *MRI = &MF.getRegInfo();
285 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
287 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
288 ReplaceUsesWithZeroReg(MRI, *I);
291 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
292 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
294 ProcessFunctionAfterISel(MF);
299 /// getGlobalBaseReg - Output the instructions required to put the
300 /// GOT address into a register.
301 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
302 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
303 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
306 /// ComplexPattern used on MipsInstrInfo
307 /// Used on Mips Load/Store instructions
308 bool MipsDAGToDAGISel::
309 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
310 EVT ValTy = Addr.getValueType();
312 // If Parent is an unaligned f32 load or store, select a (base + index)
313 // floating point load/store instruction (luxc1 or suxc1).
314 const LSBaseSDNode *LS = 0;
316 if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
317 EVT VT = LS->getMemoryVT();
319 if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
320 assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
321 "Unaligned loads/stores not supported for this type.");
327 // if Address is FI, get the TargetFrameIndex.
328 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
329 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
330 Offset = CurDAG->getTargetConstant(0, ValTy);
334 // on PIC code Load GA
335 if (Addr.getOpcode() == MipsISD::Wrapper) {
336 Base = Addr.getOperand(0);
337 Offset = Addr.getOperand(1);
341 if (TM.getRelocationModel() != Reloc::PIC_) {
342 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
343 Addr.getOpcode() == ISD::TargetGlobalAddress))
347 // Addresses of the form FI+const or FI|const
348 if (CurDAG->isBaseWithConstantOffset(Addr)) {
349 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
350 if (isInt<16>(CN->getSExtValue())) {
352 // If the first operand is a FI, get the TargetFI Node
353 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
354 (Addr.getOperand(0)))
355 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
357 Base = Addr.getOperand(0);
359 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
364 // Operand is a result from an ADD.
365 if (Addr.getOpcode() == ISD::ADD) {
366 // When loading from constant pools, load the lower address part in
367 // the instruction itself. Example, instead of:
368 // lui $2, %hi($CPI1_0)
369 // addiu $2, $2, %lo($CPI1_0)
372 // lui $2, %hi($CPI1_0)
373 // lwc1 $f0, %lo($CPI1_0)($2)
374 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
375 SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0);
376 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
377 isa<JumpTableSDNode>(Opnd0)) {
378 Base = Addr.getOperand(0);
384 // If an indexed floating point load/store can be emitted, return false.
386 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
387 Subtarget.hasMips32r2Or64())
392 Offset = CurDAG->getTargetConstant(0, ValTy);
396 /// Select multiply instructions.
397 std::pair<SDNode*, SDNode*>
398 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
399 bool HasLo, bool HasHi) {
400 SDNode *Lo = 0, *Hi = 0;
401 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
403 SDValue InFlag = SDValue(Mul, 0);
406 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
407 Ty, MVT::Glue, InFlag);
408 InFlag = SDValue(Lo, 1);
411 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
414 return std::make_pair(Lo, Hi);
418 /// Select instructions not customized! Used for
419 /// expanded, promoted and normal instructions
420 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
421 unsigned Opcode = Node->getOpcode();
422 DebugLoc dl = Node->getDebugLoc();
424 // Dump information about the Node being selected
425 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
427 // If we have a custom node, we already have selected!
428 if (Node->isMachineOpcode()) {
429 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
434 // Instruction Selection not handled by the auto-generated
435 // tablegen selection should be handled here.
437 EVT NodeTy = Node->getValueType(0);
445 SDValue InFlag = Node->getOperand(2), CmpLHS;
446 unsigned Opc = InFlag.getOpcode(); (void)Opc;
447 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
448 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
449 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
452 if (Opcode == ISD::ADDE) {
453 CmpLHS = InFlag.getValue(0);
456 CmpLHS = InFlag.getOperand(0);
460 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
462 SDValue LHS = Node->getOperand(0);
463 SDValue RHS = Node->getOperand(1);
465 EVT VT = LHS.getValueType();
466 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
467 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
468 SDValue(Carry,0), RHS);
470 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
471 LHS, SDValue(AddCarry,0));
474 /// Mul with two results
476 case ISD::UMUL_LOHI: {
477 if (NodeTy == MVT::i32)
478 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
480 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
482 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
485 if (!SDValue(Node, 0).use_empty())
486 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
488 if (!SDValue(Node, 1).use_empty())
489 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
496 // Mips32 has a 32-bit three operand mul instruction.
497 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
499 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
500 dl, NodeTy, true, false).first;
504 if (NodeTy == MVT::i32)
505 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
507 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
509 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
512 // Get target GOT address.
513 case ISD::GLOBAL_OFFSET_TABLE:
514 return getGlobalBaseReg();
516 case ISD::ConstantFP: {
517 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
518 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
519 if (Subtarget.hasMips64()) {
520 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
521 Mips::ZERO_64, MVT::i64);
522 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
525 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
526 Mips::ZERO, MVT::i32);
527 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
533 case ISD::Constant: {
534 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
535 unsigned Size = CN->getValueSizeInBits(0);
540 MipsAnalyzeImmediate AnalyzeImm;
541 int64_t Imm = CN->getSExtValue();
543 const MipsAnalyzeImmediate::InstSeq &Seq =
544 AnalyzeImm.Analyze(Imm, Size, false);
546 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
547 DebugLoc DL = CN->getDebugLoc();
549 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
552 // The first instruction can be a LUi which is different from other
553 // instructions (ADDiu, ORI and SLL) in that it does not have a register
555 if (Inst->Opc == Mips::LUi64)
556 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
559 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
560 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
563 // The remaining instructions in the sequence are handled here.
564 for (++Inst; Inst != Seq.end(); ++Inst) {
565 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
567 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
568 SDValue(RegOpnd, 0), ImmOpnd);
574 case MipsISD::ThreadPointer: {
575 EVT PtrVT = TLI.getPointerTy();
576 unsigned RdhwrOpc, SrcReg, DestReg;
578 if (PtrVT == MVT::i32) {
579 RdhwrOpc = Mips::RDHWR;
580 SrcReg = Mips::HWR29;
583 RdhwrOpc = Mips::RDHWR64;
584 SrcReg = Mips::HWR29_64;
585 DestReg = Mips::V1_64;
589 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
590 Node->getValueType(0),
591 CurDAG->getRegister(SrcReg, PtrVT));
592 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
594 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
595 ReplaceUses(SDValue(Node, 0), ResNode);
596 return ResNode.getNode();
600 // Select the default instruction
601 SDNode *ResNode = SelectCode(Node);
603 DEBUG(errs() << "=> ");
604 if (ResNode == NULL || ResNode == Node)
605 DEBUG(Node->dump(CurDAG));
607 DEBUG(ResNode->dump(CurDAG));
608 DEBUG(errs() << "\n");
612 bool MipsDAGToDAGISel::
613 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
614 std::vector<SDValue> &OutOps) {
615 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
616 OutOps.push_back(Op);
620 /// createMipsISelDag - This pass converts a legalized DAG into a
621 /// MIPS-specific DAG, ready for instruction scheduling.
622 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
623 return new MipsDAGToDAGISel(TM);