1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 // getI32Imm - Return a target constant with the specified
90 // value, of type i32.
91 inline SDValue getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
97 std::vector<SDValue> &OutOps);
103 /// getGlobalBaseReg - Output the instructions required to put the
104 /// GOT address into a register.
105 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
106 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
107 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
110 /// ComplexPattern used on MipsInstrInfo
111 /// Used on Mips Load/Store instructions
112 bool MipsDAGToDAGISel::
113 SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
114 // if Address is FI, get the TargetFrameIndex.
115 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
116 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
117 Offset = CurDAG->getTargetConstant(0, MVT::i32);
121 // on PIC code Load GA
122 if (TM.getRelocationModel() == Reloc::PIC_) {
123 if (Addr.getOpcode() == MipsISD::WrapperPIC) {
124 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
125 Offset = Addr.getOperand(0);
129 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
130 Addr.getOpcode() == ISD::TargetGlobalAddress))
132 else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
133 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
139 // Addresses of the form FI+const or FI|const
140 if (CurDAG->isBaseWithConstantOffset(Addr)) {
141 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
142 if (isInt<16>(CN->getSExtValue())) {
144 // If the first operand is a FI, get the TargetFI Node
145 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
146 (Addr.getOperand(0)))
147 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
149 Base = Addr.getOperand(0);
151 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
156 // Operand is a result from an ADD.
157 if (Addr.getOpcode() == ISD::ADD) {
158 // When loading from constant pools, load the lower address part in
159 // the instruction itself. Example, instead of:
160 // lui $2, %hi($CPI1_0)
161 // addiu $2, $2, %lo($CPI1_0)
164 // lui $2, %hi($CPI1_0)
165 // lwc1 $f0, %lo($CPI1_0)($2)
166 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
167 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
168 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
169 SDValue LoVal = Addr.getOperand(1);
170 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
171 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
172 Base = Addr.getOperand(0);
173 Offset = LoVal.getOperand(0);
180 Offset = CurDAG->getTargetConstant(0, MVT::i32);
184 /// Select instructions not customized! Used for
185 /// expanded, promoted and normal instructions
186 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
187 unsigned Opcode = Node->getOpcode();
188 DebugLoc dl = Node->getDebugLoc();
190 // Dump information about the Node being selected
191 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
193 // If we have a custom node, we already have selected!
194 if (Node->isMachineOpcode()) {
195 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
200 // Instruction Selection not handled by the auto-generated
201 // tablegen selection should be handled here.
208 SDValue InFlag = Node->getOperand(2), CmpLHS;
209 unsigned Opc = InFlag.getOpcode(); (void)Opc;
210 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
211 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
212 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
215 if (Opcode == ISD::ADDE) {
216 CmpLHS = InFlag.getValue(0);
219 CmpLHS = InFlag.getOperand(0);
223 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
225 SDValue LHS = Node->getOperand(0);
226 SDValue RHS = Node->getOperand(1);
228 EVT VT = LHS.getValueType();
229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
230 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
231 SDValue(Carry,0), RHS);
233 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
234 LHS, SDValue(AddCarry,0));
237 /// Mul with two results
239 case ISD::UMUL_LOHI: {
240 SDValue Op1 = Node->getOperand(0);
241 SDValue Op2 = Node->getOperand(1);
244 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
246 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
248 SDValue InFlag = SDValue(Mul, 0);
249 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
251 InFlag = SDValue(Lo,1);
252 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
254 if (!SDValue(Node, 0).use_empty())
255 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
257 if (!SDValue(Node, 1).use_empty())
258 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
265 if (Subtarget.isMips32())
269 SDValue MulOp1 = Node->getOperand(0);
270 SDValue MulOp2 = Node->getOperand(1);
272 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
273 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
274 MVT::Glue, MulOp1, MulOp2);
276 SDValue InFlag = SDValue(MulNode, 0);
278 if (Opcode == ISD::MUL)
279 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
281 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
284 // Get target GOT address.
285 case ISD::GLOBAL_OFFSET_TABLE:
286 return getGlobalBaseReg();
288 case ISD::ConstantFP: {
289 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
290 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
291 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
292 Mips::ZERO, MVT::i32);
293 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
299 case MipsISD::ThreadPointer: {
300 unsigned SrcReg = Mips::HWR29;
301 unsigned DestReg = Mips::V1;
302 SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
303 Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
304 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
306 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
307 ReplaceUses(SDValue(Node, 0), ResNode);
308 return ResNode.getNode();
312 // Select the default instruction
313 SDNode *ResNode = SelectCode(Node);
315 DEBUG(errs() << "=> ");
316 if (ResNode == NULL || ResNode == Node)
317 DEBUG(Node->dump(CurDAG));
319 DEBUG(ResNode->dump(CurDAG));
320 DEBUG(errs() << "\n");
324 bool MipsDAGToDAGISel::
325 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
326 std::vector<SDValue> &OutOps) {
327 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
328 OutOps.push_back(Op);
332 /// createMipsISelDag - This pass converts a legalized DAG into a
333 /// MIPS-specific DAG, ready for instruction scheduling.
334 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
335 return new MipsDAGToDAGISel(TM);