1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 // getImm - Return a target constant with the specified value.
90 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
91 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
94 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
96 std::vector<SDValue> &OutOps);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
113 EVT ValTy = Addr.getValueType();
114 unsigned GPReg = ValTy == MVT::i32 ? Mips::GP : Mips::GP_64;
116 // if Address is FI, get the TargetFrameIndex.
117 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
118 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
119 Offset = CurDAG->getTargetConstant(0, ValTy);
123 // on PIC code Load GA
124 if (Addr.getOpcode() == MipsISD::Wrapper) {
125 Base = CurDAG->getRegister(GPReg, ValTy);
126 Offset = Addr.getOperand(0);
130 if (TM.getRelocationModel() != Reloc::PIC_) {
131 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress))
136 // Addresses of the form FI+const or FI|const
137 if (CurDAG->isBaseWithConstantOffset(Addr)) {
138 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
139 if (isInt<16>(CN->getSExtValue())) {
141 // If the first operand is a FI, get the TargetFI Node
142 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
143 (Addr.getOperand(0)))
144 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
146 Base = Addr.getOperand(0);
148 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
153 // Operand is a result from an ADD.
154 if (Addr.getOpcode() == ISD::ADD) {
155 // When loading from constant pools, load the lower address part in
156 // the instruction itself. Example, instead of:
157 // lui $2, %hi($CPI1_0)
158 // addiu $2, $2, %lo($CPI1_0)
161 // lui $2, %hi($CPI1_0)
162 // lwc1 $f0, %lo($CPI1_0)($2)
163 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
164 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
165 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
166 SDValue LoVal = Addr.getOperand(1);
167 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
168 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
169 Base = Addr.getOperand(0);
170 Offset = LoVal.getOperand(0);
177 Offset = CurDAG->getTargetConstant(0, ValTy);
181 /// Select instructions not customized! Used for
182 /// expanded, promoted and normal instructions
183 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
184 unsigned Opcode = Node->getOpcode();
185 DebugLoc dl = Node->getDebugLoc();
187 // Dump information about the Node being selected
188 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
190 // If we have a custom node, we already have selected!
191 if (Node->isMachineOpcode()) {
192 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
197 // Instruction Selection not handled by the auto-generated
198 // tablegen selection should be handled here.
205 SDValue InFlag = Node->getOperand(2), CmpLHS;
206 unsigned Opc = InFlag.getOpcode(); (void)Opc;
207 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
208 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
209 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
212 if (Opcode == ISD::ADDE) {
213 CmpLHS = InFlag.getValue(0);
216 CmpLHS = InFlag.getOperand(0);
220 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
222 SDValue LHS = Node->getOperand(0);
223 SDValue RHS = Node->getOperand(1);
225 EVT VT = LHS.getValueType();
226 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
227 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
228 SDValue(Carry,0), RHS);
230 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
231 LHS, SDValue(AddCarry,0));
234 /// Mul with two results
236 case ISD::UMUL_LOHI: {
237 assert(Node->getValueType(0) != MVT::i64 &&
238 "64-bit multiplication with two results not handled.");
239 SDValue Op1 = Node->getOperand(0);
240 SDValue Op2 = Node->getOperand(1);
243 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
245 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
247 SDValue InFlag = SDValue(Mul, 0);
248 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
250 InFlag = SDValue(Lo,1);
251 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
253 if (!SDValue(Node, 0).use_empty())
254 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
256 if (!SDValue(Node, 1).use_empty())
257 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
264 // Mips32 has a 32-bit three operand mul instruction.
265 if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32)
269 assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) &&
270 "64-bit MULH* not handled.");
271 EVT Ty = Node->getValueType(0);
272 SDValue MulOp1 = Node->getOperand(0);
273 SDValue MulOp2 = Node->getOperand(1);
275 unsigned MulOp = (Opcode == ISD::MULHU ?
277 (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT));
278 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
279 MVT::Glue, MulOp1, MulOp2);
281 SDValue InFlag = SDValue(MulNode, 0);
283 if (Opcode == ISD::MUL) {
284 unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
285 return CurDAG->getMachineNode(Opc, dl, Ty, InFlag);
288 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
291 // Get target GOT address.
292 case ISD::GLOBAL_OFFSET_TABLE:
293 return getGlobalBaseReg();
295 case ISD::ConstantFP: {
296 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
297 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
298 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
299 Mips::ZERO, MVT::i32);
300 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
306 case MipsISD::ThreadPointer: {
307 EVT PtrVT = TLI.getPointerTy();
308 unsigned RdhwrOpc, SrcReg, DestReg;
310 if (PtrVT == MVT::i32) {
311 RdhwrOpc = Mips::RDHWR;
312 SrcReg = Mips::HWR29;
315 RdhwrOpc = Mips::RDHWR64;
316 SrcReg = Mips::HWR29_64;
317 DestReg = Mips::V1_64;
320 SDNode *Rdhwr = CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
321 Node->getValueType(0), CurDAG->getRegister(SrcReg, PtrVT));
322 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
324 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
325 ReplaceUses(SDValue(Node, 0), ResNode);
326 return ResNode.getNode();
330 // Select the default instruction
331 SDNode *ResNode = SelectCode(Node);
333 DEBUG(errs() << "=> ");
334 if (ResNode == NULL || ResNode == Node)
335 DEBUG(Node->dump(CurDAG));
337 DEBUG(ResNode->dump(CurDAG));
338 DEBUG(errs() << "\n");
342 bool MipsDAGToDAGISel::
343 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
344 std::vector<SDValue> &OutOps) {
345 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
346 OutOps.push_back(Op);
350 /// createMipsISelDag - This pass converts a legalized DAG into a
351 /// MIPS-specific DAG, ready for instruction scheduling.
352 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
353 return new MipsDAGToDAGISel(TM);