1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MCTargetDesc/MipsBaseInfo.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
69 virtual bool runOnMachineFunction(MachineFunction &MF);
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90 EVT Ty, bool HasLo, bool HasHi);
92 SDNode *Select(SDNode *N);
95 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
97 // getImm - Return a target constant with the specified value.
98 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
102 void ProcessFunctionAfterISel(MachineFunction &MF);
103 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104 void InitGlobalBaseReg(MachineFunction &MF);
106 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
108 std::vector<SDValue> &OutOps);
113 // Insert instructions to initialize the global base register in the
114 // first MBB of the function. When the ABI is O32 and the relocation model is
115 // PIC, the necessary instructions are emitted later to prevent optimization
116 // passes from moving them.
117 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
120 if (!MipsFI->globalBaseRegSet())
123 MachineBasicBlock &MBB = MF.front();
124 MachineBasicBlock::iterator I = MBB.begin();
125 MachineRegisterInfo &RegInfo = MF.getRegInfo();
126 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
127 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
128 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
129 const TargetRegisterClass *RC;
131 if (Subtarget.isABI_N64())
132 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
133 else if (Subtarget.inMips16Mode())
134 RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
136 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
138 V0 = RegInfo.createVirtualRegister(RC);
139 V1 = RegInfo.createVirtualRegister(RC);
140 V2 = RegInfo.createVirtualRegister(RC);
142 if (Subtarget.isABI_N64()) {
143 MF.getRegInfo().addLiveIn(Mips::T9_64);
144 MBB.addLiveIn(Mips::T9_64);
146 // lui $v0, %hi(%neg(%gp_rel(fname)))
147 // daddu $v1, $v0, $t9
148 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
149 const GlobalValue *FName = MF.getFunction();
150 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
151 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
152 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
153 .addReg(Mips::T9_64);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
155 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
159 if (Subtarget.inMips16Mode()) {
160 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
161 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
162 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
163 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
164 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
165 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
166 .addReg(V1).addReg(V2);
170 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
171 // Set global register to __gnu_local_gp.
173 // lui $v0, %hi(__gnu_local_gp)
174 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
175 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
176 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
177 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
178 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
182 MF.getRegInfo().addLiveIn(Mips::T9);
183 MBB.addLiveIn(Mips::T9);
185 if (Subtarget.isABI_N32()) {
186 // lui $v0, %hi(%neg(%gp_rel(fname)))
187 // addu $v1, $v0, $t9
188 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
189 const GlobalValue *FName = MF.getFunction();
190 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
191 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
192 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
193 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
194 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
198 assert(Subtarget.isABI_O32());
200 // For O32 ABI, the following instruction sequence is emitted to initialize
201 // the global base register:
203 // 0. lui $2, %hi(_gp_disp)
204 // 1. addiu $2, $2, %lo(_gp_disp)
205 // 2. addu $globalbasereg, $2, $t9
207 // We emit only the last instruction here.
209 // GNU linker requires that the first two instructions appear at the beginning
210 // of a function and no instructions be inserted before or between them.
211 // The two instructions are emitted during lowering to MC layer in order to
212 // avoid any reordering.
214 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
215 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
217 MF.getRegInfo().addLiveIn(Mips::V0);
218 MBB.addLiveIn(Mips::V0);
219 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
220 .addReg(Mips::V0).addReg(Mips::T9);
223 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
224 const MachineInstr& MI) {
225 unsigned DstReg = 0, ZeroReg = 0;
227 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
228 if ((MI.getOpcode() == Mips::ADDiu) &&
229 (MI.getOperand(1).getReg() == Mips::ZERO) &&
230 (MI.getOperand(2).getImm() == 0)) {
231 DstReg = MI.getOperand(0).getReg();
232 ZeroReg = Mips::ZERO;
233 } else if ((MI.getOpcode() == Mips::DADDiu) &&
234 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
235 (MI.getOperand(2).getImm() == 0)) {
236 DstReg = MI.getOperand(0).getReg();
237 ZeroReg = Mips::ZERO_64;
243 // Replace uses with ZeroReg.
244 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
245 E = MRI->use_end(); U != E;) {
246 MachineOperand &MO = U.getOperand();
247 unsigned OpNo = U.getOperandNo();
248 MachineInstr *MI = MO.getParent();
251 // Do not replace if it is a phi's operand or is tied to def operand.
252 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
261 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
262 InitGlobalBaseReg(MF);
264 MachineRegisterInfo *MRI = &MF.getRegInfo();
266 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
268 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
269 ReplaceUsesWithZeroReg(MRI, *I);
272 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
273 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
275 ProcessFunctionAfterISel(MF);
280 /// getGlobalBaseReg - Output the instructions required to put the
281 /// GOT address into a register.
282 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
283 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
284 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
287 /// ComplexPattern used on MipsInstrInfo
288 /// Used on Mips Load/Store instructions
289 bool MipsDAGToDAGISel::
290 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
291 EVT ValTy = Addr.getValueType();
293 // if Address is FI, get the TargetFrameIndex.
294 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
295 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
296 Offset = CurDAG->getTargetConstant(0, ValTy);
300 // on PIC code Load GA
301 if (Addr.getOpcode() == MipsISD::Wrapper) {
302 Base = Addr.getOperand(0);
303 Offset = Addr.getOperand(1);
307 if (TM.getRelocationModel() != Reloc::PIC_) {
308 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
309 Addr.getOpcode() == ISD::TargetGlobalAddress))
313 // Addresses of the form FI+const or FI|const
314 if (CurDAG->isBaseWithConstantOffset(Addr)) {
315 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
316 if (isInt<16>(CN->getSExtValue())) {
318 // If the first operand is a FI, get the TargetFI Node
319 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
320 (Addr.getOperand(0)))
321 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
323 Base = Addr.getOperand(0);
325 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
330 // Operand is a result from an ADD.
331 if (Addr.getOpcode() == ISD::ADD) {
332 // When loading from constant pools, load the lower address part in
333 // the instruction itself. Example, instead of:
334 // lui $2, %hi($CPI1_0)
335 // addiu $2, $2, %lo($CPI1_0)
338 // lui $2, %hi($CPI1_0)
339 // lwc1 $f0, %lo($CPI1_0)($2)
340 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
341 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
342 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
343 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
344 isa<JumpTableSDNode>(Opnd0)) {
345 Base = Addr.getOperand(0);
351 // If an indexed floating point load/store can be emitted, return false.
352 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
355 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
356 Subtarget.hasMips32r2Or64())
361 Offset = CurDAG->getTargetConstant(0, ValTy);
365 /// Select multiply instructions.
366 std::pair<SDNode*, SDNode*>
367 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
368 bool HasLo, bool HasHi) {
369 SDNode *Lo = 0, *Hi = 0;
370 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
372 SDValue InFlag = SDValue(Mul, 0);
375 unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mflo16 :
376 (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
377 Lo = CurDAG->getMachineNode(Opcode, dl, Ty, MVT::Glue, InFlag);
378 InFlag = SDValue(Lo, 1);
381 unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mfhi16 :
382 (Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
383 Hi = CurDAG->getMachineNode(Opcode, dl, Ty, InFlag);
385 return std::make_pair(Lo, Hi);
389 /// Select instructions not customized! Used for
390 /// expanded, promoted and normal instructions
391 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
392 unsigned Opcode = Node->getOpcode();
393 DebugLoc dl = Node->getDebugLoc();
395 // Dump information about the Node being selected
396 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
398 // If we have a custom node, we already have selected!
399 if (Node->isMachineOpcode()) {
400 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
405 // Instruction Selection not handled by the auto-generated
406 // tablegen selection should be handled here.
408 EVT NodeTy = Node->getValueType(0);
416 bool inMips16Mode = Subtarget.inMips16Mode();
417 SDValue InFlag = Node->getOperand(2), CmpLHS;
418 unsigned Opc = InFlag.getOpcode(); (void)Opc;
419 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
420 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
421 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
424 if (Opcode == ISD::ADDE) {
425 CmpLHS = InFlag.getValue(0);
427 MOp = Mips::AdduRxRyRz16;
431 CmpLHS = InFlag.getOperand(0);
433 MOp = Mips::SubuRxRyRz16;
438 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
440 SDValue LHS = Node->getOperand(0);
441 SDValue RHS = Node->getOperand(1);
443 EVT VT = LHS.getValueType();
445 unsigned Sltu_op = inMips16Mode? Mips::SltuRxRyRz16: Mips::SLTu;
446 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, dl, VT, Ops, 2);
447 unsigned Addu_op = inMips16Mode? Mips::AdduRxRyRz16 : Mips::ADDu;
448 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, dl, VT,
449 SDValue(Carry,0), RHS);
451 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
452 LHS, SDValue(AddCarry,0));
455 /// Mul with two results
457 case ISD::UMUL_LOHI: {
458 if (NodeTy == MVT::i32) {
459 if (Subtarget.inMips16Mode())
460 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 :
463 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
466 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
468 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
471 if (!SDValue(Node, 0).use_empty())
472 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
474 if (!SDValue(Node, 1).use_empty())
475 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
482 // Mips32 has a 32-bit three operand mul instruction.
483 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
485 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
486 dl, NodeTy, true, false).first;
490 if (NodeTy == MVT::i32) {
491 if (Subtarget.inMips16Mode())
492 MultOpc = (Opcode == ISD::MULHU ?
493 Mips::MultuRxRy16 : Mips::MultRxRy16);
495 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
498 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
500 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
503 // Get target GOT address.
504 case ISD::GLOBAL_OFFSET_TABLE:
505 return getGlobalBaseReg();
507 case ISD::ConstantFP: {
508 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
509 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
510 if (Subtarget.hasMips64()) {
511 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
512 Mips::ZERO_64, MVT::i64);
513 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
516 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
517 Mips::ZERO, MVT::i32);
518 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
524 case ISD::Constant: {
525 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
526 unsigned Size = CN->getValueSizeInBits(0);
531 MipsAnalyzeImmediate AnalyzeImm;
532 int64_t Imm = CN->getSExtValue();
534 const MipsAnalyzeImmediate::InstSeq &Seq =
535 AnalyzeImm.Analyze(Imm, Size, false);
537 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
538 DebugLoc DL = CN->getDebugLoc();
540 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
543 // The first instruction can be a LUi which is different from other
544 // instructions (ADDiu, ORI and SLL) in that it does not have a register
546 if (Inst->Opc == Mips::LUi64)
547 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
550 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
551 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
554 // The remaining instructions in the sequence are handled here.
555 for (++Inst; Inst != Seq.end(); ++Inst) {
556 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
558 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
559 SDValue(RegOpnd, 0), ImmOpnd);
568 assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
569 cast<MemSDNode>(Node)->getAlignment() &&
570 "Unexpected unaligned loads/stores.");
574 case MipsISD::ThreadPointer: {
575 EVT PtrVT = TLI.getPointerTy();
576 unsigned RdhwrOpc, SrcReg, DestReg;
578 if (PtrVT == MVT::i32) {
579 RdhwrOpc = Mips::RDHWR;
580 SrcReg = Mips::HWR29;
583 RdhwrOpc = Mips::RDHWR64;
584 SrcReg = Mips::HWR29_64;
585 DestReg = Mips::V1_64;
589 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
590 Node->getValueType(0),
591 CurDAG->getRegister(SrcReg, PtrVT));
592 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
594 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
595 ReplaceUses(SDValue(Node, 0), ResNode);
596 return ResNode.getNode();
600 // Select the default instruction
601 SDNode *ResNode = SelectCode(Node);
603 DEBUG(errs() << "=> ");
604 if (ResNode == NULL || ResNode == Node)
605 DEBUG(Node->dump(CurDAG));
607 DEBUG(ResNode->dump(CurDAG));
608 DEBUG(errs() << "\n");
612 bool MipsDAGToDAGISel::
613 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
614 std::vector<SDValue> &OutOps) {
615 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
616 OutOps.push_back(Op);
620 /// createMipsISelDag - This pass converts a legalized DAG into a
621 /// MIPS-specific DAG, ready for instruction scheduling.
622 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
623 return new MipsDAGToDAGISel(TM);