1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 SDNode *SelectLoadFp64(SDNode *N);
90 SDNode *SelectStoreFp64(SDNode *N);
92 // getI32Imm - Return a target constant with the specified
93 // value, of type i32.
94 inline SDValue getI32Imm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113 // if Address is FI, get the TargetFrameIndex.
114 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
120 // on PIC code Load GA
121 if (TM.getRelocationModel() == Reloc::PIC_) {
122 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
123 (Addr.getOpcode() == ISD::TargetConstantPool) ||
124 (Addr.getOpcode() == ISD::TargetJumpTable) ||
125 (Addr.getOpcode() == ISD::TargetBlockAddress)) {
126 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
131 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress))
136 // Operand is a result from an ADD.
137 if (Addr.getOpcode() == ISD::ADD) {
138 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
139 if (isInt<16>(CN->getSExtValue())) {
141 // If the first operand is a FI, get the TargetFI Node
142 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
143 (Addr.getOperand(0))) {
144 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
146 Base = Addr.getOperand(0);
149 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
154 // When loading from constant pools, load the lower address part in
155 // the instruction itself. Example, instead of:
156 // lui $2, %hi($CPI1_0)
157 // addiu $2, $2, %lo($CPI1_0)
160 // lui $2, %hi($CPI1_0)
161 // lwc1 $f0, %lo($CPI1_0)($2)
162 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
163 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
164 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
165 SDValue LoVal = Addr.getOperand(1);
166 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
167 Base = Addr.getOperand(0);
168 Offset = LoVal.getOperand(0);
175 Offset = CurDAG->getTargetConstant(0, MVT::i32);
179 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
180 MVT::SimpleValueType NVT =
181 N->getValueType(0).getSimpleVT().SimpleTy;
183 if (!Subtarget.isMips1() || NVT != MVT::f64)
186 LoadSDNode *LN = cast<LoadSDNode>(N);
187 if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
188 LN->getAddressingMode() != ISD::UNINDEXED)
191 SDValue Chain = N->getOperand(0);
192 SDValue N1 = N->getOperand(1);
193 SDValue Offset0, Offset1, Base;
195 if (!SelectAddr(N1, Offset0, Base) ||
196 N1.getValueType() != MVT::i32)
199 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
200 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
201 DebugLoc dl = N->getDebugLoc();
203 // The second load should start after for 4 bytes.
204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
205 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
206 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
207 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
211 CP->getTargetFlags());
215 // Choose the offsets depending on the endianess
216 if (TM.getTargetData()->isBigEndian())
217 std::swap(Offset0, Offset1);
224 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
225 MVT::Other, Offset0, Base, Chain);
226 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
228 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
229 MVT::f64, Undef, SDValue(LD0, 0));
231 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
232 MVT::Other, Offset1, Base, SDValue(LD0, 1));
233 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
234 MVT::f64, I0, SDValue(LD1, 0));
236 ReplaceUses(SDValue(N, 0), I1);
237 ReplaceUses(SDValue(N, 1), Chain);
238 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
239 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
243 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
245 if (!Subtarget.isMips1() ||
246 N->getOperand(1).getValueType() != MVT::f64)
249 SDValue Chain = N->getOperand(0);
251 StoreSDNode *SN = cast<StoreSDNode>(N);
252 if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
255 SDValue N1 = N->getOperand(1);
256 SDValue N2 = N->getOperand(2);
257 SDValue Offset0, Offset1, Base;
259 if (!SelectAddr(N2, Offset0, Base) ||
260 N1.getValueType() != MVT::f64 ||
261 N2.getValueType() != MVT::i32)
264 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
265 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
266 DebugLoc dl = N->getDebugLoc();
268 // Get the even and odd part from the f64 register
269 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
271 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
274 // The second store should start after for 4 bytes.
275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
276 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
280 // Choose the offsets depending on the endianess
281 if (TM.getTargetData()->isBigEndian())
282 std::swap(Offset0, Offset1);
289 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
290 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
291 MVT::Other, Ops0, 4), 0);
292 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
294 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
295 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
296 MVT::Other, Ops1, 4), 0);
297 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
299 ReplaceUses(SDValue(N, 0), Chain);
300 return Chain.getNode();
303 /// Select instructions not customized! Used for
304 /// expanded, promoted and normal instructions
305 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
306 unsigned Opcode = Node->getOpcode();
307 DebugLoc dl = Node->getDebugLoc();
309 // Dump information about the Node being selected
310 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
312 // If we have a custom node, we already have selected!
313 if (Node->isMachineOpcode()) {
314 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
319 // Instruction Selection not handled by the auto-generated
320 // tablegen selection should be handled here.
328 SDValue InFlag = Node->getOperand(2), CmpLHS;
329 unsigned Opc = InFlag.getOpcode(); (void)Opc;
330 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
331 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
332 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
335 if (Opcode == ISD::ADDE) {
336 CmpLHS = InFlag.getValue(0);
339 CmpLHS = InFlag.getOperand(0);
343 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
345 SDValue LHS = Node->getOperand(0);
346 SDValue RHS = Node->getOperand(1);
348 EVT VT = LHS.getValueType();
349 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
350 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
351 SDValue(Carry,0), RHS);
353 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
354 LHS, SDValue(AddCarry,0));
357 /// Mul/Div with two results
362 case ISD::UMUL_LOHI: {
363 SDValue Op1 = Node->getOperand(0);
364 SDValue Op2 = Node->getOperand(1);
367 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
369 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
371 SDValue InFlag = SDValue(Mul, 0);
372 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
374 InFlag = SDValue(Lo,1);
375 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
377 if (!SDValue(Node, 0).use_empty())
378 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
380 if (!SDValue(Node, 1).use_empty())
381 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
388 if (Subtarget.isMips32())
392 SDValue MulOp1 = Node->getOperand(0);
393 SDValue MulOp2 = Node->getOperand(1);
395 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
396 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
397 MVT::Glue, MulOp1, MulOp2);
399 SDValue InFlag = SDValue(MulNode, 0);
401 if (Opcode == ISD::MUL)
402 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
404 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
407 /// Div/Rem operations
414 // Get target GOT address.
415 case ISD::GLOBAL_OFFSET_TABLE:
416 return getGlobalBaseReg();
418 case ISD::ConstantFP: {
419 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
420 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
421 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
422 Mips::ZERO, MVT::i32);
423 SDValue Undef = SDValue(
424 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
425 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
426 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
427 MVT::f64, Undef, SDValue(MTC, 0));
428 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
429 MVT::f64, I0, SDValue(MTC, 0));
430 ReplaceUses(SDValue(Node, 0), I1);
437 if (SDNode *ResNode = SelectLoadFp64(Node))
439 // Other cases are autogenerated.
443 if (SDNode *ResNode = SelectStoreFp64(Node))
445 // Other cases are autogenerated.
448 /// Handle direct and indirect calls when using PIC. On PIC, when
449 /// GOT is smaller than about 64k (small code) the GA target is
450 /// loaded with only one instruction. Otherwise GA's target must
451 /// be loaded with 3 instructions.
452 case MipsISD::JmpLink: {
453 if (TM.getRelocationModel() == Reloc::PIC_) {
454 unsigned LastOpNum = Node->getNumOperands()-1;
456 SDValue Chain = Node->getOperand(0);
457 SDValue Callee = Node->getOperand(1);
460 // Skip the incomming flag if present
461 if (Node->getOperand(LastOpNum).getValueType() == MVT::Glue)
464 if ( (isa<GlobalAddressSDNode>(Callee)) ||
465 (isa<ExternalSymbolSDNode>(Callee)) )
467 /// Direct call for global addresses and external symbols
468 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
470 // Use load to get GOT target
471 SDValue Ops[] = { Callee, GPReg, Chain };
472 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
473 MVT::Other, Ops, 3), 0);
474 Chain = Load.getValue(1);
476 // Call target must be on T9
477 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
480 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
482 // Map the JmpLink operands to JALR
483 SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Glue);
484 SmallVector<SDValue, 8> Ops;
485 Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
487 for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
488 Ops.push_back(Node->getOperand(i));
489 Ops.push_back(Chain);
490 Ops.push_back(Chain.getValue(1));
492 // Emit Jump and Link Register
493 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
494 &Ops[0], Ops.size());
496 // Replace Chain and InFlag
497 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
498 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
504 // Select the default instruction
505 SDNode *ResNode = SelectCode(Node);
507 DEBUG(errs() << "=> ");
508 if (ResNode == NULL || ResNode == Node)
509 DEBUG(Node->dump(CurDAG));
511 DEBUG(ResNode->dump(CurDAG));
512 DEBUG(errs() << "\n");
516 /// createMipsISelDag - This pass converts a legalized DAG into a
517 /// MIPS-specific DAG, ready for instruction scheduling.
518 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
519 return new MipsDAGToDAGISel(TM);