1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NumTailCalls, "Number of tail calls");
44 LargeGOT("mxgot", cl::Hidden,
45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
48 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
49 cl::desc("MIPS: Don't trap on integer division by zero."),
52 static const uint16_t O32IntRegs[4] = {
53 Mips::A0, Mips::A1, Mips::A2, Mips::A3
56 static const uint16_t Mips64IntRegs[8] = {
57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
61 static const uint16_t Mips64DPRegs[8] = {
62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
66 // If I is a shifted mask, set the size (Size) and the first bit of the
67 // mask (Pos), and return true.
68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70 if (!isShiftedMask_64(I))
73 Size = CountPopulation_64(I);
74 Pos = countTrailingZeros(I);
78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
83 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
85 unsigned Flag) const {
86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
89 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
91 unsigned Flag) const {
92 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
95 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
97 unsigned Flag) const {
98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
101 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
103 unsigned Flag) const {
104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
107 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
109 unsigned Flag) const {
110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111 N->getOffset(), Flag);
114 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
116 case MipsISD::JmpLink: return "MipsISD::JmpLink";
117 case MipsISD::TailCall: return "MipsISD::TailCall";
118 case MipsISD::Hi: return "MipsISD::Hi";
119 case MipsISD::Lo: return "MipsISD::Lo";
120 case MipsISD::GPRel: return "MipsISD::GPRel";
121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
122 case MipsISD::Ret: return "MipsISD::Ret";
123 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
124 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
125 case MipsISD::FPCmp: return "MipsISD::FPCmp";
126 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
127 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
128 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
129 case MipsISD::MFHI: return "MipsISD::MFHI";
130 case MipsISD::MFLO: return "MipsISD::MFLO";
131 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
132 case MipsISD::Mult: return "MipsISD::Mult";
133 case MipsISD::Multu: return "MipsISD::Multu";
134 case MipsISD::MAdd: return "MipsISD::MAdd";
135 case MipsISD::MAddu: return "MipsISD::MAddu";
136 case MipsISD::MSub: return "MipsISD::MSub";
137 case MipsISD::MSubu: return "MipsISD::MSubu";
138 case MipsISD::DivRem: return "MipsISD::DivRem";
139 case MipsISD::DivRemU: return "MipsISD::DivRemU";
140 case MipsISD::DivRem16: return "MipsISD::DivRem16";
141 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
142 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
143 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
144 case MipsISD::Wrapper: return "MipsISD::Wrapper";
145 case MipsISD::Sync: return "MipsISD::Sync";
146 case MipsISD::Ext: return "MipsISD::Ext";
147 case MipsISD::Ins: return "MipsISD::Ins";
148 case MipsISD::LWL: return "MipsISD::LWL";
149 case MipsISD::LWR: return "MipsISD::LWR";
150 case MipsISD::SWL: return "MipsISD::SWL";
151 case MipsISD::SWR: return "MipsISD::SWR";
152 case MipsISD::LDL: return "MipsISD::LDL";
153 case MipsISD::LDR: return "MipsISD::LDR";
154 case MipsISD::SDL: return "MipsISD::SDL";
155 case MipsISD::SDR: return "MipsISD::SDR";
156 case MipsISD::EXTP: return "MipsISD::EXTP";
157 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
158 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
159 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
160 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
161 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
162 case MipsISD::SHILO: return "MipsISD::SHILO";
163 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
164 case MipsISD::MULT: return "MipsISD::MULT";
165 case MipsISD::MULTU: return "MipsISD::MULTU";
166 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
167 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
168 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
169 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
170 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
171 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
172 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
173 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
174 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
175 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
176 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
177 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
178 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
179 case MipsISD::VCEQ: return "MipsISD::VCEQ";
180 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
181 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
182 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
183 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
184 case MipsISD::VSMAX: return "MipsISD::VSMAX";
185 case MipsISD::VSMIN: return "MipsISD::VSMIN";
186 case MipsISD::VUMAX: return "MipsISD::VUMAX";
187 case MipsISD::VUMIN: return "MipsISD::VUMIN";
188 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
189 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
190 case MipsISD::VNOR: return "MipsISD::VNOR";
191 case MipsISD::VSHF: return "MipsISD::VSHF";
192 case MipsISD::SHF: return "MipsISD::SHF";
193 case MipsISD::ILVEV: return "MipsISD::ILVEV";
194 case MipsISD::ILVOD: return "MipsISD::ILVOD";
195 case MipsISD::ILVL: return "MipsISD::ILVL";
196 case MipsISD::ILVR: return "MipsISD::ILVR";
197 case MipsISD::PCKEV: return "MipsISD::PCKEV";
198 case MipsISD::PCKOD: return "MipsISD::PCKOD";
199 default: return NULL;
204 MipsTargetLowering(MipsTargetMachine &TM)
205 : TargetLowering(TM, new MipsTargetObjectFile()),
206 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
207 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
208 IsO32(Subtarget->isABI_O32()) {
209 // Mips does not have i1 type, so use i32 for
210 // setcc operations results (slt, sgt, ...).
211 setBooleanContents(ZeroOrOneBooleanContent);
212 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
214 // Load extented operations for i1 types must be promoted
215 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
216 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
217 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
219 // MIPS doesn't have extending float->double load/store
220 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
221 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
223 // Used by legalize types to correctly generate the setcc result.
224 // Without this, every float setcc comes with a AND/OR with the result,
225 // we don't want this, since the fpcmp result goes to a flag register,
226 // which is used implicitly by brcond and select operations.
227 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
229 // Mips Custom Operations
230 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
231 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
232 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
233 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
234 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
235 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
236 setOperationAction(ISD::SELECT, MVT::f32, Custom);
237 setOperationAction(ISD::SELECT, MVT::f64, Custom);
238 setOperationAction(ISD::SELECT, MVT::i32, Custom);
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
241 setOperationAction(ISD::SETCC, MVT::f32, Custom);
242 setOperationAction(ISD::SETCC, MVT::f64, Custom);
243 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
244 setOperationAction(ISD::VASTART, MVT::Other, Custom);
245 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
246 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
247 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
249 if (!TM.Options.NoNaNsFPMath) {
250 setOperationAction(ISD::FABS, MVT::f32, Custom);
251 setOperationAction(ISD::FABS, MVT::f64, Custom);
255 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
256 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
257 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
258 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
259 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
260 setOperationAction(ISD::SELECT, MVT::i64, Custom);
261 setOperationAction(ISD::LOAD, MVT::i64, Custom);
262 setOperationAction(ISD::STORE, MVT::i64, Custom);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
267 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
268 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
269 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
272 setOperationAction(ISD::ADD, MVT::i32, Custom);
274 setOperationAction(ISD::ADD, MVT::i64, Custom);
276 setOperationAction(ISD::SDIV, MVT::i32, Expand);
277 setOperationAction(ISD::SREM, MVT::i32, Expand);
278 setOperationAction(ISD::UDIV, MVT::i32, Expand);
279 setOperationAction(ISD::UREM, MVT::i32, Expand);
280 setOperationAction(ISD::SDIV, MVT::i64, Expand);
281 setOperationAction(ISD::SREM, MVT::i64, Expand);
282 setOperationAction(ISD::UDIV, MVT::i64, Expand);
283 setOperationAction(ISD::UREM, MVT::i64, Expand);
285 // Operations not directly supported by Mips.
286 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
287 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
288 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
289 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
290 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
291 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
292 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
293 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
294 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
296 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
297 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
298 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
299 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
300 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
301 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
302 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
303 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
304 setOperationAction(ISD::ROTL, MVT::i32, Expand);
305 setOperationAction(ISD::ROTL, MVT::i64, Expand);
306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
307 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
309 if (!Subtarget->hasMips32r2())
310 setOperationAction(ISD::ROTR, MVT::i32, Expand);
312 if (!Subtarget->hasMips64r2())
313 setOperationAction(ISD::ROTR, MVT::i64, Expand);
315 setOperationAction(ISD::FSIN, MVT::f32, Expand);
316 setOperationAction(ISD::FSIN, MVT::f64, Expand);
317 setOperationAction(ISD::FCOS, MVT::f32, Expand);
318 setOperationAction(ISD::FCOS, MVT::f64, Expand);
319 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
320 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
321 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
322 setOperationAction(ISD::FPOW, MVT::f32, Expand);
323 setOperationAction(ISD::FPOW, MVT::f64, Expand);
324 setOperationAction(ISD::FLOG, MVT::f32, Expand);
325 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
326 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
327 setOperationAction(ISD::FEXP, MVT::f32, Expand);
328 setOperationAction(ISD::FMA, MVT::f32, Expand);
329 setOperationAction(ISD::FMA, MVT::f64, Expand);
330 setOperationAction(ISD::FREM, MVT::f32, Expand);
331 setOperationAction(ISD::FREM, MVT::f64, Expand);
333 if (!TM.Options.NoNaNsFPMath) {
334 setOperationAction(ISD::FNEG, MVT::f32, Expand);
335 setOperationAction(ISD::FNEG, MVT::f64, Expand);
338 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
340 setOperationAction(ISD::VAARG, MVT::Other, Expand);
341 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
342 setOperationAction(ISD::VAEND, MVT::Other, Expand);
344 // Use the default for now
345 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
346 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
348 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
349 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
350 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
351 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
353 setInsertFencesForAtomic(true);
355 if (!Subtarget->hasSEInReg()) {
356 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
360 if (!Subtarget->hasBitCount()) {
361 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
362 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
365 if (!Subtarget->hasSwap()) {
366 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
367 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
371 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
372 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
373 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
374 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
377 setOperationAction(ISD::TRAP, MVT::Other, Legal);
379 setTargetDAGCombine(ISD::SDIVREM);
380 setTargetDAGCombine(ISD::UDIVREM);
381 setTargetDAGCombine(ISD::SELECT);
382 setTargetDAGCombine(ISD::AND);
383 setTargetDAGCombine(ISD::OR);
384 setTargetDAGCombine(ISD::ADD);
386 setMinFunctionAlignment(HasMips64 ? 3 : 2);
388 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
390 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
391 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
393 MaxStoresPerMemcpy = 16;
396 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
397 if (TM.getSubtargetImpl()->inMips16Mode())
398 return llvm::createMips16TargetLowering(TM);
400 return llvm::createMipsSETargetLowering(TM);
403 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
406 return VT.changeVectorElementTypeToInteger();
409 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
410 TargetLowering::DAGCombinerInfo &DCI,
411 const MipsSubtarget *Subtarget) {
412 if (DCI.isBeforeLegalizeOps())
415 EVT Ty = N->getValueType(0);
416 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
417 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
418 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
422 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
423 N->getOperand(0), N->getOperand(1));
424 SDValue InChain = DAG.getEntryNode();
425 SDValue InGlue = DivRem;
428 if (N->hasAnyUseOfValue(0)) {
429 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
431 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
432 InChain = CopyFromLo.getValue(1);
433 InGlue = CopyFromLo.getValue(2);
437 if (N->hasAnyUseOfValue(1)) {
438 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
440 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
446 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
448 default: llvm_unreachable("Unknown fp condition code!");
450 case ISD::SETOEQ: return Mips::FCOND_OEQ;
451 case ISD::SETUNE: return Mips::FCOND_UNE;
453 case ISD::SETOLT: return Mips::FCOND_OLT;
455 case ISD::SETOGT: return Mips::FCOND_OGT;
457 case ISD::SETOLE: return Mips::FCOND_OLE;
459 case ISD::SETOGE: return Mips::FCOND_OGE;
460 case ISD::SETULT: return Mips::FCOND_ULT;
461 case ISD::SETULE: return Mips::FCOND_ULE;
462 case ISD::SETUGT: return Mips::FCOND_UGT;
463 case ISD::SETUGE: return Mips::FCOND_UGE;
464 case ISD::SETUO: return Mips::FCOND_UN;
465 case ISD::SETO: return Mips::FCOND_OR;
467 case ISD::SETONE: return Mips::FCOND_ONE;
468 case ISD::SETUEQ: return Mips::FCOND_UEQ;
473 /// This function returns true if the floating point conditional branches and
474 /// conditional moves which use condition code CC should be inverted.
475 static bool invertFPCondCodeUser(Mips::CondCode CC) {
476 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
479 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
480 "Illegal Condition Code");
485 // Creates and returns an FPCmp node from a setcc node.
486 // Returns Op if setcc is not a floating point comparison.
487 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
488 // must be a SETCC node
489 if (Op.getOpcode() != ISD::SETCC)
492 SDValue LHS = Op.getOperand(0);
494 if (!LHS.getValueType().isFloatingPoint())
497 SDValue RHS = Op.getOperand(1);
500 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
501 // node if necessary.
502 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
504 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
505 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
508 // Creates and returns a CMovFPT/F node.
509 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
510 SDValue False, SDLoc DL) {
511 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
512 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
513 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
515 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
516 True.getValueType(), True, FCC0, False, Cond);
519 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
520 TargetLowering::DAGCombinerInfo &DCI,
521 const MipsSubtarget *Subtarget) {
522 if (DCI.isBeforeLegalizeOps())
525 SDValue SetCC = N->getOperand(0);
527 if ((SetCC.getOpcode() != ISD::SETCC) ||
528 !SetCC.getOperand(0).getValueType().isInteger())
531 SDValue False = N->getOperand(2);
532 EVT FalseTy = False.getValueType();
534 if (!FalseTy.isInteger())
537 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
539 if (!CN || CN->getZExtValue())
543 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
544 SDValue True = N->getOperand(1);
546 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
547 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
549 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
552 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
553 TargetLowering::DAGCombinerInfo &DCI,
554 const MipsSubtarget *Subtarget) {
555 // Pattern match EXT.
556 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
557 // => ext $dst, $src, size, pos
558 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
561 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
562 unsigned ShiftRightOpc = ShiftRight.getOpcode();
564 // Op's first operand must be a shift right.
565 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
568 // The second operand of the shift must be an immediate.
570 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
573 uint64_t Pos = CN->getZExtValue();
574 uint64_t SMPos, SMSize;
576 // Op's second operand must be a shifted mask.
577 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
578 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
581 // Return if the shifted mask does not start at bit 0 or the sum of its size
582 // and Pos exceeds the word's size.
583 EVT ValTy = N->getValueType(0);
584 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
587 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
588 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
589 DAG.getConstant(SMSize, MVT::i32));
592 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
593 TargetLowering::DAGCombinerInfo &DCI,
594 const MipsSubtarget *Subtarget) {
595 // Pattern match INS.
596 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
597 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
598 // => ins $dst, $src, size, pos, $src1
599 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
602 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
603 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
606 // See if Op's first operand matches (and $src1 , mask0).
607 if (And0.getOpcode() != ISD::AND)
610 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
611 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
614 // See if Op's second operand matches (and (shl $src, pos), mask1).
615 if (And1.getOpcode() != ISD::AND)
618 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
619 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
622 // The shift masks must have the same position and size.
623 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
626 SDValue Shl = And1.getOperand(0);
627 if (Shl.getOpcode() != ISD::SHL)
630 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
633 unsigned Shamt = CN->getZExtValue();
635 // Return if the shift amount and the first bit position of mask are not the
637 EVT ValTy = N->getValueType(0);
638 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
641 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
642 DAG.getConstant(SMPos0, MVT::i32),
643 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
646 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
647 TargetLowering::DAGCombinerInfo &DCI,
648 const MipsSubtarget *Subtarget) {
649 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
651 if (DCI.isBeforeLegalizeOps())
654 SDValue Add = N->getOperand(1);
656 if (Add.getOpcode() != ISD::ADD)
659 SDValue Lo = Add.getOperand(1);
661 if ((Lo.getOpcode() != MipsISD::Lo) ||
662 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
665 EVT ValTy = N->getValueType(0);
668 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
670 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
673 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
675 SelectionDAG &DAG = DCI.DAG;
676 unsigned Opc = N->getOpcode();
682 return performDivRemCombine(N, DAG, DCI, Subtarget);
684 return performSELECTCombine(N, DAG, DCI, Subtarget);
686 return performANDCombine(N, DAG, DCI, Subtarget);
688 return performORCombine(N, DAG, DCI, Subtarget);
690 return performADDCombine(N, DAG, DCI, Subtarget);
697 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
698 SmallVectorImpl<SDValue> &Results,
699 SelectionDAG &DAG) const {
700 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
702 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
703 Results.push_back(Res.getValue(I));
707 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
708 SmallVectorImpl<SDValue> &Results,
709 SelectionDAG &DAG) const {
710 return LowerOperationWrapper(N, Results, DAG);
713 SDValue MipsTargetLowering::
714 LowerOperation(SDValue Op, SelectionDAG &DAG) const
716 switch (Op.getOpcode())
718 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
719 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
720 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
721 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
722 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
723 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
724 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
725 case ISD::SELECT: return lowerSELECT(Op, DAG);
726 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
727 case ISD::SETCC: return lowerSETCC(Op, DAG);
728 case ISD::VASTART: return lowerVASTART(Op, DAG);
729 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
730 case ISD::FABS: return lowerFABS(Op, DAG);
731 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
732 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
733 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
734 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
735 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
736 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
737 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
738 case ISD::LOAD: return lowerLOAD(Op, DAG);
739 case ISD::STORE: return lowerSTORE(Op, DAG);
740 case ISD::ADD: return lowerADD(Op, DAG);
741 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
746 //===----------------------------------------------------------------------===//
747 // Lower helper functions
748 //===----------------------------------------------------------------------===//
750 // addLiveIn - This helper function adds the specified physical register to the
751 // MachineFunction as a live in value. It also creates a corresponding
752 // virtual register for it.
754 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
756 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
757 MF.getRegInfo().addLiveIn(PReg, VReg);
761 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
762 MachineBasicBlock &MBB,
763 const TargetInstrInfo &TII,
768 // Insert instruction "teq $divisor_reg, $zero, 7".
769 MachineBasicBlock::iterator I(MI);
770 MachineInstrBuilder MIB;
771 MachineOperand &Divisor = MI->getOperand(2);
772 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
773 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
774 .addReg(Mips::ZERO).addImm(7);
776 // Use the 32-bit sub-register if this is a 64-bit division.
778 MIB->getOperand(0).setSubReg(Mips::sub_32);
780 // Clear Divisor's kill flag.
781 Divisor.setIsKill(false);
786 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
787 MachineBasicBlock *BB) const {
788 switch (MI->getOpcode()) {
790 llvm_unreachable("Unexpected instr type to insert");
791 case Mips::ATOMIC_LOAD_ADD_I8:
792 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
793 case Mips::ATOMIC_LOAD_ADD_I16:
794 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
795 case Mips::ATOMIC_LOAD_ADD_I32:
796 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
797 case Mips::ATOMIC_LOAD_ADD_I64:
798 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
800 case Mips::ATOMIC_LOAD_AND_I8:
801 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
802 case Mips::ATOMIC_LOAD_AND_I16:
803 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
804 case Mips::ATOMIC_LOAD_AND_I32:
805 return emitAtomicBinary(MI, BB, 4, Mips::AND);
806 case Mips::ATOMIC_LOAD_AND_I64:
807 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
809 case Mips::ATOMIC_LOAD_OR_I8:
810 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
811 case Mips::ATOMIC_LOAD_OR_I16:
812 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
813 case Mips::ATOMIC_LOAD_OR_I32:
814 return emitAtomicBinary(MI, BB, 4, Mips::OR);
815 case Mips::ATOMIC_LOAD_OR_I64:
816 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
818 case Mips::ATOMIC_LOAD_XOR_I8:
819 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
820 case Mips::ATOMIC_LOAD_XOR_I16:
821 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
822 case Mips::ATOMIC_LOAD_XOR_I32:
823 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
824 case Mips::ATOMIC_LOAD_XOR_I64:
825 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
827 case Mips::ATOMIC_LOAD_NAND_I8:
828 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
829 case Mips::ATOMIC_LOAD_NAND_I16:
830 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
831 case Mips::ATOMIC_LOAD_NAND_I32:
832 return emitAtomicBinary(MI, BB, 4, 0, true);
833 case Mips::ATOMIC_LOAD_NAND_I64:
834 return emitAtomicBinary(MI, BB, 8, 0, true);
836 case Mips::ATOMIC_LOAD_SUB_I8:
837 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
838 case Mips::ATOMIC_LOAD_SUB_I16:
839 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
840 case Mips::ATOMIC_LOAD_SUB_I32:
841 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
842 case Mips::ATOMIC_LOAD_SUB_I64:
843 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
845 case Mips::ATOMIC_SWAP_I8:
846 return emitAtomicBinaryPartword(MI, BB, 1, 0);
847 case Mips::ATOMIC_SWAP_I16:
848 return emitAtomicBinaryPartword(MI, BB, 2, 0);
849 case Mips::ATOMIC_SWAP_I32:
850 return emitAtomicBinary(MI, BB, 4, 0);
851 case Mips::ATOMIC_SWAP_I64:
852 return emitAtomicBinary(MI, BB, 8, 0);
854 case Mips::ATOMIC_CMP_SWAP_I8:
855 return emitAtomicCmpSwapPartword(MI, BB, 1);
856 case Mips::ATOMIC_CMP_SWAP_I16:
857 return emitAtomicCmpSwapPartword(MI, BB, 2);
858 case Mips::ATOMIC_CMP_SWAP_I32:
859 return emitAtomicCmpSwap(MI, BB, 4);
860 case Mips::ATOMIC_CMP_SWAP_I64:
861 return emitAtomicCmpSwap(MI, BB, 8);
862 case Mips::PseudoSDIV:
863 case Mips::PseudoUDIV:
864 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
865 case Mips::PseudoDSDIV:
866 case Mips::PseudoDUDIV:
867 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
871 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
872 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
874 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
875 unsigned Size, unsigned BinOpcode,
877 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
879 MachineFunction *MF = BB->getParent();
880 MachineRegisterInfo &RegInfo = MF->getRegInfo();
881 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
883 DebugLoc DL = MI->getDebugLoc();
884 unsigned LL, SC, AND, NOR, ZERO, BEQ;
899 ZERO = Mips::ZERO_64;
903 unsigned OldVal = MI->getOperand(0).getReg();
904 unsigned Ptr = MI->getOperand(1).getReg();
905 unsigned Incr = MI->getOperand(2).getReg();
907 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
908 unsigned AndRes = RegInfo.createVirtualRegister(RC);
909 unsigned Success = RegInfo.createVirtualRegister(RC);
911 // insert new blocks after the current block
912 const BasicBlock *LLVM_BB = BB->getBasicBlock();
913 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
914 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
915 MachineFunction::iterator It = BB;
917 MF->insert(It, loopMBB);
918 MF->insert(It, exitMBB);
920 // Transfer the remainder of BB and its successor edges to exitMBB.
921 exitMBB->splice(exitMBB->begin(), BB,
922 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
923 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
927 // fallthrough --> loopMBB
928 BB->addSuccessor(loopMBB);
929 loopMBB->addSuccessor(loopMBB);
930 loopMBB->addSuccessor(exitMBB);
934 // <binop> storeval, oldval, incr
935 // sc success, storeval, 0(ptr)
936 // beq success, $0, loopMBB
938 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
940 // and andres, oldval, incr
941 // nor storeval, $0, andres
942 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
943 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
944 } else if (BinOpcode) {
945 // <binop> storeval, oldval, incr
946 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
950 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
951 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
953 MI->eraseFromParent(); // The instruction is gone now.
959 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
960 MachineBasicBlock *BB,
961 unsigned Size, unsigned BinOpcode,
963 assert((Size == 1 || Size == 2) &&
964 "Unsupported size for EmitAtomicBinaryPartial.");
966 MachineFunction *MF = BB->getParent();
967 MachineRegisterInfo &RegInfo = MF->getRegInfo();
968 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
969 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
970 DebugLoc DL = MI->getDebugLoc();
972 unsigned Dest = MI->getOperand(0).getReg();
973 unsigned Ptr = MI->getOperand(1).getReg();
974 unsigned Incr = MI->getOperand(2).getReg();
976 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
977 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
978 unsigned Mask = RegInfo.createVirtualRegister(RC);
979 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
980 unsigned NewVal = RegInfo.createVirtualRegister(RC);
981 unsigned OldVal = RegInfo.createVirtualRegister(RC);
982 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
983 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
984 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
985 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
986 unsigned AndRes = RegInfo.createVirtualRegister(RC);
987 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
988 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
989 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
990 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
991 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
992 unsigned SllRes = RegInfo.createVirtualRegister(RC);
993 unsigned Success = RegInfo.createVirtualRegister(RC);
995 // insert new blocks after the current block
996 const BasicBlock *LLVM_BB = BB->getBasicBlock();
997 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
998 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
999 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1000 MachineFunction::iterator It = BB;
1002 MF->insert(It, loopMBB);
1003 MF->insert(It, sinkMBB);
1004 MF->insert(It, exitMBB);
1006 // Transfer the remainder of BB and its successor edges to exitMBB.
1007 exitMBB->splice(exitMBB->begin(), BB,
1008 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1009 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1011 BB->addSuccessor(loopMBB);
1012 loopMBB->addSuccessor(loopMBB);
1013 loopMBB->addSuccessor(sinkMBB);
1014 sinkMBB->addSuccessor(exitMBB);
1017 // addiu masklsb2,$0,-4 # 0xfffffffc
1018 // and alignedaddr,ptr,masklsb2
1019 // andi ptrlsb2,ptr,3
1020 // sll shiftamt,ptrlsb2,3
1021 // ori maskupper,$0,255 # 0xff
1022 // sll mask,maskupper,shiftamt
1023 // nor mask2,$0,mask
1024 // sll incr2,incr,shiftamt
1026 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1027 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1028 .addReg(Mips::ZERO).addImm(-4);
1029 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1030 .addReg(Ptr).addReg(MaskLSB2);
1031 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1032 if (Subtarget->isLittle()) {
1033 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1035 unsigned Off = RegInfo.createVirtualRegister(RC);
1036 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1037 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1038 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1040 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1041 .addReg(Mips::ZERO).addImm(MaskImm);
1042 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1043 .addReg(MaskUpper).addReg(ShiftAmt);
1044 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1045 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1047 // atomic.load.binop
1049 // ll oldval,0(alignedaddr)
1050 // binop binopres,oldval,incr2
1051 // and newval,binopres,mask
1052 // and maskedoldval0,oldval,mask2
1053 // or storeval,maskedoldval0,newval
1054 // sc success,storeval,0(alignedaddr)
1055 // beq success,$0,loopMBB
1059 // ll oldval,0(alignedaddr)
1060 // and newval,incr2,mask
1061 // and maskedoldval0,oldval,mask2
1062 // or storeval,maskedoldval0,newval
1063 // sc success,storeval,0(alignedaddr)
1064 // beq success,$0,loopMBB
1067 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1069 // and andres, oldval, incr2
1070 // nor binopres, $0, andres
1071 // and newval, binopres, mask
1072 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1073 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1074 .addReg(Mips::ZERO).addReg(AndRes);
1075 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1076 } else if (BinOpcode) {
1077 // <binop> binopres, oldval, incr2
1078 // and newval, binopres, mask
1079 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1080 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1081 } else { // atomic.swap
1082 // and newval, incr2, mask
1083 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1086 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1087 .addReg(OldVal).addReg(Mask2);
1088 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1089 .addReg(MaskedOldVal0).addReg(NewVal);
1090 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1091 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1092 BuildMI(BB, DL, TII->get(Mips::BEQ))
1093 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1096 // and maskedoldval1,oldval,mask
1097 // srl srlres,maskedoldval1,shiftamt
1098 // sll sllres,srlres,24
1099 // sra dest,sllres,24
1101 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1103 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1104 .addReg(OldVal).addReg(Mask);
1105 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1106 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1107 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1108 .addReg(SrlRes).addImm(ShiftImm);
1109 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1110 .addReg(SllRes).addImm(ShiftImm);
1112 MI->eraseFromParent(); // The instruction is gone now.
1117 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1118 MachineBasicBlock *BB,
1119 unsigned Size) const {
1120 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1122 MachineFunction *MF = BB->getParent();
1123 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1124 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1126 DebugLoc DL = MI->getDebugLoc();
1127 unsigned LL, SC, ZERO, BNE, BEQ;
1138 ZERO = Mips::ZERO_64;
1143 unsigned Dest = MI->getOperand(0).getReg();
1144 unsigned Ptr = MI->getOperand(1).getReg();
1145 unsigned OldVal = MI->getOperand(2).getReg();
1146 unsigned NewVal = MI->getOperand(3).getReg();
1148 unsigned Success = RegInfo.createVirtualRegister(RC);
1150 // insert new blocks after the current block
1151 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1152 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1153 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1154 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1155 MachineFunction::iterator It = BB;
1157 MF->insert(It, loop1MBB);
1158 MF->insert(It, loop2MBB);
1159 MF->insert(It, exitMBB);
1161 // Transfer the remainder of BB and its successor edges to exitMBB.
1162 exitMBB->splice(exitMBB->begin(), BB,
1163 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1164 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1168 // fallthrough --> loop1MBB
1169 BB->addSuccessor(loop1MBB);
1170 loop1MBB->addSuccessor(exitMBB);
1171 loop1MBB->addSuccessor(loop2MBB);
1172 loop2MBB->addSuccessor(loop1MBB);
1173 loop2MBB->addSuccessor(exitMBB);
1177 // bne dest, oldval, exitMBB
1179 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1180 BuildMI(BB, DL, TII->get(BNE))
1181 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1184 // sc success, newval, 0(ptr)
1185 // beq success, $0, loop1MBB
1187 BuildMI(BB, DL, TII->get(SC), Success)
1188 .addReg(NewVal).addReg(Ptr).addImm(0);
1189 BuildMI(BB, DL, TII->get(BEQ))
1190 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1192 MI->eraseFromParent(); // The instruction is gone now.
1198 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1199 MachineBasicBlock *BB,
1200 unsigned Size) const {
1201 assert((Size == 1 || Size == 2) &&
1202 "Unsupported size for EmitAtomicCmpSwapPartial.");
1204 MachineFunction *MF = BB->getParent();
1205 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1206 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1207 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1208 DebugLoc DL = MI->getDebugLoc();
1210 unsigned Dest = MI->getOperand(0).getReg();
1211 unsigned Ptr = MI->getOperand(1).getReg();
1212 unsigned CmpVal = MI->getOperand(2).getReg();
1213 unsigned NewVal = MI->getOperand(3).getReg();
1215 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1216 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1217 unsigned Mask = RegInfo.createVirtualRegister(RC);
1218 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1219 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1220 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1221 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1222 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1223 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1224 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1225 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1226 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1227 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1228 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1229 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1230 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1231 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1232 unsigned Success = RegInfo.createVirtualRegister(RC);
1234 // insert new blocks after the current block
1235 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1236 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1237 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1238 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1239 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1240 MachineFunction::iterator It = BB;
1242 MF->insert(It, loop1MBB);
1243 MF->insert(It, loop2MBB);
1244 MF->insert(It, sinkMBB);
1245 MF->insert(It, exitMBB);
1247 // Transfer the remainder of BB and its successor edges to exitMBB.
1248 exitMBB->splice(exitMBB->begin(), BB,
1249 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1250 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1252 BB->addSuccessor(loop1MBB);
1253 loop1MBB->addSuccessor(sinkMBB);
1254 loop1MBB->addSuccessor(loop2MBB);
1255 loop2MBB->addSuccessor(loop1MBB);
1256 loop2MBB->addSuccessor(sinkMBB);
1257 sinkMBB->addSuccessor(exitMBB);
1259 // FIXME: computation of newval2 can be moved to loop2MBB.
1261 // addiu masklsb2,$0,-4 # 0xfffffffc
1262 // and alignedaddr,ptr,masklsb2
1263 // andi ptrlsb2,ptr,3
1264 // sll shiftamt,ptrlsb2,3
1265 // ori maskupper,$0,255 # 0xff
1266 // sll mask,maskupper,shiftamt
1267 // nor mask2,$0,mask
1268 // andi maskedcmpval,cmpval,255
1269 // sll shiftedcmpval,maskedcmpval,shiftamt
1270 // andi maskednewval,newval,255
1271 // sll shiftednewval,maskednewval,shiftamt
1272 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1273 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1274 .addReg(Mips::ZERO).addImm(-4);
1275 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1276 .addReg(Ptr).addReg(MaskLSB2);
1277 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1278 if (Subtarget->isLittle()) {
1279 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1281 unsigned Off = RegInfo.createVirtualRegister(RC);
1282 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1283 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1284 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1286 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1287 .addReg(Mips::ZERO).addImm(MaskImm);
1288 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1289 .addReg(MaskUpper).addReg(ShiftAmt);
1290 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1291 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1292 .addReg(CmpVal).addImm(MaskImm);
1293 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1294 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1295 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1296 .addReg(NewVal).addImm(MaskImm);
1297 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1298 .addReg(MaskedNewVal).addReg(ShiftAmt);
1301 // ll oldval,0(alginedaddr)
1302 // and maskedoldval0,oldval,mask
1303 // bne maskedoldval0,shiftedcmpval,sinkMBB
1305 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1306 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1307 .addReg(OldVal).addReg(Mask);
1308 BuildMI(BB, DL, TII->get(Mips::BNE))
1309 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1312 // and maskedoldval1,oldval,mask2
1313 // or storeval,maskedoldval1,shiftednewval
1314 // sc success,storeval,0(alignedaddr)
1315 // beq success,$0,loop1MBB
1317 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1318 .addReg(OldVal).addReg(Mask2);
1319 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1320 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1321 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1322 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1323 BuildMI(BB, DL, TII->get(Mips::BEQ))
1324 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1327 // srl srlres,maskedoldval0,shiftamt
1328 // sll sllres,srlres,24
1329 // sra dest,sllres,24
1331 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1333 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1334 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1335 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1336 .addReg(SrlRes).addImm(ShiftImm);
1337 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1338 .addReg(SllRes).addImm(ShiftImm);
1340 MI->eraseFromParent(); // The instruction is gone now.
1345 //===----------------------------------------------------------------------===//
1346 // Misc Lower Operation implementation
1347 //===----------------------------------------------------------------------===//
1348 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1349 SDValue Chain = Op.getOperand(0);
1350 SDValue Table = Op.getOperand(1);
1351 SDValue Index = Op.getOperand(2);
1353 EVT PTy = getPointerTy();
1354 unsigned EntrySize =
1355 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1357 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1358 DAG.getConstant(EntrySize, PTy));
1359 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1361 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1362 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1363 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1365 Chain = Addr.getValue(1);
1367 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
1368 // For PIC, the sequence is:
1369 // BRIND(load(Jumptable + index) + RelocBase)
1370 // RelocBase can be JumpTable, GOT or some sort of global base.
1371 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1372 getPICJumpTableRelocBase(Table, DAG));
1375 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1378 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1379 // The first operand is the chain, the second is the condition, the third is
1380 // the block to branch to if the condition is true.
1381 SDValue Chain = Op.getOperand(0);
1382 SDValue Dest = Op.getOperand(2);
1385 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1387 // Return if flag is not set by a floating point comparison.
1388 if (CondRes.getOpcode() != MipsISD::FPCmp)
1391 SDValue CCNode = CondRes.getOperand(2);
1393 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1394 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1395 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1396 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1397 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1398 FCC0, Dest, CondRes);
1401 SDValue MipsTargetLowering::
1402 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1404 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1406 // Return if flag is not set by a floating point comparison.
1407 if (Cond.getOpcode() != MipsISD::FPCmp)
1410 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1414 SDValue MipsTargetLowering::
1415 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1418 EVT Ty = Op.getOperand(0).getValueType();
1419 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1420 getSetCCResultType(*DAG.getContext(), Ty),
1421 Op.getOperand(0), Op.getOperand(1),
1424 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1428 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1429 SDValue Cond = createFPCmp(DAG, Op);
1431 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1432 "Floating point operand expected.");
1434 SDValue True = DAG.getConstant(1, MVT::i32);
1435 SDValue False = DAG.getConstant(0, MVT::i32);
1437 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1440 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1441 SelectionDAG &DAG) const {
1442 // FIXME there isn't actually debug info here
1444 EVT Ty = Op.getValueType();
1445 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1446 const GlobalValue *GV = N->getGlobal();
1448 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1449 const MipsTargetObjectFile &TLOF =
1450 (const MipsTargetObjectFile&)getObjFileLowering();
1452 // %gp_rel relocation
1453 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1454 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1456 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1457 DAG.getVTList(MVT::i32), &GA, 1);
1458 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1459 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1462 // %hi/%lo relocation
1463 return getAddrNonPIC(N, Ty, DAG);
1466 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1467 return getAddrLocal(N, Ty, DAG, HasMips64);
1470 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
1471 MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1472 MachinePointerInfo::getGOT());
1474 return getAddrGlobal(N, Ty, DAG,
1475 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
1476 DAG.getEntryNode(), MachinePointerInfo::getGOT());
1479 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1480 SelectionDAG &DAG) const {
1481 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1482 EVT Ty = Op.getValueType();
1484 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1485 return getAddrNonPIC(N, Ty, DAG);
1487 return getAddrLocal(N, Ty, DAG, HasMips64);
1490 SDValue MipsTargetLowering::
1491 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1493 // If the relocation model is PIC, use the General Dynamic TLS Model or
1494 // Local Dynamic TLS model, otherwise use the Initial Exec or
1495 // Local Exec TLS Model.
1497 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1499 const GlobalValue *GV = GA->getGlobal();
1500 EVT PtrVT = getPointerTy();
1502 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1504 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1505 // General Dynamic and Local Dynamic TLS Model.
1506 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1509 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1510 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1511 getGlobalReg(DAG, PtrVT), TGA);
1512 unsigned PtrSize = PtrVT.getSizeInBits();
1513 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1515 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1519 Entry.Node = Argument;
1521 Args.push_back(Entry);
1523 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1524 false, false, false, false, 0, CallingConv::C,
1525 /*IsTailCall=*/false, /*doesNotRet=*/false,
1526 /*isReturnValueUsed=*/true,
1527 TlsGetAddr, Args, DAG, DL);
1528 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1530 SDValue Ret = CallResult.first;
1532 if (model != TLSModel::LocalDynamic)
1535 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1536 MipsII::MO_DTPREL_HI);
1537 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1538 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1539 MipsII::MO_DTPREL_LO);
1540 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1541 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1542 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1546 if (model == TLSModel::InitialExec) {
1547 // Initial Exec TLS Model
1548 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1549 MipsII::MO_GOTTPREL);
1550 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1552 Offset = DAG.getLoad(PtrVT, DL,
1553 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1554 false, false, false, 0);
1556 // Local Exec TLS Model
1557 assert(model == TLSModel::LocalExec);
1558 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1559 MipsII::MO_TPREL_HI);
1560 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1561 MipsII::MO_TPREL_LO);
1562 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1563 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1564 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1567 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1568 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1571 SDValue MipsTargetLowering::
1572 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1574 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1575 EVT Ty = Op.getValueType();
1577 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1578 return getAddrNonPIC(N, Ty, DAG);
1580 return getAddrLocal(N, Ty, DAG, HasMips64);
1583 SDValue MipsTargetLowering::
1584 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1586 // gp_rel relocation
1587 // FIXME: we should reference the constant pool using small data sections,
1588 // but the asm printer currently doesn't support this feature without
1589 // hacking it. This feature should come soon so we can uncomment the
1591 //if (IsInSmallSection(C->getType())) {
1592 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1593 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1594 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1595 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1596 EVT Ty = Op.getValueType();
1598 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1599 return getAddrNonPIC(N, Ty, DAG);
1601 return getAddrLocal(N, Ty, DAG, HasMips64);
1604 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1605 MachineFunction &MF = DAG.getMachineFunction();
1606 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1609 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1612 // vastart just stores the address of the VarArgsFrameIndex slot into the
1613 // memory location argument.
1614 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1615 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1616 MachinePointerInfo(SV), false, false, 0);
1619 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1620 bool HasExtractInsert) {
1621 EVT TyX = Op.getOperand(0).getValueType();
1622 EVT TyY = Op.getOperand(1).getValueType();
1623 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1624 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1628 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1630 SDValue X = (TyX == MVT::f32) ?
1631 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1632 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1634 SDValue Y = (TyY == MVT::f32) ?
1635 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1636 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1639 if (HasExtractInsert) {
1640 // ext E, Y, 31, 1 ; extract bit31 of Y
1641 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1642 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1643 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1646 // srl SrlX, SllX, 1
1648 // sll SllY, SrlX, 31
1649 // or Or, SrlX, SllY
1650 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1651 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1652 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1653 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1654 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1657 if (TyX == MVT::f32)
1658 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1660 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1661 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1662 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1665 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1666 bool HasExtractInsert) {
1667 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1668 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1669 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1670 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1673 // Bitcast to integer nodes.
1674 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1675 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1677 if (HasExtractInsert) {
1678 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1679 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1680 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1681 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1683 if (WidthX > WidthY)
1684 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1685 else if (WidthY > WidthX)
1686 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1688 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1689 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1690 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1693 // (d)sll SllX, X, 1
1694 // (d)srl SrlX, SllX, 1
1695 // (d)srl SrlY, Y, width(Y)-1
1696 // (d)sll SllY, SrlX, width(Y)-1
1697 // or Or, SrlX, SllY
1698 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1699 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1700 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1701 DAG.getConstant(WidthY - 1, MVT::i32));
1703 if (WidthX > WidthY)
1704 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1705 else if (WidthY > WidthX)
1706 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1708 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1709 DAG.getConstant(WidthX - 1, MVT::i32));
1710 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1711 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1715 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1716 if (Subtarget->hasMips64())
1717 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert());
1719 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert());
1722 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
1723 bool HasExtractInsert) {
1724 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1727 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1729 SDValue X = (Op.getValueType() == MVT::f32) ?
1730 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1731 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1735 if (HasExtractInsert)
1736 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1737 DAG.getRegister(Mips::ZERO, MVT::i32),
1738 DAG.getConstant(31, MVT::i32), Const1, X);
1740 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1741 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1744 if (Op.getValueType() == MVT::f32)
1745 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1747 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1748 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1749 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1752 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
1753 bool HasExtractInsert) {
1754 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1757 // Bitcast to integer node.
1758 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1761 if (HasExtractInsert)
1762 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1763 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1764 DAG.getConstant(63, MVT::i32), Const1, X);
1766 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1767 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1770 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1774 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
1775 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1776 return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert());
1778 return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert());
1781 SDValue MipsTargetLowering::
1782 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1784 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1785 "Frame address can only be determined for current frame.");
1787 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1788 MFI->setFrameAddressIsTaken(true);
1789 EVT VT = Op.getValueType();
1791 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1792 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1796 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1797 SelectionDAG &DAG) const {
1799 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1800 "Return address can be determined only for current frame.");
1802 MachineFunction &MF = DAG.getMachineFunction();
1803 MachineFrameInfo *MFI = MF.getFrameInfo();
1804 MVT VT = Op.getSimpleValueType();
1805 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1806 MFI->setReturnAddressIsTaken(true);
1808 // Return RA, which contains the return address. Mark it an implicit live-in.
1809 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1810 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1813 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1814 // generated from __builtin_eh_return (offset, handler)
1815 // The effect of this is to adjust the stack pointer by "offset"
1816 // and then branch to "handler".
1817 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1819 MachineFunction &MF = DAG.getMachineFunction();
1820 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1822 MipsFI->setCallsEhReturn();
1823 SDValue Chain = Op.getOperand(0);
1824 SDValue Offset = Op.getOperand(1);
1825 SDValue Handler = Op.getOperand(2);
1827 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
1829 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1830 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1831 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1832 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
1833 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1834 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1835 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1836 DAG.getRegister(OffsetReg, Ty),
1837 DAG.getRegister(AddrReg, getPointerTy()),
1841 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1842 SelectionDAG &DAG) const {
1843 // FIXME: Need pseudo-fence for 'singlethread' fences
1844 // FIXME: Set SType for weaker fences where supported/appropriate.
1847 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1848 DAG.getConstant(SType, MVT::i32));
1851 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1852 SelectionDAG &DAG) const {
1854 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1855 SDValue Shamt = Op.getOperand(2);
1858 // lo = (shl lo, shamt)
1859 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1862 // hi = (shl lo, shamt[4:0])
1863 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1864 DAG.getConstant(-1, MVT::i32));
1865 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1866 DAG.getConstant(1, MVT::i32));
1867 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1869 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1870 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1871 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1872 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1873 DAG.getConstant(0x20, MVT::i32));
1874 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1875 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1876 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1878 SDValue Ops[2] = {Lo, Hi};
1879 return DAG.getMergeValues(Ops, 2, DL);
1882 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1885 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1886 SDValue Shamt = Op.getOperand(2);
1889 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1891 // hi = (sra hi, shamt)
1893 // hi = (srl hi, shamt)
1896 // lo = (sra hi, shamt[4:0])
1897 // hi = (sra hi, 31)
1899 // lo = (srl hi, shamt[4:0])
1901 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1902 DAG.getConstant(-1, MVT::i32));
1903 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1904 DAG.getConstant(1, MVT::i32));
1905 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1906 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1907 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1908 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1910 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1911 DAG.getConstant(0x20, MVT::i32));
1912 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1913 DAG.getConstant(31, MVT::i32));
1914 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1915 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1916 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
1919 SDValue Ops[2] = {Lo, Hi};
1920 return DAG.getMergeValues(Ops, 2, DL);
1923 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
1924 SDValue Chain, SDValue Src, unsigned Offset) {
1925 SDValue Ptr = LD->getBasePtr();
1926 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
1927 EVT BasePtrVT = Ptr.getValueType();
1929 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1932 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1933 DAG.getConstant(Offset, BasePtrVT));
1935 SDValue Ops[] = { Chain, Ptr, Src };
1936 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
1937 LD->getMemOperand());
1940 // Expand an unaligned 32 or 64-bit integer load node.
1941 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1942 LoadSDNode *LD = cast<LoadSDNode>(Op);
1943 EVT MemVT = LD->getMemoryVT();
1945 // Return if load is aligned or if MemVT is neither i32 nor i64.
1946 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
1947 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
1950 bool IsLittle = Subtarget->isLittle();
1951 EVT VT = Op.getValueType();
1952 ISD::LoadExtType ExtType = LD->getExtensionType();
1953 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
1955 assert((VT == MVT::i32) || (VT == MVT::i64));
1958 // (set dst, (i64 (load baseptr)))
1960 // (set tmp, (ldl (add baseptr, 7), undef))
1961 // (set dst, (ldr baseptr, tmp))
1962 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
1963 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1965 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
1969 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
1971 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
1975 // (set dst, (i32 (load baseptr))) or
1976 // (set dst, (i64 (sextload baseptr))) or
1977 // (set dst, (i64 (extload baseptr)))
1979 // (set tmp, (lwl (add baseptr, 3), undef))
1980 // (set dst, (lwr baseptr, tmp))
1981 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
1982 (ExtType == ISD::EXTLOAD))
1985 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
1988 // (set dst, (i64 (zextload baseptr)))
1990 // (set tmp0, (lwl (add baseptr, 3), undef))
1991 // (set tmp1, (lwr baseptr, tmp0))
1992 // (set tmp2, (shl tmp1, 32))
1993 // (set dst, (srl tmp2, 32))
1995 SDValue Const32 = DAG.getConstant(32, MVT::i32);
1996 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
1997 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
1998 SDValue Ops[] = { SRL, LWR.getValue(1) };
1999 return DAG.getMergeValues(Ops, 2, DL);
2002 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2003 SDValue Chain, unsigned Offset) {
2004 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2005 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2007 SDVTList VTList = DAG.getVTList(MVT::Other);
2010 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2011 DAG.getConstant(Offset, BasePtrVT));
2013 SDValue Ops[] = { Chain, Value, Ptr };
2014 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2015 SD->getMemOperand());
2018 // Expand an unaligned 32 or 64-bit integer store node.
2019 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2021 SDValue Value = SD->getValue(), Chain = SD->getChain();
2022 EVT VT = Value.getValueType();
2025 // (store val, baseptr) or
2026 // (truncstore val, baseptr)
2028 // (swl val, (add baseptr, 3))
2029 // (swr val, baseptr)
2030 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2031 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2033 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2036 assert(VT == MVT::i64);
2039 // (store val, baseptr)
2041 // (sdl val, (add baseptr, 7))
2042 // (sdr val, baseptr)
2043 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2044 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2047 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2048 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2049 SDValue Val = SD->getValue();
2051 if (Val.getOpcode() != ISD::FP_TO_SINT)
2054 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2055 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2058 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2059 SD->getPointerInfo(), SD->isVolatile(),
2060 SD->isNonTemporal(), SD->getAlignment());
2063 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2064 StoreSDNode *SD = cast<StoreSDNode>(Op);
2065 EVT MemVT = SD->getMemoryVT();
2067 // Lower unaligned integer stores.
2068 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2069 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2070 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
2072 return lowerFP_TO_SINT_STORE(SD, DAG);
2075 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2076 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2077 || cast<ConstantSDNode>
2078 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2079 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2083 // (add (frameaddr 0), (frame_to_args_offset))
2084 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2085 // (add FrameObject, 0)
2086 // where FrameObject is a fixed StackObject with offset 0 which points to
2087 // the old stack pointer.
2088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2089 EVT ValTy = Op->getValueType(0);
2090 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2091 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2092 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2093 DAG.getConstant(0, ValTy));
2096 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2097 SelectionDAG &DAG) const {
2098 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2099 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2101 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2104 //===----------------------------------------------------------------------===//
2105 // Calling Convention Implementation
2106 //===----------------------------------------------------------------------===//
2108 //===----------------------------------------------------------------------===//
2109 // TODO: Implement a generic logic using tblgen that can support this.
2110 // Mips O32 ABI rules:
2112 // i32 - Passed in A0, A1, A2, A3 and stack
2113 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2114 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2115 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2116 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2117 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2120 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2121 //===----------------------------------------------------------------------===//
2123 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2124 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2125 CCState &State, const uint16_t *F64Regs) {
2127 static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
2129 static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2130 static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 };
2132 // Do not process byval args here.
2133 if (ArgFlags.isByVal())
2136 // Promote i8 and i16
2137 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2139 if (ArgFlags.isSExt())
2140 LocInfo = CCValAssign::SExt;
2141 else if (ArgFlags.isZExt())
2142 LocInfo = CCValAssign::ZExt;
2144 LocInfo = CCValAssign::AExt;
2149 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2150 // is true: function is vararg, argument is 3rd or higher, there is previous
2151 // argument which is not f32 or f64.
2152 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2153 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2154 unsigned OrigAlign = ArgFlags.getOrigAlign();
2155 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2157 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2158 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2159 // If this is the first part of an i64 arg,
2160 // the allocated register must be either A0 or A2.
2161 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2162 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2164 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2165 // Allocate int register and shadow next int register. If first
2166 // available register is Mips::A1 or Mips::A3, shadow it too.
2167 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2168 if (Reg == Mips::A1 || Reg == Mips::A3)
2169 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2170 State.AllocateReg(IntRegs, IntRegsSize);
2172 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2173 // we are guaranteed to find an available float register
2174 if (ValVT == MVT::f32) {
2175 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2176 // Shadow int register
2177 State.AllocateReg(IntRegs, IntRegsSize);
2179 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2180 // Shadow int registers
2181 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2182 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2183 State.AllocateReg(IntRegs, IntRegsSize);
2184 State.AllocateReg(IntRegs, IntRegsSize);
2187 llvm_unreachable("Cannot handle this ValVT.");
2190 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2194 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2199 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2200 MVT LocVT, CCValAssign::LocInfo LocInfo,
2201 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2202 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 };
2204 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2207 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2208 MVT LocVT, CCValAssign::LocInfo LocInfo,
2209 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2210 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 };
2212 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2215 #include "MipsGenCallingConv.inc"
2217 //===----------------------------------------------------------------------===//
2218 // Call Calling Convention Implementation
2219 //===----------------------------------------------------------------------===//
2221 // Return next O32 integer argument register.
2222 static unsigned getNextIntArgReg(unsigned Reg) {
2223 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2224 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2228 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2229 SDValue Chain, SDValue Arg, SDLoc DL,
2230 bool IsTailCall, SelectionDAG &DAG) const {
2232 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2233 DAG.getIntPtrConstant(Offset));
2234 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2238 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2239 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2240 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2241 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2242 /*isVolatile=*/ true, false, 0);
2245 void MipsTargetLowering::
2246 getOpndList(SmallVectorImpl<SDValue> &Ops,
2247 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2248 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2249 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2250 // Insert node "GP copy globalreg" before call to function.
2252 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2253 // in PIC mode) allow symbols to be resolved via lazy binding.
2254 // The lazy binding stub requires GP to point to the GOT.
2255 if (IsPICCall && !InternalLinkage) {
2256 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2257 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2258 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2261 // Build a sequence of copy-to-reg nodes chained together with token
2262 // chain and flag operands which copy the outgoing args into registers.
2263 // The InFlag in necessary since all emitted instructions must be
2267 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2268 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2269 RegsToPass[i].second, InFlag);
2270 InFlag = Chain.getValue(1);
2273 // Add argument registers to the end of the list so that they are
2274 // known live into the call.
2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2276 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2277 RegsToPass[i].second.getValueType()));
2279 // Add a register mask operand representing the call-preserved registers.
2280 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2281 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2282 assert(Mask && "Missing call preserved mask for calling convention");
2283 if (Subtarget->inMips16HardFloat()) {
2284 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2285 llvm::StringRef Sym = G->getGlobal()->getName();
2286 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2287 if (F->hasFnAttribute("__Mips16RetHelper")) {
2288 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2292 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2294 if (InFlag.getNode())
2295 Ops.push_back(InFlag);
2298 /// LowerCall - functions arguments are copied from virtual regs to
2299 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2301 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2302 SmallVectorImpl<SDValue> &InVals) const {
2303 SelectionDAG &DAG = CLI.DAG;
2305 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2306 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2307 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2308 SDValue Chain = CLI.Chain;
2309 SDValue Callee = CLI.Callee;
2310 bool &IsTailCall = CLI.IsTailCall;
2311 CallingConv::ID CallConv = CLI.CallConv;
2312 bool IsVarArg = CLI.IsVarArg;
2314 MachineFunction &MF = DAG.getMachineFunction();
2315 MachineFrameInfo *MFI = MF.getFrameInfo();
2316 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2317 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2318 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2320 // Analyze operands of the call, assigning locations to each operand.
2321 SmallVector<CCValAssign, 16> ArgLocs;
2322 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2323 getTargetMachine(), ArgLocs, *DAG.getContext());
2324 MipsCC::SpecialCallingConvType SpecialCallingConv =
2325 getSpecialCallingConv(Callee);
2326 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo,
2327 SpecialCallingConv);
2329 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2330 Subtarget->mipsSEUsesSoftFloat(),
2331 Callee.getNode(), CLI.Args);
2333 // Get a count of how many bytes are to be pushed on the stack.
2334 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2336 // Check if it's really possible to do a tail call.
2339 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2340 *MF.getInfo<MipsFunctionInfo>());
2345 // Chain is the output chain of the last Load/Store or CopyToReg node.
2346 // ByValChain is the output chain of the last Memcpy node created for copying
2347 // byval arguments to the stack.
2348 unsigned StackAlignment = TFL->getStackAlignment();
2349 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2350 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2353 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2355 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
2356 IsN64 ? Mips::SP_64 : Mips::SP,
2359 // With EABI is it possible to have 16 args on registers.
2360 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2361 SmallVector<SDValue, 8> MemOpChains;
2362 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2364 // Walk the register/memloc assignments, inserting copies/loads.
2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2366 SDValue Arg = OutVals[i];
2367 CCValAssign &VA = ArgLocs[i];
2368 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2369 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2372 if (Flags.isByVal()) {
2373 assert(Flags.getByValSize() &&
2374 "ByVal args of size 0 should have been ignored by front-end.");
2375 assert(ByValArg != MipsCCInfo.byval_end());
2376 assert(!IsTailCall &&
2377 "Do not tail-call optimize if there is a byval argument.");
2378 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2379 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2384 // Promote the value if needed.
2385 switch (VA.getLocInfo()) {
2386 default: llvm_unreachable("Unknown loc info!");
2387 case CCValAssign::Full:
2388 if (VA.isRegLoc()) {
2389 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2390 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2391 (ValVT == MVT::i64 && LocVT == MVT::f64))
2392 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2393 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2394 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2395 Arg, DAG.getConstant(0, MVT::i32));
2396 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2397 Arg, DAG.getConstant(1, MVT::i32));
2398 if (!Subtarget->isLittle())
2400 unsigned LocRegLo = VA.getLocReg();
2401 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2402 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2403 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2408 case CCValAssign::SExt:
2409 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2411 case CCValAssign::ZExt:
2412 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2414 case CCValAssign::AExt:
2415 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2419 // Arguments that can be passed on register must be kept at
2420 // RegsToPass vector
2421 if (VA.isRegLoc()) {
2422 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2426 // Register can't get to this point...
2427 assert(VA.isMemLoc());
2429 // emit ISD::STORE whichs stores the
2430 // parameter value to a stack Location
2431 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2432 Chain, Arg, DL, IsTailCall, DAG));
2435 // Transform all store nodes into one single node because all store
2436 // nodes are independent of each other.
2437 if (!MemOpChains.empty())
2438 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2439 &MemOpChains[0], MemOpChains.size());
2441 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2442 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2443 // node so that legalize doesn't hack it.
2444 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2445 bool GlobalOrExternal = false, InternalLinkage = false;
2447 EVT Ty = Callee.getValueType();
2449 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2451 const GlobalValue *Val = G->getGlobal();
2452 InternalLinkage = Val->hasInternalLinkage();
2454 if (InternalLinkage)
2455 Callee = getAddrLocal(G, Ty, DAG, HasMips64);
2457 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
2458 MipsII::MO_CALL_LO16, Chain,
2459 FuncInfo->callPtrInfo(Val));
2461 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2462 FuncInfo->callPtrInfo(Val));
2464 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2465 MipsII::MO_NO_FLAG);
2466 GlobalOrExternal = true;
2468 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2469 const char *Sym = S->getSymbol();
2471 if (!IsN64 && !IsPIC) // !N64 && static
2472 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
2473 MipsII::MO_NO_FLAG);
2475 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16,
2476 MipsII::MO_CALL_LO16, Chain,
2477 FuncInfo->callPtrInfo(Sym));
2479 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2480 FuncInfo->callPtrInfo(Sym));
2482 GlobalOrExternal = true;
2485 SmallVector<SDValue, 8> Ops(1, Chain);
2486 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2488 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2489 CLI, Callee, Chain);
2492 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
2494 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
2495 SDValue InFlag = Chain.getValue(1);
2497 // Create the CALLSEQ_END node.
2498 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2499 DAG.getIntPtrConstant(0, true), InFlag, DL);
2500 InFlag = Chain.getValue(1);
2502 // Handle result values, copying them out of physregs into vregs that we
2504 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2505 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2508 /// LowerCallResult - Lower the result values of a call into the
2509 /// appropriate copies out of appropriate physical registers.
2511 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2512 CallingConv::ID CallConv, bool IsVarArg,
2513 const SmallVectorImpl<ISD::InputArg> &Ins,
2514 SDLoc DL, SelectionDAG &DAG,
2515 SmallVectorImpl<SDValue> &InVals,
2516 const SDNode *CallNode,
2517 const Type *RetTy) const {
2518 // Assign locations to each value returned by this call.
2519 SmallVector<CCValAssign, 16> RVLocs;
2520 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2521 getTargetMachine(), RVLocs, *DAG.getContext());
2522 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2524 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
2527 // Copy all of the result registers out of their specified physreg.
2528 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2529 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2530 RVLocs[i].getLocVT(), InFlag);
2531 Chain = Val.getValue(1);
2532 InFlag = Val.getValue(2);
2534 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2535 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2537 InVals.push_back(Val);
2543 //===----------------------------------------------------------------------===//
2544 // Formal Arguments Calling Convention Implementation
2545 //===----------------------------------------------------------------------===//
2546 /// LowerFormalArguments - transform physical registers into virtual registers
2547 /// and generate load operations for arguments places on the stack.
2549 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2550 CallingConv::ID CallConv,
2552 const SmallVectorImpl<ISD::InputArg> &Ins,
2553 SDLoc DL, SelectionDAG &DAG,
2554 SmallVectorImpl<SDValue> &InVals)
2556 MachineFunction &MF = DAG.getMachineFunction();
2557 MachineFrameInfo *MFI = MF.getFrameInfo();
2558 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2560 MipsFI->setVarArgsFrameIndex(0);
2562 // Used with vargs to acumulate store chains.
2563 std::vector<SDValue> OutChains;
2565 // Assign locations to all of the incoming arguments.
2566 SmallVector<CCValAssign, 16> ArgLocs;
2567 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2568 getTargetMachine(), ArgLocs, *DAG.getContext());
2569 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2570 Function::const_arg_iterator FuncArg =
2571 DAG.getMachineFunction().getFunction()->arg_begin();
2572 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
2574 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2575 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2576 MipsCCInfo.hasByValArg());
2578 unsigned CurArgIdx = 0;
2579 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2581 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2582 CCValAssign &VA = ArgLocs[i];
2583 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2584 CurArgIdx = Ins[i].OrigArgIndex;
2585 EVT ValVT = VA.getValVT();
2586 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2587 bool IsRegLoc = VA.isRegLoc();
2589 if (Flags.isByVal()) {
2590 assert(Flags.getByValSize() &&
2591 "ByVal args of size 0 should have been ignored by front-end.");
2592 assert(ByValArg != MipsCCInfo.byval_end());
2593 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2594 MipsCCInfo, *ByValArg);
2599 // Arguments stored on registers
2601 EVT RegVT = VA.getLocVT();
2602 unsigned ArgReg = VA.getLocReg();
2603 const TargetRegisterClass *RC;
2605 if (RegVT == MVT::i32)
2606 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2607 &Mips::GPR32RegClass;
2608 else if (RegVT == MVT::i64)
2609 RC = &Mips::GPR64RegClass;
2610 else if (RegVT == MVT::f32)
2611 RC = &Mips::FGR32RegClass;
2612 else if (RegVT == MVT::f64)
2613 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass :
2614 &Mips::AFGR64RegClass;
2616 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2618 // Transform the arguments stored on
2619 // physical registers into virtual ones
2620 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2621 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2623 // If this is an 8 or 16-bit value, it has been passed promoted
2624 // to 32 bits. Insert an assert[sz]ext to capture this, then
2625 // truncate to the right size.
2626 if (VA.getLocInfo() != CCValAssign::Full) {
2627 unsigned Opcode = 0;
2628 if (VA.getLocInfo() == CCValAssign::SExt)
2629 Opcode = ISD::AssertSext;
2630 else if (VA.getLocInfo() == CCValAssign::ZExt)
2631 Opcode = ISD::AssertZext;
2633 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2634 DAG.getValueType(ValVT));
2635 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2638 // Handle floating point arguments passed in integer registers and
2639 // long double arguments passed in floating point registers.
2640 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2641 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2642 (RegVT == MVT::f64 && ValVT == MVT::i64))
2643 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2644 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2645 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2646 getNextIntArgReg(ArgReg), RC);
2647 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2648 if (!Subtarget->isLittle())
2649 std::swap(ArgValue, ArgValue2);
2650 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2651 ArgValue, ArgValue2);
2654 InVals.push_back(ArgValue);
2655 } else { // VA.isRegLoc()
2658 assert(VA.isMemLoc());
2660 // The stack pointer offset is relative to the caller stack frame.
2661 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2662 VA.getLocMemOffset(), true);
2664 // Create load nodes to retrieve arguments from the stack
2665 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2666 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
2667 MachinePointerInfo::getFixedStack(FI),
2668 false, false, false, 0));
2672 // The mips ABIs for returning structs by value requires that we copy
2673 // the sret argument into $v0 for the return. Save the argument into
2674 // a virtual register so that we can access it from the return points.
2675 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2676 unsigned Reg = MipsFI->getSRetReturnReg();
2678 Reg = MF.getRegInfo().
2679 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
2680 MipsFI->setSRetReturnReg(Reg);
2682 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
2683 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2687 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2689 // All stores are grouped in one node to allow the matching between
2690 // the size of Ins and InVals. This only happens when on varg functions
2691 if (!OutChains.empty()) {
2692 OutChains.push_back(Chain);
2693 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2694 &OutChains[0], OutChains.size());
2700 //===----------------------------------------------------------------------===//
2701 // Return Value Calling Convention Implementation
2702 //===----------------------------------------------------------------------===//
2705 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2706 MachineFunction &MF, bool IsVarArg,
2707 const SmallVectorImpl<ISD::OutputArg> &Outs,
2708 LLVMContext &Context) const {
2709 SmallVector<CCValAssign, 16> RVLocs;
2710 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2712 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2716 MipsTargetLowering::LowerReturn(SDValue Chain,
2717 CallingConv::ID CallConv, bool IsVarArg,
2718 const SmallVectorImpl<ISD::OutputArg> &Outs,
2719 const SmallVectorImpl<SDValue> &OutVals,
2720 SDLoc DL, SelectionDAG &DAG) const {
2721 // CCValAssign - represent the assignment of
2722 // the return value to a location
2723 SmallVector<CCValAssign, 16> RVLocs;
2724 MachineFunction &MF = DAG.getMachineFunction();
2726 // CCState - Info about the registers and stack slot.
2727 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2729 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2731 // Analyze return values.
2732 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
2733 MF.getFunction()->getReturnType());
2736 SmallVector<SDValue, 4> RetOps(1, Chain);
2738 // Copy the result values into the output registers.
2739 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2740 SDValue Val = OutVals[i];
2741 CCValAssign &VA = RVLocs[i];
2742 assert(VA.isRegLoc() && "Can only return in registers!");
2744 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2745 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2747 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2749 // Guarantee that all emitted copies are stuck together with flags.
2750 Flag = Chain.getValue(1);
2751 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2754 // The mips ABIs for returning structs by value requires that we copy
2755 // the sret argument into $v0 for the return. We saved the argument into
2756 // a virtual register in the entry block, so now we copy the value out
2758 if (MF.getFunction()->hasStructRetAttr()) {
2759 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2760 unsigned Reg = MipsFI->getSRetReturnReg();
2763 llvm_unreachable("sret virtual register not created in the entry block");
2764 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2765 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2767 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2768 Flag = Chain.getValue(1);
2769 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2772 RetOps[0] = Chain; // Update chain.
2774 // Add the flag if we have it.
2776 RetOps.push_back(Flag);
2778 // Return on Mips is always a "jr $ra"
2779 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
2782 //===----------------------------------------------------------------------===//
2783 // Mips Inline Assembly Support
2784 //===----------------------------------------------------------------------===//
2786 /// getConstraintType - Given a constraint letter, return the type of
2787 /// constraint it is for this target.
2788 MipsTargetLowering::ConstraintType MipsTargetLowering::
2789 getConstraintType(const std::string &Constraint) const
2791 // Mips specific constrainy
2792 // GCC config/mips/constraints.md
2794 // 'd' : An address register. Equivalent to r
2795 // unless generating MIPS16 code.
2796 // 'y' : Equivalent to r; retained for
2797 // backwards compatibility.
2798 // 'c' : A register suitable for use in an indirect
2799 // jump. This will always be $25 for -mabicalls.
2800 // 'l' : The lo register. 1 word storage.
2801 // 'x' : The hilo register pair. Double word storage.
2802 if (Constraint.size() == 1) {
2803 switch (Constraint[0]) {
2811 return C_RegisterClass;
2816 return TargetLowering::getConstraintType(Constraint);
2819 /// Examine constraint type and operand type and determine a weight value.
2820 /// This object must already have been set up with the operand type
2821 /// and the current alternative constraint selected.
2822 TargetLowering::ConstraintWeight
2823 MipsTargetLowering::getSingleConstraintMatchWeight(
2824 AsmOperandInfo &info, const char *constraint) const {
2825 ConstraintWeight weight = CW_Invalid;
2826 Value *CallOperandVal = info.CallOperandVal;
2827 // If we don't have a value, we can't do a match,
2828 // but allow it at the lowest weight.
2829 if (CallOperandVal == NULL)
2831 Type *type = CallOperandVal->getType();
2832 // Look at the constraint type.
2833 switch (*constraint) {
2835 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2839 if (type->isIntegerTy())
2840 weight = CW_Register;
2843 if (type->isFloatTy())
2844 weight = CW_Register;
2846 case 'c': // $25 for indirect jumps
2847 case 'l': // lo register
2848 case 'x': // hilo register pair
2849 if (type->isIntegerTy())
2850 weight = CW_SpecificReg;
2852 case 'I': // signed 16 bit immediate
2853 case 'J': // integer zero
2854 case 'K': // unsigned 16 bit immediate
2855 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2856 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2857 case 'O': // signed 15 bit immediate (+- 16383)
2858 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2859 if (isa<ConstantInt>(CallOperandVal))
2860 weight = CW_Constant;
2869 /// This is a helper function to parse a physical register string and split it
2870 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
2871 /// that is returned indicates whether parsing was successful. The second flag
2872 /// is true if the numeric part exists.
2873 static std::pair<bool, bool>
2874 parsePhysicalReg(const StringRef &C, std::string &Prefix,
2875 unsigned long long &Reg) {
2876 if (C.front() != '{' || C.back() != '}')
2877 return std::make_pair(false, false);
2879 // Search for the first numeric character.
2880 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
2881 I = std::find_if(B, E, std::ptr_fun(isdigit));
2883 Prefix.assign(B, I - B);
2885 // The second flag is set to false if no numeric characters were found.
2887 return std::make_pair(true, false);
2889 // Parse the numeric characters.
2890 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
2894 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
2895 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
2896 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2897 const TargetRegisterClass *RC;
2899 unsigned long long Reg;
2901 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
2904 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2906 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
2907 // No numeric characters follow "hi" or "lo".
2909 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2911 RC = TRI->getRegClass(Prefix == "hi" ?
2912 Mips::HI32RegClassID : Mips::LO32RegClassID);
2913 return std::make_pair(*(RC->begin()), RC);
2917 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2919 if (Prefix == "$f") { // Parse $f0-$f31.
2920 // If the size of FP registers is 64-bit or Reg is an even number, select
2921 // the 64-bit register class. Otherwise, select the 32-bit register class.
2922 if (VT == MVT::Other)
2923 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
2925 RC = getRegClassFor(VT);
2927 if (RC == &Mips::AFGR64RegClass) {
2928 assert(Reg % 2 == 0);
2931 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7.
2932 RC = TRI->getRegClass(Mips::FCCRegClassID);
2933 } else { // Parse $0-$31.
2934 assert(Prefix == "$");
2935 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
2938 assert(Reg < RC->getNumRegs());
2939 return std::make_pair(*(RC->begin() + Reg), RC);
2942 /// Given a register class constraint, like 'r', if this corresponds directly
2943 /// to an LLVM register class, return a register of 0 and the register class
2945 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2946 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
2948 if (Constraint.size() == 1) {
2949 switch (Constraint[0]) {
2950 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2951 case 'y': // Same as 'r'. Exists for compatibility.
2953 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
2954 if (Subtarget->inMips16Mode())
2955 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2956 return std::make_pair(0U, &Mips::GPR32RegClass);
2958 if (VT == MVT::i64 && !HasMips64)
2959 return std::make_pair(0U, &Mips::GPR32RegClass);
2960 if (VT == MVT::i64 && HasMips64)
2961 return std::make_pair(0U, &Mips::GPR64RegClass);
2962 // This will generate an error message
2963 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2966 return std::make_pair(0U, &Mips::FGR32RegClass);
2967 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
2968 if (Subtarget->isFP64bit())
2969 return std::make_pair(0U, &Mips::FGR64RegClass);
2970 return std::make_pair(0U, &Mips::AFGR64RegClass);
2973 case 'c': // register suitable for indirect jump
2975 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
2976 assert(VT == MVT::i64 && "Unexpected type.");
2977 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
2978 case 'l': // register suitable for indirect jump
2980 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
2981 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
2982 case 'x': // register suitable for indirect jump
2983 // Fixme: Not triggering the use of both hi and low
2984 // This will generate an error message
2985 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2989 std::pair<unsigned, const TargetRegisterClass *> R;
2990 R = parseRegForInlineAsmConstraint(Constraint, VT);
2995 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2998 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2999 /// vector. If it is invalid, don't add anything to Ops.
3000 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3001 std::string &Constraint,
3002 std::vector<SDValue>&Ops,
3003 SelectionDAG &DAG) const {
3004 SDValue Result(0, 0);
3006 // Only support length 1 constraints for now.
3007 if (Constraint.length() > 1) return;
3009 char ConstraintLetter = Constraint[0];
3010 switch (ConstraintLetter) {
3011 default: break; // This will fall through to the generic implementation
3012 case 'I': // Signed 16 bit constant
3013 // If this fails, the parent routine will give an error
3014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3015 EVT Type = Op.getValueType();
3016 int64_t Val = C->getSExtValue();
3017 if (isInt<16>(Val)) {
3018 Result = DAG.getTargetConstant(Val, Type);
3023 case 'J': // integer zero
3024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3025 EVT Type = Op.getValueType();
3026 int64_t Val = C->getZExtValue();
3028 Result = DAG.getTargetConstant(0, Type);
3033 case 'K': // unsigned 16 bit immediate
3034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3035 EVT Type = Op.getValueType();
3036 uint64_t Val = (uint64_t)C->getZExtValue();
3037 if (isUInt<16>(Val)) {
3038 Result = DAG.getTargetConstant(Val, Type);
3043 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3045 EVT Type = Op.getValueType();
3046 int64_t Val = C->getSExtValue();
3047 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3048 Result = DAG.getTargetConstant(Val, Type);
3053 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3055 EVT Type = Op.getValueType();
3056 int64_t Val = C->getSExtValue();
3057 if ((Val >= -65535) && (Val <= -1)) {
3058 Result = DAG.getTargetConstant(Val, Type);
3063 case 'O': // signed 15 bit immediate
3064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3065 EVT Type = Op.getValueType();
3066 int64_t Val = C->getSExtValue();
3067 if ((isInt<15>(Val))) {
3068 Result = DAG.getTargetConstant(Val, Type);
3073 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3074 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3075 EVT Type = Op.getValueType();
3076 int64_t Val = C->getSExtValue();
3077 if ((Val <= 65535) && (Val >= 1)) {
3078 Result = DAG.getTargetConstant(Val, Type);
3085 if (Result.getNode()) {
3086 Ops.push_back(Result);
3090 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3093 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3095 // No global is ever allowed as a base.
3100 case 0: // "r+i" or just "i", depending on HasBaseReg.
3103 if (!AM.HasBaseReg) // allow "r+i".
3105 return false; // disallow "r+r" or "r+r+i".
3114 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3115 // The Mips target isn't yet aware of offsets.
3119 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3121 bool IsMemset, bool ZeroMemset,
3123 MachineFunction &MF) const {
3124 if (Subtarget->hasMips64())
3130 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3131 if (VT != MVT::f32 && VT != MVT::f64)
3133 if (Imm.isNegZero())
3135 return Imm.isZero();
3138 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3140 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3142 return TargetLowering::getJumpTableEncoding();
3145 /// This function returns true if CallSym is a long double emulation routine.
3146 static bool isF128SoftLibCall(const char *CallSym) {
3147 const char *const LibCalls[] =
3148 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3149 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3150 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3151 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3152 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3153 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3154 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3155 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3158 const char *const *End = LibCalls + array_lengthof(LibCalls);
3160 // Check that LibCalls is sorted alphabetically.
3161 MipsTargetLowering::LTStr Comp;
3164 for (const char *const *I = LibCalls; I < End - 1; ++I)
3165 assert(Comp(*I, *(I + 1)));
3168 return std::binary_search(LibCalls, End, CallSym, Comp);
3171 /// This function returns true if Ty is fp128 or i128 which was originally a
3173 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3174 if (Ty->isFP128Ty())
3177 const ExternalSymbolSDNode *ES =
3178 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3180 // If the Ty is i128 and the function being called is a long double emulation
3181 // routine, then the original type is f128.
3182 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3185 MipsTargetLowering::MipsCC::SpecialCallingConvType
3186 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3187 MipsCC::SpecialCallingConvType SpecialCallingConv =
3188 MipsCC::NoSpecialCallingConv;;
3189 if (Subtarget->inMips16HardFloat()) {
3190 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3191 llvm::StringRef Sym = G->getGlobal()->getName();
3192 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3193 if (F->hasFnAttribute("__Mips16RetHelper")) {
3194 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3198 return SpecialCallingConv;
3201 MipsTargetLowering::MipsCC::MipsCC(
3202 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
3203 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3204 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
3205 SpecialCallingConv(SpecialCallingConv_){
3206 // Pre-allocate reserved argument area.
3207 CCInfo.AllocateStack(reservedArgArea(), 1);
3211 void MipsTargetLowering::MipsCC::
3212 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3213 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3214 std::vector<ArgListEntry> &FuncArgs) {
3215 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3216 "CallingConv::Fast shouldn't be used for vararg functions.");
3218 unsigned NumOpnds = Args.size();
3219 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3221 for (unsigned I = 0; I != NumOpnds; ++I) {
3222 MVT ArgVT = Args[I].VT;
3223 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3226 if (ArgFlags.isByVal()) {
3227 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3231 if (IsVarArg && !Args[I].IsFixed)
3232 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3234 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3236 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3241 dbgs() << "Call operand #" << I << " has unhandled type "
3242 << EVT(ArgVT).getEVTString();
3244 llvm_unreachable(0);
3249 void MipsTargetLowering::MipsCC::
3250 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3251 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3252 unsigned NumArgs = Args.size();
3253 llvm::CCAssignFn *FixedFn = fixedArgFn();
3254 unsigned CurArgIdx = 0;
3256 for (unsigned I = 0; I != NumArgs; ++I) {
3257 MVT ArgVT = Args[I].VT;
3258 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3259 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3260 CurArgIdx = Args[I].OrigArgIndex;
3262 if (ArgFlags.isByVal()) {
3263 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3267 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
3269 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3273 dbgs() << "Formal Arg #" << I << " has unhandled type "
3274 << EVT(ArgVT).getEVTString();
3276 llvm_unreachable(0);
3280 template<typename Ty>
3281 void MipsTargetLowering::MipsCC::
3282 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3283 const SDNode *CallNode, const Type *RetTy) const {
3286 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3287 Fn = RetCC_F128Soft;
3291 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3292 MVT VT = RetVals[I].VT;
3293 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3294 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3296 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3298 dbgs() << "Call result #" << I << " has unhandled type "
3299 << EVT(VT).getEVTString() << '\n';
3301 llvm_unreachable(0);
3306 void MipsTargetLowering::MipsCC::
3307 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3308 const SDNode *CallNode, const Type *RetTy) const {
3309 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3312 void MipsTargetLowering::MipsCC::
3313 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3314 const Type *RetTy) const {
3315 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
3318 void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3320 CCValAssign::LocInfo LocInfo,
3321 ISD::ArgFlagsTy ArgFlags) {
3322 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3324 struct ByValArgInfo ByVal;
3325 unsigned RegSize = regSize();
3326 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3327 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3330 if (useRegsForByval())
3331 allocateRegs(ByVal, ByValSize, Align);
3333 // Allocate space on caller's stack.
3334 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3336 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3338 ByValArgs.push_back(ByVal);
3341 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3342 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3345 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3346 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3349 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3350 return IsO32 ? O32IntRegs : Mips64IntRegs;
3353 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3354 if (CallConv == CallingConv::Fast)
3355 return CC_Mips_FastCC;
3357 if (SpecialCallingConv == Mips16RetHelperConv)
3358 return CC_Mips16RetHelper;
3359 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
3362 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3363 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
3366 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3367 return IsO32 ? O32IntRegs : Mips64DPRegs;
3370 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3373 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3374 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3375 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3376 "Byval argument's size and alignment should be a multiple of"
3379 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3381 // If Align > RegSize, the first arg register must be even.
3382 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3383 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3387 // Mark the registers allocated.
3388 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3389 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3390 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3393 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3394 const SDNode *CallNode,
3395 bool IsSoftFloat) const {
3396 if (IsSoftFloat || IsO32)
3399 // Check if the original type was fp128.
3400 if (originalTypeIsF128(OrigTy, CallNode)) {
3401 assert(VT == MVT::i64);
3408 void MipsTargetLowering::
3409 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3410 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3411 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3412 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3413 MachineFunction &MF = DAG.getMachineFunction();
3414 MachineFrameInfo *MFI = MF.getFrameInfo();
3415 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3416 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3420 FrameObjOffset = (int)CC.reservedArgArea() -
3421 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3423 FrameObjOffset = ByVal.Address;
3425 // Create frame object.
3426 EVT PtrTy = getPointerTy();
3427 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3428 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3429 InVals.push_back(FIN);
3434 // Copy arg registers.
3435 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3436 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3438 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3439 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3440 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3441 unsigned Offset = I * CC.regSize();
3442 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3443 DAG.getConstant(Offset, PtrTy));
3444 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3445 StorePtr, MachinePointerInfo(FuncArg, Offset),
3447 OutChains.push_back(Store);
3451 // Copy byVal arg to registers and stack.
3452 void MipsTargetLowering::
3453 passByValArg(SDValue Chain, SDLoc DL,
3454 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3455 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3456 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3457 const MipsCC &CC, const ByValArgInfo &ByVal,
3458 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3459 unsigned ByValSize = Flags.getByValSize();
3460 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3461 unsigned RegSize = CC.regSize();
3462 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3463 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3465 if (ByVal.NumRegs) {
3466 const uint16_t *ArgRegs = CC.intArgRegs();
3467 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3470 // Copy words to registers.
3471 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3472 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3473 DAG.getConstant(Offset, PtrTy));
3474 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3475 MachinePointerInfo(), false, false, false,
3477 MemOpChains.push_back(LoadVal.getValue(1));
3478 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3479 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3482 // Return if the struct has been fully copied.
3483 if (ByValSize == Offset)
3486 // Copy the remainder of the byval argument with sub-word loads and shifts.
3487 if (LeftoverBytes) {
3488 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3489 "Size of the remainder should be smaller than RegSize.");
3492 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3493 Offset < ByValSize; LoadSize /= 2) {
3494 unsigned RemSize = ByValSize - Offset;
3496 if (RemSize < LoadSize)
3500 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3501 DAG.getConstant(Offset, PtrTy));
3503 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3504 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3505 false, false, Alignment);
3506 MemOpChains.push_back(LoadVal.getValue(1));
3508 // Shift the loaded value.
3512 Shamt = TotalSizeLoaded;
3514 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3516 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3517 DAG.getConstant(Shamt, MVT::i32));
3520 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3525 TotalSizeLoaded += LoadSize;
3526 Alignment = std::min(Alignment, LoadSize);
3529 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3530 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3535 // Copy remainder of byval arg to it with memcpy.
3536 unsigned MemCpySize = ByValSize - Offset;
3537 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3538 DAG.getConstant(Offset, PtrTy));
3539 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3540 DAG.getIntPtrConstant(ByVal.Address));
3541 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
3542 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3543 MachinePointerInfo(0), MachinePointerInfo(0));
3544 MemOpChains.push_back(Chain);
3547 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3548 const MipsCC &CC, SDValue Chain,
3549 SDLoc DL, SelectionDAG &DAG) const {
3550 unsigned NumRegs = CC.numIntArgRegs();
3551 const uint16_t *ArgRegs = CC.intArgRegs();
3552 const CCState &CCInfo = CC.getCCInfo();
3553 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3554 unsigned RegSize = CC.regSize();
3555 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3556 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3557 MachineFunction &MF = DAG.getMachineFunction();
3558 MachineFrameInfo *MFI = MF.getFrameInfo();
3559 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3561 // Offset of the first variable argument from stack pointer.
3565 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3567 VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3569 // Record the frame index of the first variable argument
3570 // which is a value necessary to VASTART.
3571 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3572 MipsFI->setVarArgsFrameIndex(FI);
3574 // Copy the integer registers that have not been used for argument passing
3575 // to the argument register save area. For O32, the save area is allocated
3576 // in the caller's stack frame, while for N32/64, it is allocated in the
3577 // callee's stack frame.
3578 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3579 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3580 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3581 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3582 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3583 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3584 MachinePointerInfo(), false, false, 0);
3585 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3586 OutChains.push_back(Store);