1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
45 case MipsISD::FPCmp : return "MipsISD::FPCmp";
46 case MipsISD::CMovFP_T : return "MipsISD::CMovFP_T";
47 case MipsISD::CMovFP_F : return "MipsISD::CMovFP_F";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 case MipsISD::MAdd : return "MipsISD::MAdd";
50 case MipsISD::MAddu : return "MipsISD::MAddu";
51 case MipsISD::MSub : return "MipsISD::MSub";
52 case MipsISD::MSubu : return "MipsISD::MSubu";
53 case MipsISD::DivRem : return "MipsISD::DivRem";
54 case MipsISD::DivRemU : return "MipsISD::DivRemU";
55 default : return NULL;
60 MipsTargetLowering(MipsTargetMachine &TM)
61 : TargetLowering(TM, new MipsTargetObjectFile()) {
62 Subtarget = &TM.getSubtarget<MipsSubtarget>();
64 // Mips does not have i1 type, so use i32 for
65 // setcc operations results (slt, sgt, ...).
66 setBooleanContents(ZeroOrOneBooleanContent);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat())
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
77 // Load extented operations for i1 types must be promoted
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
82 // MIPS doesn't have extending float->double load/store
83 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
95 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
102 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
104 setOperationAction(ISD::VASTART, MVT::Other, Custom);
106 setOperationAction(ISD::SDIV, MVT::i32, Expand);
107 setOperationAction(ISD::SREM, MVT::i32, Expand);
108 setOperationAction(ISD::UDIV, MVT::i32, Expand);
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
111 // Operations not directly supported by Mips.
112 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
113 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
115 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
116 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
118 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
120 setOperationAction(ISD::ROTL, MVT::i32, Expand);
122 if (!Subtarget->isMips32r2())
123 setOperationAction(ISD::ROTR, MVT::i32, Expand);
125 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
129 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
130 setOperationAction(ISD::FSIN, MVT::f32, Expand);
131 setOperationAction(ISD::FSIN, MVT::f64, Expand);
132 setOperationAction(ISD::FCOS, MVT::f32, Expand);
133 setOperationAction(ISD::FCOS, MVT::f64, Expand);
134 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
135 setOperationAction(ISD::FPOW, MVT::f32, Expand);
136 setOperationAction(ISD::FLOG, MVT::f32, Expand);
137 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
139 setOperationAction(ISD::FEXP, MVT::f32, Expand);
141 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
143 setOperationAction(ISD::VAARG, MVT::Other, Expand);
144 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
145 setOperationAction(ISD::VAEND, MVT::Other, Expand);
147 // Use the default for now
148 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
149 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
150 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
152 if (Subtarget->isSingleFloat())
153 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
155 if (!Subtarget->hasSEInReg()) {
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
160 if (!Subtarget->hasBitCount())
161 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
163 if (!Subtarget->hasSwap())
164 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
166 setTargetDAGCombine(ISD::ADDE);
167 setTargetDAGCombine(ISD::SUBE);
168 setTargetDAGCombine(ISD::SDIVREM);
169 setTargetDAGCombine(ISD::UDIVREM);
170 setTargetDAGCombine(ISD::SETCC);
172 setStackPointerRegisterToSaveRestore(Mips::SP);
173 computeRegisterProperties();
176 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
180 /// getFunctionAlignment - Return the Log2 alignment of this function.
181 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
186 // Transforms a subgraph in CurDAG if the following pattern is found:
187 // (addc multLo, Lo0), (adde multHi, Hi0),
189 // multHi/Lo: product of multiplication
190 // Lo0: initial value of Lo register
191 // Hi0: initial value of Hi register
192 // Return true if pattern matching was successful.
193 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
194 // ADDENode's second operand must be a flag output of an ADDC node in order
195 // for the matching to be successful.
196 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
198 if (ADDCNode->getOpcode() != ISD::ADDC)
201 SDValue MultHi = ADDENode->getOperand(0);
202 SDValue MultLo = ADDCNode->getOperand(0);
203 SDNode* MultNode = MultHi.getNode();
204 unsigned MultOpc = MultHi.getOpcode();
206 // MultHi and MultLo must be generated by the same node,
207 if (MultLo.getNode() != MultNode)
210 // and it must be a multiplication.
211 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
214 // MultLo amd MultHi must be the first and second output of MultNode
216 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
219 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
220 // of the values of MultNode, in which case MultNode will be removed in later
222 // If there exist users other than ADDENode or ADDCNode, this function returns
223 // here, which will result in MultNode being mapped to a single MULT
224 // instruction node rather than a pair of MULT and MADD instructions being
226 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
229 SDValue Chain = CurDAG->getEntryNode();
230 DebugLoc dl = ADDENode->getDebugLoc();
232 // create MipsMAdd(u) node
233 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
235 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
237 MultNode->getOperand(0),// Factor 0
238 MultNode->getOperand(1),// Factor 1
239 ADDCNode->getOperand(1),// Lo0
240 ADDENode->getOperand(1));// Hi0
242 // create CopyFromReg nodes
243 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
245 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
247 CopyFromLo.getValue(2));
249 // replace uses of adde and addc here
250 if (!SDValue(ADDCNode, 0).use_empty())
251 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
253 if (!SDValue(ADDENode, 0).use_empty())
254 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
260 // Transforms a subgraph in CurDAG if the following pattern is found:
261 // (addc Lo0, multLo), (sube Hi0, multHi),
263 // multHi/Lo: product of multiplication
264 // Lo0: initial value of Lo register
265 // Hi0: initial value of Hi register
266 // Return true if pattern matching was successful.
267 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
268 // SUBENode's second operand must be a flag output of an SUBC node in order
269 // for the matching to be successful.
270 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
272 if (SUBCNode->getOpcode() != ISD::SUBC)
275 SDValue MultHi = SUBENode->getOperand(1);
276 SDValue MultLo = SUBCNode->getOperand(1);
277 SDNode* MultNode = MultHi.getNode();
278 unsigned MultOpc = MultHi.getOpcode();
280 // MultHi and MultLo must be generated by the same node,
281 if (MultLo.getNode() != MultNode)
284 // and it must be a multiplication.
285 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
288 // MultLo amd MultHi must be the first and second output of MultNode
290 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
293 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
294 // of the values of MultNode, in which case MultNode will be removed in later
296 // If there exist users other than SUBENode or SUBCNode, this function returns
297 // here, which will result in MultNode being mapped to a single MULT
298 // instruction node rather than a pair of MULT and MSUB instructions being
300 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
303 SDValue Chain = CurDAG->getEntryNode();
304 DebugLoc dl = SUBENode->getDebugLoc();
306 // create MipsSub(u) node
307 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
309 SDValue MSub = CurDAG->getNode(MultOpc, dl,
311 MultNode->getOperand(0),// Factor 0
312 MultNode->getOperand(1),// Factor 1
313 SUBCNode->getOperand(0),// Lo0
314 SUBENode->getOperand(0));// Hi0
316 // create CopyFromReg nodes
317 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
319 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
321 CopyFromLo.getValue(2));
323 // replace uses of sube and subc here
324 if (!SDValue(SUBCNode, 0).use_empty())
325 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
327 if (!SDValue(SUBENode, 0).use_empty())
328 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
333 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
334 TargetLowering::DAGCombinerInfo &DCI,
335 const MipsSubtarget* Subtarget) {
336 if (DCI.isBeforeLegalize())
339 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
340 return SDValue(N, 0);
345 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
346 TargetLowering::DAGCombinerInfo &DCI,
347 const MipsSubtarget* Subtarget) {
348 if (DCI.isBeforeLegalize())
351 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
352 return SDValue(N, 0);
357 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
358 TargetLowering::DAGCombinerInfo &DCI,
359 const MipsSubtarget* Subtarget) {
360 if (DCI.isBeforeLegalizeOps())
363 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
365 DebugLoc dl = N->getDebugLoc();
367 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
368 N->getOperand(0), N->getOperand(1));
369 SDValue InChain = DAG.getEntryNode();
370 SDValue InGlue = DivRem;
373 if (N->hasAnyUseOfValue(0)) {
374 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
376 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
377 InChain = CopyFromLo.getValue(1);
378 InGlue = CopyFromLo.getValue(2);
382 if (N->hasAnyUseOfValue(1)) {
383 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
384 Mips::HI, MVT::i32, InGlue);
385 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
391 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
393 default: llvm_unreachable("Unknown fp condition code!");
395 case ISD::SETOEQ: return Mips::FCOND_OEQ;
396 case ISD::SETUNE: return Mips::FCOND_UNE;
398 case ISD::SETOLT: return Mips::FCOND_OLT;
400 case ISD::SETOGT: return Mips::FCOND_OGT;
402 case ISD::SETOLE: return Mips::FCOND_OLE;
404 case ISD::SETOGE: return Mips::FCOND_OGE;
405 case ISD::SETULT: return Mips::FCOND_ULT;
406 case ISD::SETULE: return Mips::FCOND_ULE;
407 case ISD::SETUGT: return Mips::FCOND_UGT;
408 case ISD::SETUGE: return Mips::FCOND_UGE;
409 case ISD::SETUO: return Mips::FCOND_UN;
410 case ISD::SETO: return Mips::FCOND_OR;
412 case ISD::SETONE: return Mips::FCOND_ONE;
413 case ISD::SETUEQ: return Mips::FCOND_UEQ;
418 // Returns true if condition code has to be inverted.
419 static bool InvertFPCondCode(Mips::CondCode CC) {
420 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
423 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
426 assert(false && "Illegal Condition Code");
430 // Creates and returns an FPCmp node from a setcc node.
431 // Returns Op if setcc is not a floating point comparison.
432 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
433 // must be a SETCC node
434 if (Op.getOpcode() != ISD::SETCC)
437 SDValue LHS = Op.getOperand(0);
439 if (!LHS.getValueType().isFloatingPoint())
442 SDValue RHS = Op.getOperand(1);
443 DebugLoc dl = Op.getDebugLoc();
445 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of node
447 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
449 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
450 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
453 // Creates and returns a CMovFPT/F node.
454 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
455 SDValue False, DebugLoc DL) {
456 bool invert = InvertFPCondCode((Mips::CondCode)
457 cast<ConstantSDNode>(Cond.getOperand(2))
460 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
461 True.getValueType(), True, False, Cond);
464 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
465 TargetLowering::DAGCombinerInfo &DCI,
466 const MipsSubtarget* Subtarget) {
467 if (DCI.isBeforeLegalizeOps())
470 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
472 if (Cond.getOpcode() != MipsISD::FPCmp)
475 SDValue True = DAG.getConstant(1, MVT::i32);
476 SDValue False = DAG.getConstant(0, MVT::i32);
478 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
481 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
483 SelectionDAG &DAG = DCI.DAG;
484 unsigned opc = N->getOpcode();
489 return PerformADDECombine(N, DAG, DCI, Subtarget);
491 return PerformSUBECombine(N, DAG, DCI, Subtarget);
494 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
496 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
502 SDValue MipsTargetLowering::
503 LowerOperation(SDValue Op, SelectionDAG &DAG) const
505 switch (Op.getOpcode())
507 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
508 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
509 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
510 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
511 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
512 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
513 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
514 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
515 case ISD::SELECT: return LowerSELECT(Op, DAG);
516 case ISD::VASTART: return LowerVASTART(Op, DAG);
521 //===----------------------------------------------------------------------===//
522 // Lower helper functions
523 //===----------------------------------------------------------------------===//
525 // AddLiveIn - This helper function adds the specified physical register to the
526 // MachineFunction as a live in value. It also creates a corresponding
527 // virtual register for it.
529 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
531 assert(RC->contains(PReg) && "Not the correct regclass!");
532 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
533 MF.getRegInfo().addLiveIn(PReg, VReg);
537 // Get fp branch code (not opcode) from condition code.
538 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
539 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
540 return Mips::BRANCH_T;
542 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
543 return Mips::BRANCH_F;
545 return Mips::BRANCH_INVALID;
549 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
550 MachineBasicBlock *BB) const {
551 // There is no need to expand CMov instructions if target has
552 // conditional moves.
553 if (Subtarget->hasCondMov())
556 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
557 bool isFPCmp = false;
558 DebugLoc dl = MI->getDebugLoc();
561 switch (MI->getOpcode()) {
562 default: assert(false && "Unexpected instr type to insert");
587 // To "insert" a SELECT_CC instruction, we actually have to insert the
588 // diamond control-flow pattern. The incoming instruction knows the
589 // destination vreg to set, the condition code register to branch on, the
590 // true/false values to select between, and a branch opcode to use.
591 const BasicBlock *LLVM_BB = BB->getBasicBlock();
592 MachineFunction::iterator It = BB;
599 // bNE r1, r0, copy1MBB
600 // fallthrough --> copy0MBB
601 MachineBasicBlock *thisMBB = BB;
602 MachineFunction *F = BB->getParent();
603 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
604 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
605 F->insert(It, copy0MBB);
606 F->insert(It, sinkMBB);
608 // Transfer the remainder of BB and its successor edges to sinkMBB.
609 sinkMBB->splice(sinkMBB->begin(), BB,
610 llvm::next(MachineBasicBlock::iterator(MI)),
612 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
614 // Next, add the true and fallthrough blocks as its successors.
615 BB->addSuccessor(copy0MBB);
616 BB->addSuccessor(sinkMBB);
618 // Emit the right instruction according to the type of the operands compared
620 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
622 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
623 .addReg(Mips::ZERO).addMBB(sinkMBB);
628 // # fallthrough to sinkMBB
631 // Update machine-CFG edges
632 BB->addSuccessor(sinkMBB);
635 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
640 BuildMI(*BB, BB->begin(), dl,
641 TII->get(Mips::PHI), MI->getOperand(0).getReg())
642 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
643 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
645 BuildMI(*BB, BB->begin(), dl,
646 TII->get(Mips::PHI), MI->getOperand(0).getReg())
647 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
648 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
650 MI->eraseFromParent(); // The pseudo instruction is gone now.
654 //===----------------------------------------------------------------------===//
655 // Misc Lower Operation implementation
656 //===----------------------------------------------------------------------===//
658 SDValue MipsTargetLowering::
659 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
661 if (!Subtarget->isMips1())
664 MachineFunction &MF = DAG.getMachineFunction();
665 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
667 SDValue Chain = DAG.getEntryNode();
668 DebugLoc dl = Op.getDebugLoc();
669 SDValue Src = Op.getOperand(0);
671 // Set the condition register
672 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
673 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
674 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
676 SDValue Cst = DAG.getConstant(3, MVT::i32);
677 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
678 Cst = DAG.getConstant(2, MVT::i32);
679 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
681 SDValue InFlag(0, 0);
682 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
684 // Emit the round instruction and bit convert to integer
685 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
686 Src, CondReg.getValue(1));
687 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
691 SDValue MipsTargetLowering::
692 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
694 SDValue Chain = Op.getOperand(0);
695 SDValue Size = Op.getOperand(1);
696 DebugLoc dl = Op.getDebugLoc();
698 // Get a reference from Mips stack pointer
699 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
701 // Subtract the dynamic size from the actual stack size to
702 // obtain the new stack size.
703 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
705 // The Sub result contains the new stack start address, so it
706 // must be placed in the stack pointer register.
707 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
709 // This node always has two return values: a new stack pointer
711 SDValue Ops[2] = { Sub, Chain };
712 return DAG.getMergeValues(Ops, 2, dl);
715 SDValue MipsTargetLowering::
716 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
718 // The first operand is the chain, the second is the condition, the third is
719 // the block to branch to if the condition is true.
720 SDValue Chain = Op.getOperand(0);
721 SDValue Dest = Op.getOperand(2);
722 DebugLoc dl = Op.getDebugLoc();
724 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
726 // Return if flag is not set by a floating point comparision.
727 if (CondRes.getOpcode() != MipsISD::FPCmp)
730 SDValue CCNode = CondRes.getOperand(2);
732 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
733 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
735 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
739 SDValue MipsTargetLowering::
740 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
742 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
744 // Return if flag is not set by a floating point comparision.
745 if (Cond.getOpcode() != MipsISD::FPCmp)
748 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
752 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
753 SelectionDAG &DAG) const {
754 // FIXME there isn't actually debug info here
755 DebugLoc dl = Op.getDebugLoc();
756 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
758 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
759 SDVTList VTs = DAG.getVTList(MVT::i32);
761 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
763 // %gp_rel relocation
764 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
765 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
767 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
768 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
769 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
771 // %hi/%lo relocation
772 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
774 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
776 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
777 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
778 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
780 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
782 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
783 DAG.getEntryNode(), GA, MachinePointerInfo(),
785 // On functions and global targets not internal linked only
786 // a load from got/GP is necessary for PIC to work.
787 if (!GV->hasInternalLinkage() &&
788 (!GV->hasLocalLinkage() || isa<Function>(GV)))
790 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
792 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
793 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
796 llvm_unreachable("Dont know how to handle GlobalAddress");
800 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
801 SelectionDAG &DAG) const {
802 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
803 assert(false && "implement LowerBlockAddress for -static");
804 return SDValue(0, 0);
807 // FIXME there isn't actually debug info here
808 DebugLoc dl = Op.getDebugLoc();
809 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
810 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
812 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
814 SDValue Load = DAG.getLoad(MVT::i32, dl,
815 DAG.getEntryNode(), BAGOTOffset,
816 MachinePointerInfo(), false, false, 0);
817 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
818 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
822 SDValue MipsTargetLowering::
823 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
825 llvm_unreachable("TLS not implemented for MIPS.");
826 return SDValue(); // Not reached
829 SDValue MipsTargetLowering::
830 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
834 // FIXME there isn't actually debug info here
835 DebugLoc dl = Op.getDebugLoc();
836 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
837 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
839 EVT PtrVT = Op.getValueType();
840 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
842 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
845 SDValue Ops[] = { JTI };
846 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
847 } else // Emit Load from Global Pointer
848 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
849 MachinePointerInfo(),
852 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
853 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
854 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
859 SDValue MipsTargetLowering::
860 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
863 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
864 const Constant *C = N->getConstVal();
865 // FIXME there isn't actually debug info here
866 DebugLoc dl = Op.getDebugLoc();
869 // FIXME: we should reference the constant pool using small data sections,
870 // but the asm printer currently doens't support this feature without
871 // hacking it. This feature should come soon so we can uncomment the
873 //if (IsInSmallSection(C->getType())) {
874 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
875 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
876 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
878 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
879 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
880 N->getOffset(), MipsII::MO_ABS_HI);
881 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
882 N->getOffset(), MipsII::MO_ABS_LO);
883 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
884 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
885 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
887 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
888 N->getOffset(), MipsII::MO_GOT);
889 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
890 CP, MachinePointerInfo::getConstantPool(),
892 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
893 N->getOffset(), MipsII::MO_ABS_LO);
894 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
895 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
901 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
902 MachineFunction &MF = DAG.getMachineFunction();
903 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
905 DebugLoc dl = Op.getDebugLoc();
906 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
909 // vastart just stores the address of the VarArgsFrameIndex slot into the
910 // memory location argument.
911 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
912 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
913 MachinePointerInfo(SV),
917 //===----------------------------------------------------------------------===//
918 // Calling Convention Implementation
919 //===----------------------------------------------------------------------===//
921 #include "MipsGenCallingConv.inc"
923 //===----------------------------------------------------------------------===//
924 // TODO: Implement a generic logic using tblgen that can support this.
925 // Mips O32 ABI rules:
927 // i32 - Passed in A0, A1, A2, A3 and stack
928 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
929 // an argument. Otherwise, passed in A1, A2, A3 and stack.
930 // f64 - Only passed in two aliased f32 registers if no int reg has been used
931 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
932 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
934 //===----------------------------------------------------------------------===//
936 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
937 MVT LocVT, CCValAssign::LocInfo LocInfo,
938 ISD::ArgFlagsTy ArgFlags, CCState &State) {
940 static const unsigned IntRegsSize=4, FloatRegsSize=2;
942 static const unsigned IntRegs[] = {
943 Mips::A0, Mips::A1, Mips::A2, Mips::A3
945 static const unsigned F32Regs[] = {
948 static const unsigned F64Regs[] = {
953 static bool IntRegUsed = false;
955 // This must be the first arg of the call if no regs have been allocated.
956 // Initialize IntRegUsed in that case.
957 if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
958 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
959 F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
962 // Promote i8 and i16
963 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
965 if (ArgFlags.isSExt())
966 LocInfo = CCValAssign::SExt;
967 else if (ArgFlags.isZExt())
968 LocInfo = CCValAssign::ZExt;
970 LocInfo = CCValAssign::AExt;
973 if (ValVT == MVT::i32) {
974 Reg = State.AllocateReg(IntRegs, IntRegsSize);
976 } else if (ValVT == MVT::f32) {
977 // An int reg has to be marked allocated regardless of whether or not
978 // IntRegUsed is true.
979 Reg = State.AllocateReg(IntRegs, IntRegsSize);
982 if (Reg) // Int reg is available
985 unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize);
986 if (FReg) // F32 reg is available
988 else if (Reg) // No F32 regs are available, but an int reg is available.
991 } else if (ValVT == MVT::f64) {
992 // Int regs have to be marked allocated regardless of whether or not
993 // IntRegUsed is true.
994 Reg = State.AllocateReg(IntRegs, IntRegsSize);
996 Reg = State.AllocateReg(IntRegs, IntRegsSize);
997 else if (Reg == Mips::A3)
999 State.AllocateReg(IntRegs, IntRegsSize);
1001 // At this point, Reg is A0, A2 or 0, and all the unavailable integer regs
1002 // are marked as allocated.
1004 if (Reg)// if int reg is available
1007 unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize);
1008 if (FReg) // F64 reg is available.
1010 else if (Reg) // No F64 regs are available, but an int reg is available.
1014 assert(false && "cannot handle this ValVT");
1017 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1018 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1019 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1021 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1023 return false; // CC must always match
1026 static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
1027 MVT LocVT, CCValAssign::LocInfo LocInfo,
1028 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1030 static const unsigned IntRegsSize=4;
1032 static const unsigned IntRegs[] = {
1033 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1036 // Promote i8 and i16
1037 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1039 if (ArgFlags.isSExt())
1040 LocInfo = CCValAssign::SExt;
1041 else if (ArgFlags.isZExt())
1042 LocInfo = CCValAssign::ZExt;
1044 LocInfo = CCValAssign::AExt;
1049 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
1050 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1052 } else if (ValVT == MVT::f64) {
1053 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1054 if (Reg == Mips::A1 || Reg == Mips::A3)
1055 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1056 State.AllocateReg(IntRegs, IntRegsSize);
1059 llvm_unreachable("Cannot handle this ValVT.");
1062 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1063 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1064 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1066 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1068 return false; // CC must always match
1071 //===----------------------------------------------------------------------===//
1072 // Call Calling Convention Implementation
1073 //===----------------------------------------------------------------------===//
1075 /// LowerCall - functions arguments are copied from virtual regs to
1076 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1077 /// TODO: isTailCall.
1079 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1080 CallingConv::ID CallConv, bool isVarArg,
1082 const SmallVectorImpl<ISD::OutputArg> &Outs,
1083 const SmallVectorImpl<SDValue> &OutVals,
1084 const SmallVectorImpl<ISD::InputArg> &Ins,
1085 DebugLoc dl, SelectionDAG &DAG,
1086 SmallVectorImpl<SDValue> &InVals) const {
1087 // MIPs target does not yet support tail call optimization.
1090 MachineFunction &MF = DAG.getMachineFunction();
1091 MachineFrameInfo *MFI = MF.getFrameInfo();
1092 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1094 // Analyze operands of the call, assigning locations to each operand.
1095 SmallVector<CCValAssign, 16> ArgLocs;
1096 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1099 // To meet O32 ABI, Mips must always allocate 16 bytes on
1100 // the stack (even if less than 4 are used as arguments)
1101 if (Subtarget->isABI_O32()) {
1102 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
1103 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
1104 CCInfo.AnalyzeCallOperands(Outs,
1105 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1107 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1109 // Get a count of how many bytes are to be pushed on the stack.
1110 unsigned NumBytes = CCInfo.getNextStackOffset();
1111 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1113 // With EABI is it possible to have 16 args on registers.
1114 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1115 SmallVector<SDValue, 8> MemOpChains;
1117 // First/LastArgStackLoc contains the first/last
1118 // "at stack" argument location.
1119 int LastArgStackLoc = 0;
1120 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1122 // Walk the register/memloc assignments, inserting copies/loads.
1123 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1124 SDValue Arg = OutVals[i];
1125 CCValAssign &VA = ArgLocs[i];
1127 // Promote the value if needed.
1128 switch (VA.getLocInfo()) {
1129 default: llvm_unreachable("Unknown loc info!");
1130 case CCValAssign::Full:
1131 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1132 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1133 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1134 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1135 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1136 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1137 DAG.getConstant(0, getPointerTy()));
1138 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1139 DAG.getConstant(1, getPointerTy()));
1140 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1141 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1146 case CCValAssign::SExt:
1147 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1149 case CCValAssign::ZExt:
1150 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1152 case CCValAssign::AExt:
1153 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1157 // Arguments that can be passed on register must be kept at
1158 // RegsToPass vector
1159 if (VA.isRegLoc()) {
1160 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1164 // Register can't get to this point...
1165 assert(VA.isMemLoc());
1167 // Create the frame index object for this incoming parameter
1168 // This guarantees that when allocating Local Area the firsts
1169 // 16 bytes which are alwayes reserved won't be overwritten
1170 // if O32 ABI is used. For EABI the first address is zero.
1171 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
1172 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1173 LastArgStackLoc, true);
1175 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
1177 // emit ISD::STORE whichs stores the
1178 // parameter value to a stack Location
1179 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1180 MachinePointerInfo(),
1184 // Transform all store nodes into one single node because all store
1185 // nodes are independent of each other.
1186 if (!MemOpChains.empty())
1187 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1188 &MemOpChains[0], MemOpChains.size());
1190 // Build a sequence of copy-to-reg nodes chained together with token
1191 // chain and flag operands which copy the outgoing args into registers.
1192 // The InFlag in necessary since all emited instructions must be
1195 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1196 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1197 RegsToPass[i].second, InFlag);
1198 InFlag = Chain.getValue(1);
1201 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1202 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1203 // node so that legalize doesn't hack it.
1204 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1205 bool LoadSymAddr = false;
1208 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1209 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1210 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1211 getPointerTy(), 0,MipsII:: MO_GOT);
1212 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1213 0, MipsII::MO_ABS_LO);
1215 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1216 getPointerTy(), 0, OpFlag);
1221 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1222 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1223 getPointerTy(), OpFlag);
1227 // Create nodes that load address of callee and copy it to T9
1230 // Load callee address
1231 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1232 MachinePointerInfo::getGOT(),
1235 // Use GOT+LO if callee has internal linkage.
1236 if (CalleeLo.getNode()) {
1237 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1238 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1242 // Use chain output from LoadValue
1243 Chain = LoadValue.getValue(1);
1247 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1248 InFlag = Chain.getValue(1);
1249 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1252 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1253 // = Chain, Callee, Reg#1, Reg#2, ...
1255 // Returns a chain & a flag for retval copy to use.
1256 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1257 SmallVector<SDValue, 8> Ops;
1258 Ops.push_back(Chain);
1259 Ops.push_back(Callee);
1261 // Add argument registers to the end of the list so that they are
1262 // known live into the call.
1263 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1264 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1265 RegsToPass[i].second.getValueType()));
1267 if (InFlag.getNode())
1268 Ops.push_back(InFlag);
1270 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1271 InFlag = Chain.getValue(1);
1273 // Create a stack location to hold GP when PIC is used. This stack
1274 // location is used on function prologue to save GP and also after all
1275 // emited CALL's to restore GP.
1277 // Function can have an arbitrary number of calls, so
1278 // hold the LastArgStackLoc with the biggest offset.
1280 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1281 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
1282 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
1283 // Create the frame index only once. SPOffset here can be anything
1284 // (this will be fixed on processFunctionBeforeFrameFinalized)
1285 if (MipsFI->getGPStackOffset() == -1) {
1286 FI = MFI->CreateFixedObject(4, 0, true);
1287 MipsFI->setGPFI(FI);
1289 MipsFI->setGPStackOffset(LastArgStackLoc);
1293 FI = MipsFI->getGPFI();
1294 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1295 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
1296 MachinePointerInfo::getFixedStack(FI),
1298 Chain = GPLoad.getValue(1);
1299 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
1300 GPLoad, SDValue(0,0));
1301 InFlag = Chain.getValue(1);
1304 // Create the CALLSEQ_END node.
1305 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1306 DAG.getIntPtrConstant(0, true), InFlag);
1307 InFlag = Chain.getValue(1);
1309 // Handle result values, copying them out of physregs into vregs that we
1311 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1312 Ins, dl, DAG, InVals);
1315 /// LowerCallResult - Lower the result values of a call into the
1316 /// appropriate copies out of appropriate physical registers.
1318 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1319 CallingConv::ID CallConv, bool isVarArg,
1320 const SmallVectorImpl<ISD::InputArg> &Ins,
1321 DebugLoc dl, SelectionDAG &DAG,
1322 SmallVectorImpl<SDValue> &InVals) const {
1324 // Assign locations to each value returned by this call.
1325 SmallVector<CCValAssign, 16> RVLocs;
1326 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1327 RVLocs, *DAG.getContext());
1329 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1331 // Copy all of the result registers out of their specified physreg.
1332 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1333 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1334 RVLocs[i].getValVT(), InFlag).getValue(1);
1335 InFlag = Chain.getValue(2);
1336 InVals.push_back(Chain.getValue(0));
1342 //===----------------------------------------------------------------------===//
1343 // Formal Arguments Calling Convention Implementation
1344 //===----------------------------------------------------------------------===//
1346 /// LowerFormalArguments - transform physical registers into virtual registers
1347 /// and generate load operations for arguments places on the stack.
1349 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1350 CallingConv::ID CallConv, bool isVarArg,
1351 const SmallVectorImpl<ISD::InputArg>
1353 DebugLoc dl, SelectionDAG &DAG,
1354 SmallVectorImpl<SDValue> &InVals)
1357 MachineFunction &MF = DAG.getMachineFunction();
1358 MachineFrameInfo *MFI = MF.getFrameInfo();
1359 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1361 MipsFI->setVarArgsFrameIndex(0);
1363 // Used with vargs to acumulate store chains.
1364 std::vector<SDValue> OutChains;
1366 // Keep track of the last register used for arguments
1367 unsigned ArgRegEnd = 0;
1369 // Assign locations to all of the incoming arguments.
1370 SmallVector<CCValAssign, 16> ArgLocs;
1371 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1372 ArgLocs, *DAG.getContext());
1374 if (Subtarget->isABI_O32())
1375 CCInfo.AnalyzeFormalArguments(Ins,
1376 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1378 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1380 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1381 unsigned LastStackArgEndOffset = 0;
1382 EVT LastRegArgValVT;
1384 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1385 CCValAssign &VA = ArgLocs[i];
1387 // Arguments stored on registers
1388 if (VA.isRegLoc()) {
1389 EVT RegVT = VA.getLocVT();
1390 ArgRegEnd = VA.getLocReg();
1391 LastRegArgValVT = VA.getValVT();
1392 TargetRegisterClass *RC = 0;
1394 if (RegVT == MVT::i32)
1395 RC = Mips::CPURegsRegisterClass;
1396 else if (RegVT == MVT::f32)
1397 RC = Mips::FGR32RegisterClass;
1398 else if (RegVT == MVT::f64) {
1399 if (!Subtarget->isSingleFloat())
1400 RC = Mips::AFGR64RegisterClass;
1402 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1404 // Transform the arguments stored on
1405 // physical registers into virtual ones
1406 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1407 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1409 // If this is an 8 or 16-bit value, it has been passed promoted
1410 // to 32 bits. Insert an assert[sz]ext to capture this, then
1411 // truncate to the right size.
1412 if (VA.getLocInfo() != CCValAssign::Full) {
1413 unsigned Opcode = 0;
1414 if (VA.getLocInfo() == CCValAssign::SExt)
1415 Opcode = ISD::AssertSext;
1416 else if (VA.getLocInfo() == CCValAssign::ZExt)
1417 Opcode = ISD::AssertZext;
1419 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1420 DAG.getValueType(VA.getValVT()));
1421 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1424 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1425 if (Subtarget->isABI_O32()) {
1426 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1427 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1428 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1429 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1430 VA.getLocReg()+1, RC);
1431 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1432 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, ArgValue,
1434 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Pair);
1438 InVals.push_back(ArgValue);
1439 } else { // VA.isRegLoc()
1442 assert(VA.isMemLoc());
1444 // The last argument is not a register anymore
1447 // The stack pointer offset is relative to the caller stack frame.
1448 // Since the real stack size is unknown here, a negative SPOffset
1449 // is used so there's a way to adjust these offsets when the stack
1450 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1451 // used instead of a direct negative address (which is recorded to
1452 // be used on emitPrologue) to avoid mis-calc of the first stack
1453 // offset on PEI::calculateFrameObjectOffsets.
1454 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1455 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
1456 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1457 MipsFI->recordLoadArgsFI(FI, -(4 +
1458 (FirstStackArgLoc + VA.getLocMemOffset())));
1460 // Create load nodes to retrieve arguments from the stack
1461 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1462 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1463 MachinePointerInfo::getFixedStack(FI),
1468 // The mips ABIs for returning structs by value requires that we copy
1469 // the sret argument into $v0 for the return. Save the argument into
1470 // a virtual register so that we can access it from the return points.
1471 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1472 unsigned Reg = MipsFI->getSRetReturnReg();
1474 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1475 MipsFI->setSRetReturnReg(Reg);
1477 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1478 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1481 // To meet ABI, when VARARGS are passed on registers, the registers
1482 // must have their values written to the caller stack frame. If the last
1483 // argument was placed in the stack, there's no need to save any register.
1484 if (isVarArg && Subtarget->isABI_O32()) {
1486 // Last named formal argument is passed in register.
1488 // The last register argument that must be saved is Mips::A3
1489 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1490 if (LastRegArgValVT == MVT::f64)
1493 if (ArgRegEnd < Mips::A3) {
1494 // Both the last named formal argument and the first variable
1495 // argument are passed in registers.
1496 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd) {
1497 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1498 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1500 int FI = MFI->CreateFixedObject(4, 0, true);
1501 MipsFI->recordStoreVarArgsFI(FI, -(4+(ArgRegEnd-Mips::A0)*4));
1502 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1503 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1504 MachinePointerInfo(),
1507 // Record the frame index of the first variable argument
1508 // which is a value necessary to VASTART.
1509 if (!MipsFI->getVarArgsFrameIndex()) {
1510 MFI->setObjectAlignment(FI, 4);
1511 MipsFI->setVarArgsFrameIndex(FI);
1515 // Last named formal argument is in register Mips::A3, and the first
1516 // variable argument is on stack. Record the frame index of the first
1517 // variable argument.
1518 int FI = MFI->CreateFixedObject(4, 0, true);
1519 MFI->setObjectAlignment(FI, 4);
1520 MipsFI->recordStoreVarArgsFI(FI, -20);
1521 MipsFI->setVarArgsFrameIndex(FI);
1524 // Last named formal argument and all the variable arguments are passed
1525 // on stack. Record the frame index of the first variable argument.
1526 int FI = MFI->CreateFixedObject(4, 0, true);
1527 MFI->setObjectAlignment(FI, 4);
1528 MipsFI->recordStoreVarArgsFI(FI, -(4+LastStackArgEndOffset));
1529 MipsFI->setVarArgsFrameIndex(FI);
1533 // All stores are grouped in one node to allow the matching between
1534 // the size of Ins and InVals. This only happens when on varg functions
1535 if (!OutChains.empty()) {
1536 OutChains.push_back(Chain);
1537 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1538 &OutChains[0], OutChains.size());
1544 //===----------------------------------------------------------------------===//
1545 // Return Value Calling Convention Implementation
1546 //===----------------------------------------------------------------------===//
1549 MipsTargetLowering::LowerReturn(SDValue Chain,
1550 CallingConv::ID CallConv, bool isVarArg,
1551 const SmallVectorImpl<ISD::OutputArg> &Outs,
1552 const SmallVectorImpl<SDValue> &OutVals,
1553 DebugLoc dl, SelectionDAG &DAG) const {
1555 // CCValAssign - represent the assignment of
1556 // the return value to a location
1557 SmallVector<CCValAssign, 16> RVLocs;
1559 // CCState - Info about the registers and stack slot.
1560 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1561 RVLocs, *DAG.getContext());
1563 // Analize return values.
1564 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1566 // If this is the first return lowered for this function, add
1567 // the regs to the liveout set for the function.
1568 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1569 for (unsigned i = 0; i != RVLocs.size(); ++i)
1570 if (RVLocs[i].isRegLoc())
1571 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1576 // Copy the result values into the output registers.
1577 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1578 CCValAssign &VA = RVLocs[i];
1579 assert(VA.isRegLoc() && "Can only return in registers!");
1581 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1584 // guarantee that all emitted copies are
1585 // stuck together, avoiding something bad
1586 Flag = Chain.getValue(1);
1589 // The mips ABIs for returning structs by value requires that we copy
1590 // the sret argument into $v0 for the return. We saved the argument into
1591 // a virtual register in the entry block, so now we copy the value out
1593 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1594 MachineFunction &MF = DAG.getMachineFunction();
1595 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1596 unsigned Reg = MipsFI->getSRetReturnReg();
1599 llvm_unreachable("sret virtual register not created in the entry block");
1600 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1602 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1603 Flag = Chain.getValue(1);
1606 // Return on Mips is always a "jr $ra"
1608 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1609 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1611 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1612 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1615 //===----------------------------------------------------------------------===//
1616 // Mips Inline Assembly Support
1617 //===----------------------------------------------------------------------===//
1619 /// getConstraintType - Given a constraint letter, return the type of
1620 /// constraint it is for this target.
1621 MipsTargetLowering::ConstraintType MipsTargetLowering::
1622 getConstraintType(const std::string &Constraint) const
1624 // Mips specific constrainy
1625 // GCC config/mips/constraints.md
1627 // 'd' : An address register. Equivalent to r
1628 // unless generating MIPS16 code.
1629 // 'y' : Equivalent to r; retained for
1630 // backwards compatibility.
1631 // 'f' : Floating Point registers.
1632 if (Constraint.size() == 1) {
1633 switch (Constraint[0]) {
1638 return C_RegisterClass;
1642 return TargetLowering::getConstraintType(Constraint);
1645 /// Examine constraint type and operand type and determine a weight value.
1646 /// This object must already have been set up with the operand type
1647 /// and the current alternative constraint selected.
1648 TargetLowering::ConstraintWeight
1649 MipsTargetLowering::getSingleConstraintMatchWeight(
1650 AsmOperandInfo &info, const char *constraint) const {
1651 ConstraintWeight weight = CW_Invalid;
1652 Value *CallOperandVal = info.CallOperandVal;
1653 // If we don't have a value, we can't do a match,
1654 // but allow it at the lowest weight.
1655 if (CallOperandVal == NULL)
1657 const Type *type = CallOperandVal->getType();
1658 // Look at the constraint type.
1659 switch (*constraint) {
1661 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1665 if (type->isIntegerTy())
1666 weight = CW_Register;
1669 if (type->isFloatTy())
1670 weight = CW_Register;
1676 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1677 /// return a list of registers that can be used to satisfy the constraint.
1678 /// This should only be used for C_RegisterClass constraints.
1679 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1680 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1682 if (Constraint.size() == 1) {
1683 switch (Constraint[0]) {
1685 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1688 return std::make_pair(0U, Mips::FGR32RegisterClass);
1690 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1691 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1694 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1697 /// Given a register class constraint, like 'r', if this corresponds directly
1698 /// to an LLVM register class, return a register of 0 and the register class
1700 std::vector<unsigned> MipsTargetLowering::
1701 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1704 if (Constraint.size() != 1)
1705 return std::vector<unsigned>();
1707 switch (Constraint[0]) {
1710 // GCC Mips Constraint Letters
1713 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1714 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1715 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1719 if (VT == MVT::f32) {
1720 if (Subtarget->isSingleFloat())
1721 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1722 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1723 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1724 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1725 Mips::F30, Mips::F31, 0);
1727 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1728 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1729 Mips::F28, Mips::F30, 0);
1733 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1734 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1735 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1736 Mips::D14, Mips::D15, 0);
1738 return std::vector<unsigned>();
1742 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1743 // The Mips target isn't yet aware of offsets.
1747 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1748 if (VT != MVT::f32 && VT != MVT::f64)
1750 if (Imm.isNegZero())
1752 return Imm.isZero();