1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::SelectCC : return "MipsISD::SelectCC";
47 default : return NULL;
52 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
54 // Mips does not have i1 type, so use i32 for
55 // setcc operations results (slt, sgt, ...).
56 setSetCCResultContents(ZeroOrOneSetCCResult);
58 // JumpTable targets must use GOT when using PIC_
59 setUsesGlobalOffsetTable(true);
61 // Set up the register classes
62 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
66 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
67 setOperationAction(ISD::RET, MVT::Other, Custom);
68 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
69 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
71 // Load extented operations for i1 types must be promoted
72 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
74 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
76 // Mips does not have these NodeTypes below.
77 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
78 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
79 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
80 setOperationAction(ISD::SELECT, MVT::i32, Expand);
81 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
83 // Mips not supported intrinsics.
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
87 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
88 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
89 setOperationAction(ISD::ROTL , MVT::i32, Expand);
90 setOperationAction(ISD::ROTR , MVT::i32, Expand);
91 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
93 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
94 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
95 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
97 // We don't have line number support yet.
98 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
99 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
100 setOperationAction(ISD::LABEL, MVT::Other, Expand);
102 // Use the default for now
103 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
104 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
106 setStackPointerRegisterToSaveRestore(Mips::SP);
107 computeRegisterProperties();
111 MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
116 SDOperand MipsTargetLowering::
117 LowerOperation(SDOperand Op, SelectionDAG &DAG)
119 switch (Op.getOpcode())
121 case ISD::CALL: return LowerCALL(Op, DAG);
122 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
123 case ISD::RET: return LowerRET(Op, DAG);
124 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
125 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
126 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
127 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
133 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
134 MachineBasicBlock *BB)
136 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
137 switch (MI->getOpcode()) {
138 default: assert(false && "Unexpected instr type to insert");
139 case Mips::Select_CC: {
140 // To "insert" a SELECT_CC instruction, we actually have to insert the
141 // diamond control-flow pattern. The incoming instruction knows the
142 // destination vreg to set, the condition code register to branch on, the
143 // true/false values to select between, and a branch opcode to use.
144 const BasicBlock *LLVM_BB = BB->getBasicBlock();
145 ilist<MachineBasicBlock>::iterator It = BB;
152 // bNE r1, r0, copy1MBB
153 // fallthrough --> copy0MBB
154 MachineBasicBlock *thisMBB = BB;
155 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
156 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
157 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
158 .addReg(Mips::ZERO).addMBB(sinkMBB);
159 MachineFunction *F = BB->getParent();
160 F->getBasicBlockList().insert(It, copy0MBB);
161 F->getBasicBlockList().insert(It, sinkMBB);
162 // Update machine-CFG edges by first adding all successors of the current
163 // block to the new block which will contain the Phi node for the select.
164 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
165 e = BB->succ_end(); i != e; ++i)
166 sinkMBB->addSuccessor(*i);
167 // Next, remove all successors of the current block, and add the true
168 // and fallthrough blocks as its successors.
169 while(!BB->succ_empty())
170 BB->removeSuccessor(BB->succ_begin());
171 BB->addSuccessor(copy0MBB);
172 BB->addSuccessor(sinkMBB);
176 // # fallthrough to sinkMBB
179 // Update machine-CFG edges
180 BB->addSuccessor(sinkMBB);
183 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
186 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
187 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
188 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
190 delete MI; // The pseudo instruction is gone now.
196 //===----------------------------------------------------------------------===//
197 // Lower helper functions
198 //===----------------------------------------------------------------------===//
200 // AddLiveIn - This helper function adds the specified physical register to the
201 // MachineFunction as a live in value. It also creates a corresponding
202 // virtual register for it.
204 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
206 assert(RC->contains(PReg) && "Not the correct regclass!");
207 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
208 MF.getRegInfo().addLiveIn(PReg, VReg);
212 //===----------------------------------------------------------------------===//
213 // Misc Lower Operation implementation
214 //===----------------------------------------------------------------------===//
215 SDOperand MipsTargetLowering::
216 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
219 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
220 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
221 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
225 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
226 SDOperand Ops[] = { GA };
227 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
228 } else // Emit Load from Global Pointer
229 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
231 // On functions and global targets not internal linked only
232 // a load from got/GP is necessary for PIC to work.
233 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
236 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
237 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
242 SDOperand MipsTargetLowering::
243 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
245 assert(0 && "TLS not implemented for MIPS.");
246 return SDOperand(); // Not reached
249 SDOperand MipsTargetLowering::
250 LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
252 SDOperand LHS = Op.getOperand(0);
253 SDOperand RHS = Op.getOperand(1);
254 SDOperand True = Op.getOperand(2);
255 SDOperand False = Op.getOperand(3);
256 SDOperand CC = Op.getOperand(4);
258 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
259 SDOperand Ops[] = { LHS, RHS, CC };
260 SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
262 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
263 SetCCRes, True, False);
266 SDOperand MipsTargetLowering::
267 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
272 MVT PtrVT = Op.getValueType();
273 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
274 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
276 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
277 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
278 SDOperand Ops[] = { JTI };
279 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
280 } else // Emit Load from Global Pointer
281 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
283 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
284 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
289 //===----------------------------------------------------------------------===//
290 // Calling Convention Implementation
292 // The lower operations present on calling convention works on this order:
293 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
294 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
295 // LowerRET (virt regs --> phys regs)
296 // LowerCALL (phys regs --> virt regs)
298 //===----------------------------------------------------------------------===//
300 #include "MipsGenCallingConv.inc"
302 //===----------------------------------------------------------------------===//
303 // CALL Calling Convention Implementation
304 //===----------------------------------------------------------------------===//
306 /// Mips custom CALL implementation
307 SDOperand MipsTargetLowering::
308 LowerCALL(SDOperand Op, SelectionDAG &DAG)
310 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
312 // By now, only CallingConv::C implemented
313 switch (CallingConv) {
315 assert(0 && "Unsupported calling convention");
316 case CallingConv::Fast:
318 return LowerCCCCallTo(Op, DAG, CallingConv);
322 /// LowerCCCCallTo - functions arguments are copied from virtual
323 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
324 /// CALLSEQ_END are emitted.
325 /// TODO: isVarArg, isTailCall, sret.
326 SDOperand MipsTargetLowering::
327 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
329 MachineFunction &MF = DAG.getMachineFunction();
331 SDOperand Chain = Op.getOperand(0);
332 SDOperand Callee = Op.getOperand(4);
333 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
335 MachineFrameInfo *MFI = MF.getFrameInfo();
337 // Analyze operands of the call, assigning locations to each operand.
338 SmallVector<CCValAssign, 16> ArgLocs;
339 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
341 // To meet ABI, Mips must always allocate 16 bytes on
342 // the stack (even if less than 4 are used as arguments)
343 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
344 MFI->CreateFixedObject(VTsize, (VTsize*3));
346 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
348 // Get a count of how many bytes are to be pushed on the stack.
349 unsigned NumBytes = CCInfo.getNextStackOffset();
350 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
353 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
354 SmallVector<SDOperand, 8> MemOpChains;
356 int LastStackLoc = 0;
358 // Walk the register/memloc assignments, inserting copies/loads.
359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
360 CCValAssign &VA = ArgLocs[i];
362 // Arguments start after the 5 first operands of ISD::CALL
363 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
365 // Promote the value if needed.
366 switch (VA.getLocInfo()) {
367 default: assert(0 && "Unknown loc info!");
368 case CCValAssign::Full: break;
369 case CCValAssign::SExt:
370 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
372 case CCValAssign::ZExt:
373 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
375 case CCValAssign::AExt:
376 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
380 // Arguments that can be passed on register must be kept at
383 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
387 assert(VA.isMemLoc());
389 // Create the frame index object for this incoming parameter
390 // This guarantees that when allocating Local Area the firsts
391 // 16 bytes which are alwayes reserved won't be overwritten.
392 LastStackLoc = (16 + VA.getLocMemOffset());
393 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
396 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
398 // emit ISD::STORE whichs stores the
399 // parameter value to a stack Location
400 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
403 // Transform all store nodes into one single node because
404 // all store nodes are independent of each other.
405 if (!MemOpChains.empty())
406 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
407 &MemOpChains[0], MemOpChains.size());
409 // Build a sequence of copy-to-reg nodes chained together with token
410 // chain and flag operands which copy the outgoing args into registers.
411 // The InFlag in necessary since all emited instructions must be
414 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
415 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
416 RegsToPass[i].second, InFlag);
417 InFlag = Chain.getValue(1);
420 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
421 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
422 // node so that legalize doesn't hack it.
423 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
424 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
425 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
426 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
429 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
430 // = Chain, Callee, Reg#1, Reg#2, ...
432 // Returns a chain & a flag for retval copy to use.
433 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
434 SmallVector<SDOperand, 8> Ops;
435 Ops.push_back(Chain);
436 Ops.push_back(Callee);
438 // Add argument registers to the end of the list so that they are
439 // known live into the call.
440 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
441 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
442 RegsToPass[i].second.getValueType()));
445 Ops.push_back(InFlag);
447 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
448 InFlag = Chain.getValue(1);
450 // Create the CALLSEQ_END node.
451 Chain = DAG.getCALLSEQ_END(Chain,
452 DAG.getConstant(NumBytes, getPointerTy()),
453 DAG.getConstant(0, getPointerTy()),
455 InFlag = Chain.getValue(1);
457 // Create a stack location to hold GP when PIC is used. This stack
458 // location is used on function prologue to save GP and also after all
459 // emited CALL's to restore GP.
460 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
461 // Function can have an arbitrary number of calls, so
462 // hold the LastStackLoc with the biggest offset.
464 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
465 if (LastStackLoc >= MipsFI->getGPStackOffset()) {
466 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
467 // Create the frame index only once. SPOffset here can be anything
468 // (this will be fixed on processFunctionBeforeFrameFinalized)
469 if (MipsFI->getGPStackOffset() == -1) {
470 FI = MFI->CreateFixedObject(4, 0);
473 MipsFI->setGPStackOffset(LastStackLoc);
477 FI = MipsFI->getGPFI();
478 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
479 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
480 Chain = GPLoad.getValue(1);
481 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
482 GPLoad, SDOperand(0,0));
483 InFlag = Chain.getValue(1);
486 // Handle result values, copying them out of physregs into vregs that we
488 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
491 /// LowerCallResult - Lower the result values of an ISD::CALL into the
492 /// appropriate copies out of appropriate physical registers. This assumes that
493 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
494 /// being lowered. Returns a SDNode with the same number of values as the
496 SDNode *MipsTargetLowering::
497 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
498 unsigned CallingConv, SelectionDAG &DAG) {
500 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
502 // Assign locations to each value returned by this call.
503 SmallVector<CCValAssign, 16> RVLocs;
504 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
506 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
507 SmallVector<SDOperand, 8> ResultVals;
509 // Copy all of the result registers out of their specified physreg.
510 for (unsigned i = 0; i != RVLocs.size(); ++i) {
511 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
512 RVLocs[i].getValVT(), InFlag).getValue(1);
513 InFlag = Chain.getValue(2);
514 ResultVals.push_back(Chain.getValue(0));
517 ResultVals.push_back(Chain);
519 // Merge everything together with a MERGE_VALUES node.
520 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
521 &ResultVals[0], ResultVals.size()).Val;
524 //===----------------------------------------------------------------------===//
525 // FORMAL_ARGUMENTS Calling Convention Implementation
526 //===----------------------------------------------------------------------===//
528 /// Mips custom FORMAL_ARGUMENTS implementation
529 SDOperand MipsTargetLowering::
530 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
532 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
536 assert(0 && "Unsupported calling convention");
538 return LowerCCCArguments(Op, DAG);
542 /// LowerCCCArguments - transform physical registers into
543 /// virtual registers and generate load operations for
544 /// arguments places on the stack.
545 /// TODO: isVarArg, sret
546 SDOperand MipsTargetLowering::
547 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
549 SDOperand Root = Op.getOperand(0);
550 MachineFunction &MF = DAG.getMachineFunction();
551 MachineFrameInfo *MFI = MF.getFrameInfo();
552 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
554 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
555 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
557 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
559 // GP holds the GOT address on PIC calls.
560 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
561 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
563 // Assign locations to all of the incoming arguments.
564 SmallVector<CCValAssign, 16> ArgLocs;
565 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
567 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
568 SmallVector<SDOperand, 8> ArgValues;
571 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
573 CCValAssign &VA = ArgLocs[i];
575 // Arguments stored on registers
577 MVT RegVT = VA.getLocVT();
578 TargetRegisterClass *RC;
580 if (RegVT == MVT::i32)
581 RC = Mips::CPURegsRegisterClass;
583 assert(0 && "support only Mips::CPURegsRegisterClass");
585 // Transform the arguments stored on
586 // physical registers into virtual ones
587 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
588 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
590 // If this is an 8 or 16-bit value, it is really passed promoted
591 // to 32 bits. Insert an assert[sz]ext to capture this, then
592 // truncate to the right size.
593 if (VA.getLocInfo() == CCValAssign::SExt)
594 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
595 DAG.getValueType(VA.getValVT()));
596 else if (VA.getLocInfo() == CCValAssign::ZExt)
597 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
598 DAG.getValueType(VA.getValVT()));
600 if (VA.getLocInfo() != CCValAssign::Full)
601 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
603 ArgValues.push_back(ArgValue);
605 // To meet ABI, when VARARGS are passed on registers, the registers
606 // must have their values written to the caller stack frame.
609 if (StackPtr.Val == 0)
610 StackPtr = DAG.getRegister(StackReg, getPointerTy());
612 // The stack pointer offset is relative to the caller stack frame.
613 // Since the real stack size is unknown here, a negative SPOffset
614 // is used so there's a way to adjust these offsets when the stack
615 // size get known (on EliminateFrameIndex). A dummy SPOffset is
616 // used instead of a direct negative address (which is recorded to
617 // be used on emitPrologue) to avoid mis-calc of the first stack
618 // offset on PEI::calculateFrameObjectOffsets.
619 // Arguments are always 32-bit.
620 int FI = MFI->CreateFixedObject(4, 0);
621 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
622 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
624 // emit ISD::STORE whichs stores the
625 // parameter value to a stack Location
626 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
631 assert(VA.isMemLoc());
633 // The stack pointer offset is relative to the caller stack frame.
634 // Since the real stack size is unknown here, a negative SPOffset
635 // is used so there's a way to adjust these offsets when the stack
636 // size get known (on EliminateFrameIndex). A dummy SPOffset is
637 // used instead of a direct negative address (which is recorded to
638 // be used on emitPrologue) to avoid mis-calc of the first stack
639 // offset on PEI::calculateFrameObjectOffsets.
640 // Arguments are always 32-bit.
641 int FI = MFI->CreateFixedObject(4, 0);
642 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
644 // Create load nodes to retrieve arguments from the stack
645 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
646 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
649 ArgValues.push_back(Root);
651 // Return the new list of results.
652 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
653 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
656 //===----------------------------------------------------------------------===//
657 // Return Value Calling Convention Implementation
658 //===----------------------------------------------------------------------===//
660 SDOperand MipsTargetLowering::
661 LowerRET(SDOperand Op, SelectionDAG &DAG)
663 // CCValAssign - represent the assignment of
664 // the return value to a location
665 SmallVector<CCValAssign, 16> RVLocs;
666 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
667 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
669 // CCState - Info about the registers and stack slot.
670 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
672 // Analize return values of ISD::RET
673 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
675 // If this is the first return lowered for this function, add
676 // the regs to the liveout set for the function.
677 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
678 for (unsigned i = 0; i != RVLocs.size(); ++i)
679 if (RVLocs[i].isRegLoc())
680 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
683 // The chain is always operand #0
684 SDOperand Chain = Op.getOperand(0);
687 // Copy the result values into the output registers.
688 for (unsigned i = 0; i != RVLocs.size(); ++i) {
689 CCValAssign &VA = RVLocs[i];
690 assert(VA.isRegLoc() && "Can only return in registers!");
692 // ISD::RET => ret chain, (regnum1,val1), ...
693 // So i*2+1 index only the regnums
694 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
696 // guarantee that all emitted copies are
697 // stuck together, avoiding something bad
698 Flag = Chain.getValue(1);
701 // Return on Mips is always a "jr $ra"
703 return DAG.getNode(MipsISD::Ret, MVT::Other,
704 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
706 return DAG.getNode(MipsISD::Ret, MVT::Other,
707 Chain, DAG.getRegister(Mips::RA, MVT::i32));
710 //===----------------------------------------------------------------------===//
711 // Mips Inline Assembly Support
712 //===----------------------------------------------------------------------===//
714 /// getConstraintType - Given a constraint letter, return the type of
715 /// constraint it is for this target.
716 MipsTargetLowering::ConstraintType MipsTargetLowering::
717 getConstraintType(const std::string &Constraint) const
719 if (Constraint.size() == 1) {
720 // Mips specific constrainy
721 // GCC config/mips/constraints.md
723 // 'd' : An address register. Equivalent to r
724 // unless generating MIPS16 code.
725 // 'y' : Equivalent to r; retained for
726 // backwards compatibility.
728 switch (Constraint[0]) {
732 return C_RegisterClass;
736 return TargetLowering::getConstraintType(Constraint);
739 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
740 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
742 if (Constraint.size() == 1) {
743 switch (Constraint[0]) {
745 return std::make_pair(0U, Mips::CPURegsRegisterClass);
749 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
752 std::vector<unsigned> MipsTargetLowering::
753 getRegClassForInlineAsmConstraint(const std::string &Constraint,
756 if (Constraint.size() != 1)
757 return std::vector<unsigned>();
759 switch (Constraint[0]) {
762 // GCC Mips Constraint Letters
765 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
766 Mips::A1, Mips::A2, Mips::A3,
767 Mips::T0, Mips::T1, Mips::T2,
768 Mips::T3, Mips::T4, Mips::T5,
769 Mips::T6, Mips::T7, Mips::S0,
770 Mips::S1, Mips::S2, Mips::S3,
771 Mips::S4, Mips::S5, Mips::S6,
772 Mips::S7, Mips::T8, Mips::T9, 0);
775 return std::vector<unsigned>();