1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "MipsTargetObjectFile.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NumTailCalls, "Number of tail calls");
45 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
46 cl::desc("MIPS: Enable tail calls."), cl::init(false));
49 LargeGOT("mxgot", cl::Hidden,
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
53 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
54 cl::desc("MIPS: mips16 hard float enable."),
57 static cl::opt<bool> DontExpandCondPseudos16(
58 "mips16-dont-expand-cond-pseudo",
60 cl::desc("Dont expand conditional move related "
61 "pseudos for Mips 16"),
65 static const uint16_t O32IntRegs[4] = {
66 Mips::A0, Mips::A1, Mips::A2, Mips::A3
69 static const uint16_t Mips64IntRegs[8] = {
70 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
71 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
74 static const uint16_t Mips64DPRegs[8] = {
75 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
76 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
79 // If I is a shifted mask, set the size (Size) and the first bit of the
80 // mask (Pos), and return true.
81 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
82 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
83 if (!isShiftedMask_64(I))
86 Size = CountPopulation_64(I);
87 Pos = CountTrailingZeros_64(I);
91 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
92 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
93 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
96 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
97 EVT Ty = Op.getValueType();
99 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
100 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0,
102 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
103 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
104 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
105 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
106 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
107 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
108 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
109 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
110 N->getOffset(), Flag);
112 llvm_unreachable("Unexpected node type.");
116 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
117 DebugLoc DL = Op.getDebugLoc();
118 EVT Ty = Op.getValueType();
119 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
120 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
121 return DAG.getNode(ISD::ADD, DL, Ty,
122 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
123 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
126 static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) {
127 DebugLoc DL = Op.getDebugLoc();
128 EVT Ty = Op.getValueType();
129 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
130 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
131 getTargetNode(Op, DAG, GOTFlag));
132 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
133 MachinePointerInfo::getGOT(), false, false, false,
135 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
136 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
137 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
140 static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
141 DebugLoc DL = Op.getDebugLoc();
142 EVT Ty = Op.getValueType();
143 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
144 getTargetNode(Op, DAG, Flag));
145 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
146 MachinePointerInfo::getGOT(), false, false, false, 0);
149 static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
150 unsigned HiFlag, unsigned LoFlag) {
151 DebugLoc DL = Op.getDebugLoc();
152 EVT Ty = Op.getValueType();
153 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
154 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty));
155 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
156 getTargetNode(Op, DAG, LoFlag));
157 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
158 MachinePointerInfo::getGOT(), false, false, false, 0);
161 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
163 case MipsISD::JmpLink: return "MipsISD::JmpLink";
164 case MipsISD::TailCall: return "MipsISD::TailCall";
165 case MipsISD::Hi: return "MipsISD::Hi";
166 case MipsISD::Lo: return "MipsISD::Lo";
167 case MipsISD::GPRel: return "MipsISD::GPRel";
168 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
169 case MipsISD::Ret: return "MipsISD::Ret";
170 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
171 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
172 case MipsISD::FPCmp: return "MipsISD::FPCmp";
173 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
174 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
175 case MipsISD::FPRound: return "MipsISD::FPRound";
176 case MipsISD::MAdd: return "MipsISD::MAdd";
177 case MipsISD::MAddu: return "MipsISD::MAddu";
178 case MipsISD::MSub: return "MipsISD::MSub";
179 case MipsISD::MSubu: return "MipsISD::MSubu";
180 case MipsISD::DivRem: return "MipsISD::DivRem";
181 case MipsISD::DivRemU: return "MipsISD::DivRemU";
182 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
183 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
184 case MipsISD::Wrapper: return "MipsISD::Wrapper";
185 case MipsISD::Sync: return "MipsISD::Sync";
186 case MipsISD::Ext: return "MipsISD::Ext";
187 case MipsISD::Ins: return "MipsISD::Ins";
188 case MipsISD::LWL: return "MipsISD::LWL";
189 case MipsISD::LWR: return "MipsISD::LWR";
190 case MipsISD::SWL: return "MipsISD::SWL";
191 case MipsISD::SWR: return "MipsISD::SWR";
192 case MipsISD::LDL: return "MipsISD::LDL";
193 case MipsISD::LDR: return "MipsISD::LDR";
194 case MipsISD::SDL: return "MipsISD::SDL";
195 case MipsISD::SDR: return "MipsISD::SDR";
196 case MipsISD::EXTP: return "MipsISD::EXTP";
197 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
198 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
199 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
200 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
201 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
202 case MipsISD::SHILO: return "MipsISD::SHILO";
203 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
204 case MipsISD::MULT: return "MipsISD::MULT";
205 case MipsISD::MULTU: return "MipsISD::MULTU";
206 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
207 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
208 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
209 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
210 default: return NULL;
216 bool operator()(const char *s1, const char *s2) const
218 return strcmp(s1, s2) < 0;
222 std::set<const char*, ltstr> noHelperNeeded;
225 void MipsTargetLowering::SetMips16LibcallName
226 (RTLIB::Libcall l, const char *Name) {
227 setLibcallName(l, Name);
228 noHelperNeeded.insert(Name);
231 void MipsTargetLowering::setMips16HardFloatLibCalls() {
232 SetMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
233 SetMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
234 SetMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
235 SetMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
236 SetMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
237 SetMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
238 SetMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
239 SetMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
240 SetMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
241 SetMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
242 SetMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
243 SetMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
244 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
245 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
246 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
247 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
248 SetMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
249 SetMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
250 SetMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
251 SetMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
252 SetMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
253 SetMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
254 SetMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
255 SetMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
256 SetMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
257 SetMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
258 SetMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
259 SetMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
260 SetMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
261 SetMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
262 SetMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
263 SetMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
267 MipsTargetLowering(MipsTargetMachine &TM)
268 : TargetLowering(TM, new MipsTargetObjectFile()),
269 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
270 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
271 IsO32(Subtarget->isABI_O32()) {
273 // Mips does not have i1 type, so use i32 for
274 // setcc operations results (slt, sgt, ...).
275 setBooleanContents(ZeroOrOneBooleanContent);
276 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
278 // Set up the register classes
279 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
282 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
284 if (Subtarget->inMips16Mode()) {
285 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
287 setMips16HardFloatLibCalls();
290 if (Subtarget->hasDSP()) {
291 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
293 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
294 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
296 // Expand all builtin opcodes.
297 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
298 setOperationAction(Opc, VecTys[i], Expand);
300 setOperationAction(ISD::LOAD, VecTys[i], Legal);
301 setOperationAction(ISD::STORE, VecTys[i], Legal);
302 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
306 if (!TM.Options.UseSoftFloat) {
307 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
309 // When dealing with single precision only, use libcalls
310 if (!Subtarget->isSingleFloat()) {
312 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
314 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
318 // Load extented operations for i1 types must be promoted
319 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
320 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
321 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
323 // MIPS doesn't have extending float->double load/store
324 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
325 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
327 // Used by legalize types to correctly generate the setcc result.
328 // Without this, every float setcc comes with a AND/OR with the result,
329 // we don't want this, since the fpcmp result goes to a flag register,
330 // which is used implicitly by brcond and select operations.
331 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
333 // Mips Custom Operations
334 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
335 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
336 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
337 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
338 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
339 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
340 setOperationAction(ISD::SELECT, MVT::f32, Custom);
341 setOperationAction(ISD::SELECT, MVT::f64, Custom);
342 setOperationAction(ISD::SELECT, MVT::i32, Custom);
343 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
344 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
345 setOperationAction(ISD::SETCC, MVT::f32, Custom);
346 setOperationAction(ISD::SETCC, MVT::f64, Custom);
347 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
348 setOperationAction(ISD::VASTART, MVT::Other, Custom);
349 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
350 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
351 if (Subtarget->inMips16Mode()) {
352 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
353 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
356 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
357 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
359 if (!Subtarget->inMips16Mode()) {
360 setOperationAction(ISD::LOAD, MVT::i32, Custom);
361 setOperationAction(ISD::STORE, MVT::i32, Custom);
364 if (!TM.Options.NoNaNsFPMath) {
365 setOperationAction(ISD::FABS, MVT::f32, Custom);
366 setOperationAction(ISD::FABS, MVT::f64, Custom);
370 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
371 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
372 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
373 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
374 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
375 setOperationAction(ISD::SELECT, MVT::i64, Custom);
376 setOperationAction(ISD::LOAD, MVT::i64, Custom);
377 setOperationAction(ISD::STORE, MVT::i64, Custom);
381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
386 setOperationAction(ISD::ADD, MVT::i32, Custom);
388 setOperationAction(ISD::ADD, MVT::i64, Custom);
390 setOperationAction(ISD::SDIV, MVT::i32, Expand);
391 setOperationAction(ISD::SREM, MVT::i32, Expand);
392 setOperationAction(ISD::UDIV, MVT::i32, Expand);
393 setOperationAction(ISD::UREM, MVT::i32, Expand);
394 setOperationAction(ISD::SDIV, MVT::i64, Expand);
395 setOperationAction(ISD::SREM, MVT::i64, Expand);
396 setOperationAction(ISD::UDIV, MVT::i64, Expand);
397 setOperationAction(ISD::UREM, MVT::i64, Expand);
399 // Operations not directly supported by Mips.
400 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
401 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
402 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
403 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
404 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
407 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
410 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
411 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
412 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
413 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
414 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
415 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
418 setOperationAction(ISD::ROTL, MVT::i32, Expand);
419 setOperationAction(ISD::ROTL, MVT::i64, Expand);
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
423 if (!Subtarget->hasMips32r2())
424 setOperationAction(ISD::ROTR, MVT::i32, Expand);
426 if (!Subtarget->hasMips64r2())
427 setOperationAction(ISD::ROTR, MVT::i64, Expand);
429 setOperationAction(ISD::FSIN, MVT::f32, Expand);
430 setOperationAction(ISD::FSIN, MVT::f64, Expand);
431 setOperationAction(ISD::FCOS, MVT::f32, Expand);
432 setOperationAction(ISD::FCOS, MVT::f64, Expand);
433 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
434 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
435 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
436 setOperationAction(ISD::FPOW, MVT::f32, Expand);
437 setOperationAction(ISD::FPOW, MVT::f64, Expand);
438 setOperationAction(ISD::FLOG, MVT::f32, Expand);
439 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
440 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
441 setOperationAction(ISD::FEXP, MVT::f32, Expand);
442 setOperationAction(ISD::FMA, MVT::f32, Expand);
443 setOperationAction(ISD::FMA, MVT::f64, Expand);
444 setOperationAction(ISD::FREM, MVT::f32, Expand);
445 setOperationAction(ISD::FREM, MVT::f64, Expand);
447 if (!TM.Options.NoNaNsFPMath) {
448 setOperationAction(ISD::FNEG, MVT::f32, Expand);
449 setOperationAction(ISD::FNEG, MVT::f64, Expand);
452 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
453 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
454 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
455 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
457 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
459 setOperationAction(ISD::VAARG, MVT::Other, Expand);
460 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
461 setOperationAction(ISD::VAEND, MVT::Other, Expand);
463 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
464 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
466 // Use the default for now
467 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
468 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
470 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
472 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
473 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
475 if (Subtarget->inMips16Mode()) {
476 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
477 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
478 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
479 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
480 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
481 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
482 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
483 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
484 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
485 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
486 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
487 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
490 setInsertFencesForAtomic(true);
492 if (!Subtarget->hasSEInReg()) {
493 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
494 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
497 if (!Subtarget->hasBitCount()) {
498 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
499 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
502 if (!Subtarget->hasSwap()) {
503 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
504 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
508 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
509 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
510 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
511 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
514 setTargetDAGCombine(ISD::ADDE);
515 setTargetDAGCombine(ISD::SUBE);
516 setTargetDAGCombine(ISD::SDIVREM);
517 setTargetDAGCombine(ISD::UDIVREM);
518 setTargetDAGCombine(ISD::SELECT);
519 setTargetDAGCombine(ISD::AND);
520 setTargetDAGCombine(ISD::OR);
521 setTargetDAGCombine(ISD::ADD);
523 setMinFunctionAlignment(HasMips64 ? 3 : 2);
525 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
526 computeRegisterProperties();
528 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
529 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
531 MaxStoresPerMemcpy = 16;
535 MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
536 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
538 if (Subtarget->inMips16Mode())
552 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
555 return VT.changeVectorElementTypeToInteger();
559 // Transforms a subgraph in CurDAG if the following pattern is found:
560 // (addc multLo, Lo0), (adde multHi, Hi0),
562 // multHi/Lo: product of multiplication
563 // Lo0: initial value of Lo register
564 // Hi0: initial value of Hi register
565 // Return true if pattern matching was successful.
566 static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
567 // ADDENode's second operand must be a flag output of an ADDC node in order
568 // for the matching to be successful.
569 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
571 if (ADDCNode->getOpcode() != ISD::ADDC)
574 SDValue MultHi = ADDENode->getOperand(0);
575 SDValue MultLo = ADDCNode->getOperand(0);
576 SDNode *MultNode = MultHi.getNode();
577 unsigned MultOpc = MultHi.getOpcode();
579 // MultHi and MultLo must be generated by the same node,
580 if (MultLo.getNode() != MultNode)
583 // and it must be a multiplication.
584 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
587 // MultLo amd MultHi must be the first and second output of MultNode
589 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
592 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
593 // of the values of MultNode, in which case MultNode will be removed in later
595 // If there exist users other than ADDENode or ADDCNode, this function returns
596 // here, which will result in MultNode being mapped to a single MULT
597 // instruction node rather than a pair of MULT and MADD instructions being
599 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
602 SDValue Chain = CurDAG->getEntryNode();
603 DebugLoc dl = ADDENode->getDebugLoc();
605 // create MipsMAdd(u) node
606 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
608 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
609 MultNode->getOperand(0),// Factor 0
610 MultNode->getOperand(1),// Factor 1
611 ADDCNode->getOperand(1),// Lo0
612 ADDENode->getOperand(1));// Hi0
614 // create CopyFromReg nodes
615 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
617 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
619 CopyFromLo.getValue(2));
621 // replace uses of adde and addc here
622 if (!SDValue(ADDCNode, 0).use_empty())
623 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
625 if (!SDValue(ADDENode, 0).use_empty())
626 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
632 // Transforms a subgraph in CurDAG if the following pattern is found:
633 // (addc Lo0, multLo), (sube Hi0, multHi),
635 // multHi/Lo: product of multiplication
636 // Lo0: initial value of Lo register
637 // Hi0: initial value of Hi register
638 // Return true if pattern matching was successful.
639 static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
640 // SUBENode's second operand must be a flag output of an SUBC node in order
641 // for the matching to be successful.
642 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
644 if (SUBCNode->getOpcode() != ISD::SUBC)
647 SDValue MultHi = SUBENode->getOperand(1);
648 SDValue MultLo = SUBCNode->getOperand(1);
649 SDNode *MultNode = MultHi.getNode();
650 unsigned MultOpc = MultHi.getOpcode();
652 // MultHi and MultLo must be generated by the same node,
653 if (MultLo.getNode() != MultNode)
656 // and it must be a multiplication.
657 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
660 // MultLo amd MultHi must be the first and second output of MultNode
662 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
665 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
666 // of the values of MultNode, in which case MultNode will be removed in later
668 // If there exist users other than SUBENode or SUBCNode, this function returns
669 // here, which will result in MultNode being mapped to a single MULT
670 // instruction node rather than a pair of MULT and MSUB instructions being
672 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
675 SDValue Chain = CurDAG->getEntryNode();
676 DebugLoc dl = SUBENode->getDebugLoc();
678 // create MipsSub(u) node
679 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
681 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
682 MultNode->getOperand(0),// Factor 0
683 MultNode->getOperand(1),// Factor 1
684 SUBCNode->getOperand(0),// Lo0
685 SUBENode->getOperand(0));// Hi0
687 // create CopyFromReg nodes
688 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
690 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
692 CopyFromLo.getValue(2));
694 // replace uses of sube and subc here
695 if (!SDValue(SUBCNode, 0).use_empty())
696 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
698 if (!SDValue(SUBENode, 0).use_empty())
699 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
704 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
705 TargetLowering::DAGCombinerInfo &DCI,
706 const MipsSubtarget *Subtarget) {
707 if (DCI.isBeforeLegalize())
710 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
712 return SDValue(N, 0);
717 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
718 TargetLowering::DAGCombinerInfo &DCI,
719 const MipsSubtarget *Subtarget) {
720 if (DCI.isBeforeLegalize())
723 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
725 return SDValue(N, 0);
730 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
731 TargetLowering::DAGCombinerInfo &DCI,
732 const MipsSubtarget *Subtarget) {
733 if (DCI.isBeforeLegalizeOps())
736 EVT Ty = N->getValueType(0);
737 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
738 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
739 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
741 DebugLoc dl = N->getDebugLoc();
743 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
744 N->getOperand(0), N->getOperand(1));
745 SDValue InChain = DAG.getEntryNode();
746 SDValue InGlue = DivRem;
749 if (N->hasAnyUseOfValue(0)) {
750 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
752 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
753 InChain = CopyFromLo.getValue(1);
754 InGlue = CopyFromLo.getValue(2);
758 if (N->hasAnyUseOfValue(1)) {
759 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
761 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
767 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
769 default: llvm_unreachable("Unknown fp condition code!");
771 case ISD::SETOEQ: return Mips::FCOND_OEQ;
772 case ISD::SETUNE: return Mips::FCOND_UNE;
774 case ISD::SETOLT: return Mips::FCOND_OLT;
776 case ISD::SETOGT: return Mips::FCOND_OGT;
778 case ISD::SETOLE: return Mips::FCOND_OLE;
780 case ISD::SETOGE: return Mips::FCOND_OGE;
781 case ISD::SETULT: return Mips::FCOND_ULT;
782 case ISD::SETULE: return Mips::FCOND_ULE;
783 case ISD::SETUGT: return Mips::FCOND_UGT;
784 case ISD::SETUGE: return Mips::FCOND_UGE;
785 case ISD::SETUO: return Mips::FCOND_UN;
786 case ISD::SETO: return Mips::FCOND_OR;
788 case ISD::SETONE: return Mips::FCOND_ONE;
789 case ISD::SETUEQ: return Mips::FCOND_UEQ;
794 // Returns true if condition code has to be inverted.
795 static bool InvertFPCondCode(Mips::CondCode CC) {
796 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
799 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
800 "Illegal Condition Code");
805 // Creates and returns an FPCmp node from a setcc node.
806 // Returns Op if setcc is not a floating point comparison.
807 static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
808 // must be a SETCC node
809 if (Op.getOpcode() != ISD::SETCC)
812 SDValue LHS = Op.getOperand(0);
814 if (!LHS.getValueType().isFloatingPoint())
817 SDValue RHS = Op.getOperand(1);
818 DebugLoc dl = Op.getDebugLoc();
820 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
821 // node if necessary.
822 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
824 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
825 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
828 // Creates and returns a CMovFPT/F node.
829 static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
830 SDValue False, DebugLoc DL) {
831 bool invert = InvertFPCondCode((Mips::CondCode)
832 cast<ConstantSDNode>(Cond.getOperand(2))
835 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
836 True.getValueType(), True, False, Cond);
839 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
840 TargetLowering::DAGCombinerInfo &DCI,
841 const MipsSubtarget *Subtarget) {
842 if (DCI.isBeforeLegalizeOps())
845 SDValue SetCC = N->getOperand(0);
847 if ((SetCC.getOpcode() != ISD::SETCC) ||
848 !SetCC.getOperand(0).getValueType().isInteger())
851 SDValue False = N->getOperand(2);
852 EVT FalseTy = False.getValueType();
854 if (!FalseTy.isInteger())
857 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
859 if (!CN || CN->getZExtValue())
862 const DebugLoc DL = N->getDebugLoc();
863 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
864 SDValue True = N->getOperand(1);
866 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
867 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
869 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
872 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
873 TargetLowering::DAGCombinerInfo &DCI,
874 const MipsSubtarget *Subtarget) {
875 // Pattern match EXT.
876 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
877 // => ext $dst, $src, size, pos
878 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
881 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
882 unsigned ShiftRightOpc = ShiftRight.getOpcode();
884 // Op's first operand must be a shift right.
885 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
888 // The second operand of the shift must be an immediate.
890 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
893 uint64_t Pos = CN->getZExtValue();
894 uint64_t SMPos, SMSize;
896 // Op's second operand must be a shifted mask.
897 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
898 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
901 // Return if the shifted mask does not start at bit 0 or the sum of its size
902 // and Pos exceeds the word's size.
903 EVT ValTy = N->getValueType(0);
904 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
907 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
908 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
909 DAG.getConstant(SMSize, MVT::i32));
912 static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
913 TargetLowering::DAGCombinerInfo &DCI,
914 const MipsSubtarget *Subtarget) {
915 // Pattern match INS.
916 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
917 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
918 // => ins $dst, $src, size, pos, $src1
919 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
922 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
923 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
926 // See if Op's first operand matches (and $src1 , mask0).
927 if (And0.getOpcode() != ISD::AND)
930 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
931 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
934 // See if Op's second operand matches (and (shl $src, pos), mask1).
935 if (And1.getOpcode() != ISD::AND)
938 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
939 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
942 // The shift masks must have the same position and size.
943 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
946 SDValue Shl = And1.getOperand(0);
947 if (Shl.getOpcode() != ISD::SHL)
950 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
953 unsigned Shamt = CN->getZExtValue();
955 // Return if the shift amount and the first bit position of mask are not the
957 EVT ValTy = N->getValueType(0);
958 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
961 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
962 DAG.getConstant(SMPos0, MVT::i32),
963 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
966 static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
967 TargetLowering::DAGCombinerInfo &DCI,
968 const MipsSubtarget *Subtarget) {
969 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
971 if (DCI.isBeforeLegalizeOps())
974 SDValue Add = N->getOperand(1);
976 if (Add.getOpcode() != ISD::ADD)
979 SDValue Lo = Add.getOperand(1);
981 if ((Lo.getOpcode() != MipsISD::Lo) ||
982 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
985 EVT ValTy = N->getValueType(0);
986 DebugLoc DL = N->getDebugLoc();
988 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
990 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
993 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
995 SelectionDAG &DAG = DCI.DAG;
996 unsigned opc = N->getOpcode();
1001 return PerformADDECombine(N, DAG, DCI, Subtarget);
1003 return PerformSUBECombine(N, DAG, DCI, Subtarget);
1006 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
1008 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
1010 return PerformANDCombine(N, DAG, DCI, Subtarget);
1012 return PerformORCombine(N, DAG, DCI, Subtarget);
1014 return PerformADDCombine(N, DAG, DCI, Subtarget);
1021 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1022 SmallVectorImpl<SDValue> &Results,
1023 SelectionDAG &DAG) const {
1024 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1026 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1027 Results.push_back(Res.getValue(I));
1031 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1032 SmallVectorImpl<SDValue> &Results,
1033 SelectionDAG &DAG) const {
1034 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1036 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1037 Results.push_back(Res.getValue(I));
1040 SDValue MipsTargetLowering::
1041 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1043 switch (Op.getOpcode())
1045 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1046 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1047 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1048 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1049 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1050 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1051 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1052 case ISD::SELECT: return LowerSELECT(Op, DAG);
1053 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1054 case ISD::SETCC: return LowerSETCC(Op, DAG);
1055 case ISD::VASTART: return LowerVASTART(Op, DAG);
1056 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1057 case ISD::FABS: return LowerFABS(Op, DAG);
1058 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1059 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1060 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1061 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1062 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1063 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
1064 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
1065 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
1066 case ISD::LOAD: return LowerLOAD(Op, DAG);
1067 case ISD::STORE: return LowerSTORE(Op, DAG);
1068 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1069 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
1070 case ISD::ADD: return LowerADD(Op, DAG);
1075 //===----------------------------------------------------------------------===//
1076 // Lower helper functions
1077 //===----------------------------------------------------------------------===//
1079 // AddLiveIn - This helper function adds the specified physical register to the
1080 // MachineFunction as a live in value. It also creates a corresponding
1081 // virtual register for it.
1083 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1085 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1086 MF.getRegInfo().addLiveIn(PReg, VReg);
1090 // Get fp branch code (not opcode) from condition code.
1091 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
1092 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
1093 return Mips::BRANCH_T;
1095 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
1096 "Invalid CondCode.");
1098 return Mips::BRANCH_F;
1102 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
1104 const MipsSubtarget *Subtarget,
1105 const TargetInstrInfo *TII,
1106 bool isFPCmp, unsigned Opc) {
1107 // There is no need to expand CMov instructions if target has
1108 // conditional moves.
1109 if (Subtarget->hasCondMov())
1112 // To "insert" a SELECT_CC instruction, we actually have to insert the
1113 // diamond control-flow pattern. The incoming instruction knows the
1114 // destination vreg to set, the condition code register to branch on, the
1115 // true/false values to select between, and a branch opcode to use.
1116 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1117 MachineFunction::iterator It = BB;
1124 // bNE r1, r0, copy1MBB
1125 // fallthrough --> copy0MBB
1126 MachineBasicBlock *thisMBB = BB;
1127 MachineFunction *F = BB->getParent();
1128 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1129 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1130 F->insert(It, copy0MBB);
1131 F->insert(It, sinkMBB);
1133 // Transfer the remainder of BB and its successor edges to sinkMBB.
1134 sinkMBB->splice(sinkMBB->begin(), BB,
1135 llvm::next(MachineBasicBlock::iterator(MI)),
1137 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1139 // Next, add the true and fallthrough blocks as its successors.
1140 BB->addSuccessor(copy0MBB);
1141 BB->addSuccessor(sinkMBB);
1143 // Emit the right instruction according to the type of the operands compared
1145 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
1147 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
1148 .addReg(Mips::ZERO).addMBB(sinkMBB);
1151 // %FalseValue = ...
1152 // # fallthrough to sinkMBB
1155 // Update machine-CFG edges
1156 BB->addSuccessor(sinkMBB);
1159 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1164 BuildMI(*BB, BB->begin(), dl,
1165 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1166 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1167 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1169 BuildMI(*BB, BB->begin(), dl,
1170 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1171 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1172 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1174 MI->eraseFromParent(); // The pseudo instruction is gone now.
1180 MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1182 // bposge32_pseudo $vr0
1192 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1194 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1195 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1196 const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1197 DebugLoc DL = MI->getDebugLoc();
1198 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1199 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1200 MachineFunction *F = BB->getParent();
1201 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1202 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1203 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1206 F->insert(It, Sink);
1208 // Transfer the remainder of BB and its successor edges to Sink.
1209 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1211 Sink->transferSuccessorsAndUpdatePHIs(BB);
1214 BB->addSuccessor(FBB);
1215 BB->addSuccessor(TBB);
1216 FBB->addSuccessor(Sink);
1217 TBB->addSuccessor(Sink);
1219 // Insert the real bposge32 instruction to $BB.
1220 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1223 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1224 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1225 .addReg(Mips::ZERO).addImm(0);
1226 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1229 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1230 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1231 .addReg(Mips::ZERO).addImm(1);
1233 // Insert phi function to $Sink.
1234 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1235 MI->getOperand(0).getReg())
1236 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1238 MI->eraseFromParent(); // The pseudo instruction is gone now.
1242 MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
1243 MachineBasicBlock *BB) const {
1244 if (DontExpandCondPseudos16)
1246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1247 DebugLoc dl = MI->getDebugLoc();
1248 // To "insert" a SELECT_CC instruction, we actually have to insert the
1249 // diamond control-flow pattern. The incoming instruction knows the
1250 // destination vreg to set, the condition code register to branch on, the
1251 // true/false values to select between, and a branch opcode to use.
1252 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1253 MachineFunction::iterator It = BB;
1260 // bNE r1, r0, copy1MBB
1261 // fallthrough --> copy0MBB
1262 MachineBasicBlock *thisMBB = BB;
1263 MachineFunction *F = BB->getParent();
1264 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1265 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1266 F->insert(It, copy0MBB);
1267 F->insert(It, sinkMBB);
1269 // Transfer the remainder of BB and its successor edges to sinkMBB.
1270 sinkMBB->splice(sinkMBB->begin(), BB,
1271 llvm::next(MachineBasicBlock::iterator(MI)),
1273 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1275 // Next, add the true and fallthrough blocks as its successors.
1276 BB->addSuccessor(copy0MBB);
1277 BB->addSuccessor(sinkMBB);
1279 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
1283 // %FalseValue = ...
1284 // # fallthrough to sinkMBB
1287 // Update machine-CFG edges
1288 BB->addSuccessor(sinkMBB);
1291 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1295 BuildMI(*BB, BB->begin(), dl,
1296 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1297 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1298 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1300 MI->eraseFromParent(); // The pseudo instruction is gone now.
1304 MachineBasicBlock *MipsTargetLowering::EmitSelT16
1305 (unsigned Opc1, unsigned Opc2,
1306 MachineInstr *MI, MachineBasicBlock *BB) const {
1307 if (DontExpandCondPseudos16)
1309 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1310 DebugLoc dl = MI->getDebugLoc();
1311 // To "insert" a SELECT_CC instruction, we actually have to insert the
1312 // diamond control-flow pattern. The incoming instruction knows the
1313 // destination vreg to set, the condition code register to branch on, the
1314 // true/false values to select between, and a branch opcode to use.
1315 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1316 MachineFunction::iterator It = BB;
1323 // bNE r1, r0, copy1MBB
1324 // fallthrough --> copy0MBB
1325 MachineBasicBlock *thisMBB = BB;
1326 MachineFunction *F = BB->getParent();
1327 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1328 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1329 F->insert(It, copy0MBB);
1330 F->insert(It, sinkMBB);
1332 // Transfer the remainder of BB and its successor edges to sinkMBB.
1333 sinkMBB->splice(sinkMBB->begin(), BB,
1334 llvm::next(MachineBasicBlock::iterator(MI)),
1336 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1338 // Next, add the true and fallthrough blocks as its successors.
1339 BB->addSuccessor(copy0MBB);
1340 BB->addSuccessor(sinkMBB);
1342 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1343 .addReg(MI->getOperand(4).getReg());
1344 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1347 // %FalseValue = ...
1348 // # fallthrough to sinkMBB
1351 // Update machine-CFG edges
1352 BB->addSuccessor(sinkMBB);
1355 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1359 BuildMI(*BB, BB->begin(), dl,
1360 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1361 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1362 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1364 MI->eraseFromParent(); // The pseudo instruction is gone now.
1370 MachineBasicBlock *MipsTargetLowering::EmitSeliT16
1371 (unsigned Opc1, unsigned Opc2,
1372 MachineInstr *MI, MachineBasicBlock *BB) const {
1373 if (DontExpandCondPseudos16)
1375 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1376 DebugLoc dl = MI->getDebugLoc();
1377 // To "insert" a SELECT_CC instruction, we actually have to insert the
1378 // diamond control-flow pattern. The incoming instruction knows the
1379 // destination vreg to set, the condition code register to branch on, the
1380 // true/false values to select between, and a branch opcode to use.
1381 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1382 MachineFunction::iterator It = BB;
1389 // bNE r1, r0, copy1MBB
1390 // fallthrough --> copy0MBB
1391 MachineBasicBlock *thisMBB = BB;
1392 MachineFunction *F = BB->getParent();
1393 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1394 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1395 F->insert(It, copy0MBB);
1396 F->insert(It, sinkMBB);
1398 // Transfer the remainder of BB and its successor edges to sinkMBB.
1399 sinkMBB->splice(sinkMBB->begin(), BB,
1400 llvm::next(MachineBasicBlock::iterator(MI)),
1402 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1404 // Next, add the true and fallthrough blocks as its successors.
1405 BB->addSuccessor(copy0MBB);
1406 BB->addSuccessor(sinkMBB);
1408 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1409 .addImm(MI->getOperand(4).getImm());
1410 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1413 // %FalseValue = ...
1414 // # fallthrough to sinkMBB
1417 // Update machine-CFG edges
1418 BB->addSuccessor(sinkMBB);
1421 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1425 BuildMI(*BB, BB->begin(), dl,
1426 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1427 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1428 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1430 MI->eraseFromParent(); // The pseudo instruction is gone now.
1437 *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
1439 MachineBasicBlock *BB) const {
1440 if (DontExpandCondPseudos16)
1442 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1443 unsigned regX = MI->getOperand(0).getReg();
1444 unsigned regY = MI->getOperand(1).getReg();
1445 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1446 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
1447 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1448 MI->eraseFromParent(); // The pseudo instruction is gone now.
1453 MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
1454 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
1455 MachineInstr *MI, MachineBasicBlock *BB) const {
1456 if (DontExpandCondPseudos16)
1458 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1459 unsigned regX = MI->getOperand(0).getReg();
1460 int64_t imm = MI->getOperand(1).getImm();
1461 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1465 else if (isUInt<16>(imm))
1468 llvm_unreachable("immediate field not usable");
1469 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
1470 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1471 MI->eraseFromParent(); // The pseudo instruction is gone now.
1476 static unsigned Mips16WhichOp8uOr16simm
1477 (unsigned shortOp, unsigned longOp, int64_t Imm) {
1480 else if (isInt<16>(Imm))
1483 llvm_unreachable("immediate field not usable");
1486 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRX16_ins(
1488 MachineInstr *MI, MachineBasicBlock *BB) const {
1489 if (DontExpandCondPseudos16)
1491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1492 unsigned CC = MI->getOperand(0).getReg();
1493 unsigned regX = MI->getOperand(1).getReg();
1494 unsigned regY = MI->getOperand(2).getReg();
1495 BuildMI(*BB, MI, MI->getDebugLoc(),
1496 TII->get(SltOpc)).addReg(regX).addReg(regY);
1497 BuildMI(*BB, MI, MI->getDebugLoc(),
1498 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1499 MI->eraseFromParent(); // The pseudo instruction is gone now.
1502 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRXI16_ins(
1503 unsigned SltiOpc, unsigned SltiXOpc,
1504 MachineInstr *MI, MachineBasicBlock *BB )const {
1505 if (DontExpandCondPseudos16)
1507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1508 unsigned CC = MI->getOperand(0).getReg();
1509 unsigned regX = MI->getOperand(1).getReg();
1510 int64_t Imm = MI->getOperand(2).getImm();
1511 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
1512 BuildMI(*BB, MI, MI->getDebugLoc(),
1513 TII->get(SltOpc)).addReg(regX).addImm(Imm);
1514 BuildMI(*BB, MI, MI->getDebugLoc(),
1515 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1516 MI->eraseFromParent(); // The pseudo instruction is gone now.
1521 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1522 MachineBasicBlock *BB) const {
1523 switch (MI->getOpcode()) {
1525 llvm_unreachable("Unexpected instr type to insert");
1526 case Mips::ATOMIC_LOAD_ADD_I8:
1527 case Mips::ATOMIC_LOAD_ADD_I8_P8:
1528 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1529 case Mips::ATOMIC_LOAD_ADD_I16:
1530 case Mips::ATOMIC_LOAD_ADD_I16_P8:
1531 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1532 case Mips::ATOMIC_LOAD_ADD_I32:
1533 case Mips::ATOMIC_LOAD_ADD_I32_P8:
1534 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1535 case Mips::ATOMIC_LOAD_ADD_I64:
1536 case Mips::ATOMIC_LOAD_ADD_I64_P8:
1537 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1539 case Mips::ATOMIC_LOAD_AND_I8:
1540 case Mips::ATOMIC_LOAD_AND_I8_P8:
1541 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1542 case Mips::ATOMIC_LOAD_AND_I16:
1543 case Mips::ATOMIC_LOAD_AND_I16_P8:
1544 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1545 case Mips::ATOMIC_LOAD_AND_I32:
1546 case Mips::ATOMIC_LOAD_AND_I32_P8:
1547 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1548 case Mips::ATOMIC_LOAD_AND_I64:
1549 case Mips::ATOMIC_LOAD_AND_I64_P8:
1550 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1552 case Mips::ATOMIC_LOAD_OR_I8:
1553 case Mips::ATOMIC_LOAD_OR_I8_P8:
1554 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1555 case Mips::ATOMIC_LOAD_OR_I16:
1556 case Mips::ATOMIC_LOAD_OR_I16_P8:
1557 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1558 case Mips::ATOMIC_LOAD_OR_I32:
1559 case Mips::ATOMIC_LOAD_OR_I32_P8:
1560 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1561 case Mips::ATOMIC_LOAD_OR_I64:
1562 case Mips::ATOMIC_LOAD_OR_I64_P8:
1563 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1565 case Mips::ATOMIC_LOAD_XOR_I8:
1566 case Mips::ATOMIC_LOAD_XOR_I8_P8:
1567 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1568 case Mips::ATOMIC_LOAD_XOR_I16:
1569 case Mips::ATOMIC_LOAD_XOR_I16_P8:
1570 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1571 case Mips::ATOMIC_LOAD_XOR_I32:
1572 case Mips::ATOMIC_LOAD_XOR_I32_P8:
1573 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1574 case Mips::ATOMIC_LOAD_XOR_I64:
1575 case Mips::ATOMIC_LOAD_XOR_I64_P8:
1576 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1578 case Mips::ATOMIC_LOAD_NAND_I8:
1579 case Mips::ATOMIC_LOAD_NAND_I8_P8:
1580 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1581 case Mips::ATOMIC_LOAD_NAND_I16:
1582 case Mips::ATOMIC_LOAD_NAND_I16_P8:
1583 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1584 case Mips::ATOMIC_LOAD_NAND_I32:
1585 case Mips::ATOMIC_LOAD_NAND_I32_P8:
1586 return EmitAtomicBinary(MI, BB, 4, 0, true);
1587 case Mips::ATOMIC_LOAD_NAND_I64:
1588 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1589 return EmitAtomicBinary(MI, BB, 8, 0, true);
1591 case Mips::ATOMIC_LOAD_SUB_I8:
1592 case Mips::ATOMIC_LOAD_SUB_I8_P8:
1593 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1594 case Mips::ATOMIC_LOAD_SUB_I16:
1595 case Mips::ATOMIC_LOAD_SUB_I16_P8:
1596 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1597 case Mips::ATOMIC_LOAD_SUB_I32:
1598 case Mips::ATOMIC_LOAD_SUB_I32_P8:
1599 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1600 case Mips::ATOMIC_LOAD_SUB_I64:
1601 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1602 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1604 case Mips::ATOMIC_SWAP_I8:
1605 case Mips::ATOMIC_SWAP_I8_P8:
1606 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1607 case Mips::ATOMIC_SWAP_I16:
1608 case Mips::ATOMIC_SWAP_I16_P8:
1609 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1610 case Mips::ATOMIC_SWAP_I32:
1611 case Mips::ATOMIC_SWAP_I32_P8:
1612 return EmitAtomicBinary(MI, BB, 4, 0);
1613 case Mips::ATOMIC_SWAP_I64:
1614 case Mips::ATOMIC_SWAP_I64_P8:
1615 return EmitAtomicBinary(MI, BB, 8, 0);
1617 case Mips::ATOMIC_CMP_SWAP_I8:
1618 case Mips::ATOMIC_CMP_SWAP_I8_P8:
1619 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1620 case Mips::ATOMIC_CMP_SWAP_I16:
1621 case Mips::ATOMIC_CMP_SWAP_I16_P8:
1622 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1623 case Mips::ATOMIC_CMP_SWAP_I32:
1624 case Mips::ATOMIC_CMP_SWAP_I32_P8:
1625 return EmitAtomicCmpSwap(MI, BB, 4);
1626 case Mips::ATOMIC_CMP_SWAP_I64:
1627 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1628 return EmitAtomicCmpSwap(MI, BB, 8);
1629 case Mips::BPOSGE32_PSEUDO:
1630 return EmitBPOSGE32(MI, BB);
1632 return EmitSel16(Mips::BeqzRxImm16, MI, BB);
1634 return EmitSel16(Mips::BnezRxImm16, MI, BB);
1635 case Mips::SelTBteqZCmpi:
1636 return EmitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
1637 case Mips::SelTBteqZSlti:
1638 return EmitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
1639 case Mips::SelTBteqZSltiu:
1640 return EmitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
1641 case Mips::SelTBtneZCmpi:
1642 return EmitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
1643 case Mips::SelTBtneZSlti:
1644 return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
1645 case Mips::SelTBtneZSltiu:
1646 return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
1647 case Mips::SelTBteqZCmp:
1648 return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1649 case Mips::SelTBteqZSlt:
1650 return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1651 case Mips::SelTBteqZSltu:
1652 return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1653 case Mips::SelTBtneZCmp:
1654 return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1655 case Mips::SelTBtneZSlt:
1656 return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1657 case Mips::SelTBtneZSltu:
1658 return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1659 case Mips::BteqzT8CmpX16:
1660 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1661 case Mips::BteqzT8SltX16:
1662 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1663 case Mips::BteqzT8SltuX16:
1664 // TBD: figure out a way to get this or remove the instruction
1666 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1667 case Mips::BtnezT8CmpX16:
1668 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1669 case Mips::BtnezT8SltX16:
1670 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1671 case Mips::BtnezT8SltuX16:
1672 // TBD: figure out a way to get this or remove the instruction
1674 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1675 case Mips::BteqzT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1676 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1677 case Mips::BteqzT8SltiX16: return EmitFEXT_T8I8I16_ins(
1678 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1679 case Mips::BteqzT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1680 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1681 case Mips::BtnezT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1682 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1683 case Mips::BtnezT8SltiX16: return EmitFEXT_T8I8I16_ins(
1684 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1685 case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1686 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1688 case Mips::SltCCRxRy16:
1689 return EmitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
1691 case Mips::SltiCCRxImmX16:
1692 return EmitFEXT_CCRXI16_ins
1693 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1694 case Mips::SltiuCCRxImmX16:
1695 return EmitFEXT_CCRXI16_ins
1696 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1697 case Mips::SltuCCRxRy16:
1698 return EmitFEXT_CCRX16_ins
1699 (Mips::SltuRxRy16, MI, BB);
1703 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1704 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1706 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1707 unsigned Size, unsigned BinOpcode,
1709 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1711 MachineFunction *MF = BB->getParent();
1712 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1713 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1714 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1715 DebugLoc dl = MI->getDebugLoc();
1716 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1719 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1720 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1727 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1728 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1731 ZERO = Mips::ZERO_64;
1735 unsigned OldVal = MI->getOperand(0).getReg();
1736 unsigned Ptr = MI->getOperand(1).getReg();
1737 unsigned Incr = MI->getOperand(2).getReg();
1739 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1740 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1741 unsigned Success = RegInfo.createVirtualRegister(RC);
1743 // insert new blocks after the current block
1744 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1745 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1746 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1747 MachineFunction::iterator It = BB;
1749 MF->insert(It, loopMBB);
1750 MF->insert(It, exitMBB);
1752 // Transfer the remainder of BB and its successor edges to exitMBB.
1753 exitMBB->splice(exitMBB->begin(), BB,
1754 llvm::next(MachineBasicBlock::iterator(MI)),
1756 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1760 // fallthrough --> loopMBB
1761 BB->addSuccessor(loopMBB);
1762 loopMBB->addSuccessor(loopMBB);
1763 loopMBB->addSuccessor(exitMBB);
1766 // ll oldval, 0(ptr)
1767 // <binop> storeval, oldval, incr
1768 // sc success, storeval, 0(ptr)
1769 // beq success, $0, loopMBB
1771 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1773 // and andres, oldval, incr
1774 // nor storeval, $0, andres
1775 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1776 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1777 } else if (BinOpcode) {
1778 // <binop> storeval, oldval, incr
1779 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1783 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1784 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1786 MI->eraseFromParent(); // The instruction is gone now.
1792 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1793 MachineBasicBlock *BB,
1794 unsigned Size, unsigned BinOpcode,
1796 assert((Size == 1 || Size == 2) &&
1797 "Unsupported size for EmitAtomicBinaryPartial.");
1799 MachineFunction *MF = BB->getParent();
1800 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1801 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1802 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1803 DebugLoc dl = MI->getDebugLoc();
1804 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1805 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1807 unsigned Dest = MI->getOperand(0).getReg();
1808 unsigned Ptr = MI->getOperand(1).getReg();
1809 unsigned Incr = MI->getOperand(2).getReg();
1811 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1812 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1813 unsigned Mask = RegInfo.createVirtualRegister(RC);
1814 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1815 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1816 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1817 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1818 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1819 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1820 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1821 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1822 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1823 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1824 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1825 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1826 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1827 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1828 unsigned Success = RegInfo.createVirtualRegister(RC);
1830 // insert new blocks after the current block
1831 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1832 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1833 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1834 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1835 MachineFunction::iterator It = BB;
1837 MF->insert(It, loopMBB);
1838 MF->insert(It, sinkMBB);
1839 MF->insert(It, exitMBB);
1841 // Transfer the remainder of BB and its successor edges to exitMBB.
1842 exitMBB->splice(exitMBB->begin(), BB,
1843 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1844 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1846 BB->addSuccessor(loopMBB);
1847 loopMBB->addSuccessor(loopMBB);
1848 loopMBB->addSuccessor(sinkMBB);
1849 sinkMBB->addSuccessor(exitMBB);
1852 // addiu masklsb2,$0,-4 # 0xfffffffc
1853 // and alignedaddr,ptr,masklsb2
1854 // andi ptrlsb2,ptr,3
1855 // sll shiftamt,ptrlsb2,3
1856 // ori maskupper,$0,255 # 0xff
1857 // sll mask,maskupper,shiftamt
1858 // nor mask2,$0,mask
1859 // sll incr2,incr,shiftamt
1861 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1862 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1863 .addReg(Mips::ZERO).addImm(-4);
1864 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1865 .addReg(Ptr).addReg(MaskLSB2);
1866 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1867 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1868 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1869 .addReg(Mips::ZERO).addImm(MaskImm);
1870 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1871 .addReg(ShiftAmt).addReg(MaskUpper);
1872 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1873 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1875 // atomic.load.binop
1877 // ll oldval,0(alignedaddr)
1878 // binop binopres,oldval,incr2
1879 // and newval,binopres,mask
1880 // and maskedoldval0,oldval,mask2
1881 // or storeval,maskedoldval0,newval
1882 // sc success,storeval,0(alignedaddr)
1883 // beq success,$0,loopMBB
1887 // ll oldval,0(alignedaddr)
1888 // and newval,incr2,mask
1889 // and maskedoldval0,oldval,mask2
1890 // or storeval,maskedoldval0,newval
1891 // sc success,storeval,0(alignedaddr)
1892 // beq success,$0,loopMBB
1895 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1897 // and andres, oldval, incr2
1898 // nor binopres, $0, andres
1899 // and newval, binopres, mask
1900 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1901 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1902 .addReg(Mips::ZERO).addReg(AndRes);
1903 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1904 } else if (BinOpcode) {
1905 // <binop> binopres, oldval, incr2
1906 // and newval, binopres, mask
1907 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1908 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1909 } else {// atomic.swap
1910 // and newval, incr2, mask
1911 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1914 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1915 .addReg(OldVal).addReg(Mask2);
1916 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1917 .addReg(MaskedOldVal0).addReg(NewVal);
1918 BuildMI(BB, dl, TII->get(SC), Success)
1919 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1920 BuildMI(BB, dl, TII->get(Mips::BEQ))
1921 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1924 // and maskedoldval1,oldval,mask
1925 // srl srlres,maskedoldval1,shiftamt
1926 // sll sllres,srlres,24
1927 // sra dest,sllres,24
1929 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1931 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1932 .addReg(OldVal).addReg(Mask);
1933 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1934 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1935 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1936 .addReg(SrlRes).addImm(ShiftImm);
1937 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1938 .addReg(SllRes).addImm(ShiftImm);
1940 MI->eraseFromParent(); // The instruction is gone now.
1946 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1947 MachineBasicBlock *BB,
1948 unsigned Size) const {
1949 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1951 MachineFunction *MF = BB->getParent();
1952 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1953 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1954 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1955 DebugLoc dl = MI->getDebugLoc();
1956 unsigned LL, SC, ZERO, BNE, BEQ;
1959 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1960 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1966 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1967 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1968 ZERO = Mips::ZERO_64;
1973 unsigned Dest = MI->getOperand(0).getReg();
1974 unsigned Ptr = MI->getOperand(1).getReg();
1975 unsigned OldVal = MI->getOperand(2).getReg();
1976 unsigned NewVal = MI->getOperand(3).getReg();
1978 unsigned Success = RegInfo.createVirtualRegister(RC);
1980 // insert new blocks after the current block
1981 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1982 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1983 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1984 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1985 MachineFunction::iterator It = BB;
1987 MF->insert(It, loop1MBB);
1988 MF->insert(It, loop2MBB);
1989 MF->insert(It, exitMBB);
1991 // Transfer the remainder of BB and its successor edges to exitMBB.
1992 exitMBB->splice(exitMBB->begin(), BB,
1993 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1994 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1998 // fallthrough --> loop1MBB
1999 BB->addSuccessor(loop1MBB);
2000 loop1MBB->addSuccessor(exitMBB);
2001 loop1MBB->addSuccessor(loop2MBB);
2002 loop2MBB->addSuccessor(loop1MBB);
2003 loop2MBB->addSuccessor(exitMBB);
2007 // bne dest, oldval, exitMBB
2009 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
2010 BuildMI(BB, dl, TII->get(BNE))
2011 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
2014 // sc success, newval, 0(ptr)
2015 // beq success, $0, loop1MBB
2017 BuildMI(BB, dl, TII->get(SC), Success)
2018 .addReg(NewVal).addReg(Ptr).addImm(0);
2019 BuildMI(BB, dl, TII->get(BEQ))
2020 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
2022 MI->eraseFromParent(); // The instruction is gone now.
2028 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
2029 MachineBasicBlock *BB,
2030 unsigned Size) const {
2031 assert((Size == 1 || Size == 2) &&
2032 "Unsupported size for EmitAtomicCmpSwapPartial.");
2034 MachineFunction *MF = BB->getParent();
2035 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2036 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
2037 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2038 DebugLoc dl = MI->getDebugLoc();
2039 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
2040 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
2042 unsigned Dest = MI->getOperand(0).getReg();
2043 unsigned Ptr = MI->getOperand(1).getReg();
2044 unsigned CmpVal = MI->getOperand(2).getReg();
2045 unsigned NewVal = MI->getOperand(3).getReg();
2047 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
2048 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
2049 unsigned Mask = RegInfo.createVirtualRegister(RC);
2050 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
2051 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
2052 unsigned OldVal = RegInfo.createVirtualRegister(RC);
2053 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
2054 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
2055 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
2056 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
2057 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
2058 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
2059 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
2060 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
2061 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
2062 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
2063 unsigned SllRes = RegInfo.createVirtualRegister(RC);
2064 unsigned Success = RegInfo.createVirtualRegister(RC);
2066 // insert new blocks after the current block
2067 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2068 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2069 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2070 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2071 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2072 MachineFunction::iterator It = BB;
2074 MF->insert(It, loop1MBB);
2075 MF->insert(It, loop2MBB);
2076 MF->insert(It, sinkMBB);
2077 MF->insert(It, exitMBB);
2079 // Transfer the remainder of BB and its successor edges to exitMBB.
2080 exitMBB->splice(exitMBB->begin(), BB,
2081 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
2082 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
2084 BB->addSuccessor(loop1MBB);
2085 loop1MBB->addSuccessor(sinkMBB);
2086 loop1MBB->addSuccessor(loop2MBB);
2087 loop2MBB->addSuccessor(loop1MBB);
2088 loop2MBB->addSuccessor(sinkMBB);
2089 sinkMBB->addSuccessor(exitMBB);
2091 // FIXME: computation of newval2 can be moved to loop2MBB.
2093 // addiu masklsb2,$0,-4 # 0xfffffffc
2094 // and alignedaddr,ptr,masklsb2
2095 // andi ptrlsb2,ptr,3
2096 // sll shiftamt,ptrlsb2,3
2097 // ori maskupper,$0,255 # 0xff
2098 // sll mask,maskupper,shiftamt
2099 // nor mask2,$0,mask
2100 // andi maskedcmpval,cmpval,255
2101 // sll shiftedcmpval,maskedcmpval,shiftamt
2102 // andi maskednewval,newval,255
2103 // sll shiftednewval,maskednewval,shiftamt
2104 int64_t MaskImm = (Size == 1) ? 255 : 65535;
2105 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
2106 .addReg(Mips::ZERO).addImm(-4);
2107 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
2108 .addReg(Ptr).addReg(MaskLSB2);
2109 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
2110 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
2111 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
2112 .addReg(Mips::ZERO).addImm(MaskImm);
2113 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
2114 .addReg(ShiftAmt).addReg(MaskUpper);
2115 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2116 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
2117 .addReg(CmpVal).addImm(MaskImm);
2118 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
2119 .addReg(ShiftAmt).addReg(MaskedCmpVal);
2120 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
2121 .addReg(NewVal).addImm(MaskImm);
2122 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
2123 .addReg(ShiftAmt).addReg(MaskedNewVal);
2126 // ll oldval,0(alginedaddr)
2127 // and maskedoldval0,oldval,mask
2128 // bne maskedoldval0,shiftedcmpval,sinkMBB
2130 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
2131 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
2132 .addReg(OldVal).addReg(Mask);
2133 BuildMI(BB, dl, TII->get(Mips::BNE))
2134 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
2137 // and maskedoldval1,oldval,mask2
2138 // or storeval,maskedoldval1,shiftednewval
2139 // sc success,storeval,0(alignedaddr)
2140 // beq success,$0,loop1MBB
2142 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
2143 .addReg(OldVal).addReg(Mask2);
2144 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
2145 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
2146 BuildMI(BB, dl, TII->get(SC), Success)
2147 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
2148 BuildMI(BB, dl, TII->get(Mips::BEQ))
2149 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
2152 // srl srlres,maskedoldval0,shiftamt
2153 // sll sllres,srlres,24
2154 // sra dest,sllres,24
2156 int64_t ShiftImm = (Size == 1) ? 24 : 16;
2158 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
2159 .addReg(ShiftAmt).addReg(MaskedOldVal0);
2160 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
2161 .addReg(SrlRes).addImm(ShiftImm);
2162 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
2163 .addReg(SllRes).addImm(ShiftImm);
2165 MI->eraseFromParent(); // The instruction is gone now.
2170 //===----------------------------------------------------------------------===//
2171 // Misc Lower Operation implementation
2172 //===----------------------------------------------------------------------===//
2173 SDValue MipsTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2174 SDValue Chain = Op.getOperand(0);
2175 SDValue Table = Op.getOperand(1);
2176 SDValue Index = Op.getOperand(2);
2177 DebugLoc DL = Op.getDebugLoc();
2178 EVT PTy = getPointerTy();
2179 unsigned EntrySize =
2180 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
2182 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
2183 DAG.getConstant(EntrySize, PTy));
2184 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
2186 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2187 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
2188 MachinePointerInfo::getJumpTable(), MemVT, false, false,
2190 Chain = Addr.getValue(1);
2192 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
2193 // For PIC, the sequence is:
2194 // BRIND(load(Jumptable + index) + RelocBase)
2195 // RelocBase can be JumpTable, GOT or some sort of global base.
2196 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
2197 getPICJumpTableRelocBase(Table, DAG));
2200 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
2203 SDValue MipsTargetLowering::
2204 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
2206 // The first operand is the chain, the second is the condition, the third is
2207 // the block to branch to if the condition is true.
2208 SDValue Chain = Op.getOperand(0);
2209 SDValue Dest = Op.getOperand(2);
2210 DebugLoc dl = Op.getDebugLoc();
2212 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
2214 // Return if flag is not set by a floating point comparison.
2215 if (CondRes.getOpcode() != MipsISD::FPCmp)
2218 SDValue CCNode = CondRes.getOperand(2);
2220 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2221 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
2223 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
2227 SDValue MipsTargetLowering::
2228 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
2230 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
2232 // Return if flag is not set by a floating point comparison.
2233 if (Cond.getOpcode() != MipsISD::FPCmp)
2236 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2240 SDValue MipsTargetLowering::
2241 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
2243 DebugLoc DL = Op.getDebugLoc();
2244 EVT Ty = Op.getOperand(0).getValueType();
2245 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
2246 Op.getOperand(0), Op.getOperand(1),
2249 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
2253 SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2254 SDValue Cond = CreateFPCmp(DAG, Op);
2256 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2257 "Floating point operand expected.");
2259 SDValue True = DAG.getConstant(1, MVT::i32);
2260 SDValue False = DAG.getConstant(0, MVT::i32);
2262 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
2265 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
2266 SelectionDAG &DAG) const {
2267 // FIXME there isn't actually debug info here
2268 DebugLoc dl = Op.getDebugLoc();
2269 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2271 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
2272 const MipsTargetObjectFile &TLOF =
2273 (const MipsTargetObjectFile&)getObjFileLowering();
2275 // %gp_rel relocation
2276 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
2277 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
2279 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl,
2280 DAG.getVTList(MVT::i32), &GA, 1);
2281 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
2282 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
2285 // %hi/%lo relocation
2286 return getAddrNonPIC(Op, DAG);
2289 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
2290 return getAddrLocal(Op, DAG, HasMips64);
2293 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
2294 MipsII::MO_GOT_LO16);
2296 return getAddrGlobal(Op, DAG,
2297 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
2300 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
2301 SelectionDAG &DAG) const {
2302 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2303 return getAddrNonPIC(Op, DAG);
2305 return getAddrLocal(Op, DAG, HasMips64);
2308 SDValue MipsTargetLowering::
2309 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2311 // If the relocation model is PIC, use the General Dynamic TLS Model or
2312 // Local Dynamic TLS model, otherwise use the Initial Exec or
2313 // Local Exec TLS Model.
2315 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2316 DebugLoc dl = GA->getDebugLoc();
2317 const GlobalValue *GV = GA->getGlobal();
2318 EVT PtrVT = getPointerTy();
2320 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2322 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2323 // General Dynamic and Local Dynamic TLS Model.
2324 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2327 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
2328 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
2329 GetGlobalReg(DAG, PtrVT), TGA);
2330 unsigned PtrSize = PtrVT.getSizeInBits();
2331 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2333 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2337 Entry.Node = Argument;
2339 Args.push_back(Entry);
2341 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
2342 false, false, false, false, 0, CallingConv::C,
2343 /*isTailCall=*/false, /*doesNotRet=*/false,
2344 /*isReturnValueUsed=*/true,
2345 TlsGetAddr, Args, DAG, dl);
2346 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2348 SDValue Ret = CallResult.first;
2350 if (model != TLSModel::LocalDynamic)
2353 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2354 MipsII::MO_DTPREL_HI);
2355 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2356 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2357 MipsII::MO_DTPREL_LO);
2358 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2359 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
2360 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
2364 if (model == TLSModel::InitialExec) {
2365 // Initial Exec TLS Model
2366 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2367 MipsII::MO_GOTTPREL);
2368 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
2370 Offset = DAG.getLoad(PtrVT, dl,
2371 DAG.getEntryNode(), TGA, MachinePointerInfo(),
2372 false, false, false, 0);
2374 // Local Exec TLS Model
2375 assert(model == TLSModel::LocalExec);
2376 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2377 MipsII::MO_TPREL_HI);
2378 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2379 MipsII::MO_TPREL_LO);
2380 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2381 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2382 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
2385 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
2386 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2389 SDValue MipsTargetLowering::
2390 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2392 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2393 return getAddrNonPIC(Op, DAG);
2395 return getAddrLocal(Op, DAG, HasMips64);
2398 SDValue MipsTargetLowering::
2399 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2401 // gp_rel relocation
2402 // FIXME: we should reference the constant pool using small data sections,
2403 // but the asm printer currently doesn't support this feature without
2404 // hacking it. This feature should come soon so we can uncomment the
2406 //if (IsInSmallSection(C->getType())) {
2407 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
2408 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
2409 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
2411 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2412 return getAddrNonPIC(Op, DAG);
2414 return getAddrLocal(Op, DAG, HasMips64);
2417 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2418 MachineFunction &MF = DAG.getMachineFunction();
2419 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2421 DebugLoc dl = Op.getDebugLoc();
2422 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2425 // vastart just stores the address of the VarArgsFrameIndex slot into the
2426 // memory location argument.
2427 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2428 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
2429 MachinePointerInfo(SV), false, false, 0);
2432 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2433 EVT TyX = Op.getOperand(0).getValueType();
2434 EVT TyY = Op.getOperand(1).getValueType();
2435 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2436 SDValue Const31 = DAG.getConstant(31, MVT::i32);
2437 DebugLoc DL = Op.getDebugLoc();
2440 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2442 SDValue X = (TyX == MVT::f32) ?
2443 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2444 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2446 SDValue Y = (TyY == MVT::f32) ?
2447 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2448 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2452 // ext E, Y, 31, 1 ; extract bit31 of Y
2453 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2454 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2455 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2458 // srl SrlX, SllX, 1
2460 // sll SllY, SrlX, 31
2461 // or Or, SrlX, SllY
2462 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2463 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2464 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2465 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2466 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2469 if (TyX == MVT::f32)
2470 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2472 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2473 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2474 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2477 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2478 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2479 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2480 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2481 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2482 DebugLoc DL = Op.getDebugLoc();
2484 // Bitcast to integer nodes.
2485 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2486 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2489 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2490 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2491 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2492 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2494 if (WidthX > WidthY)
2495 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2496 else if (WidthY > WidthX)
2497 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2499 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2500 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2501 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2504 // (d)sll SllX, X, 1
2505 // (d)srl SrlX, SllX, 1
2506 // (d)srl SrlY, Y, width(Y)-1
2507 // (d)sll SllY, SrlX, width(Y)-1
2508 // or Or, SrlX, SllY
2509 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2510 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2511 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2512 DAG.getConstant(WidthY - 1, MVT::i32));
2514 if (WidthX > WidthY)
2515 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2516 else if (WidthY > WidthX)
2517 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2519 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2520 DAG.getConstant(WidthX - 1, MVT::i32));
2521 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2522 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2526 MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2527 if (Subtarget->hasMips64())
2528 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2530 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2533 static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2534 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2535 DebugLoc DL = Op.getDebugLoc();
2537 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2539 SDValue X = (Op.getValueType() == MVT::f32) ?
2540 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2541 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2546 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2547 DAG.getRegister(Mips::ZERO, MVT::i32),
2548 DAG.getConstant(31, MVT::i32), Const1, X);
2550 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2551 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2554 if (Op.getValueType() == MVT::f32)
2555 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2557 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2558 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2559 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2562 static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2563 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2564 DebugLoc DL = Op.getDebugLoc();
2566 // Bitcast to integer node.
2567 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2571 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2572 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2573 DAG.getConstant(63, MVT::i32), Const1, X);
2575 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2576 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2579 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2583 MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2584 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2585 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2587 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2590 SDValue MipsTargetLowering::
2591 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2593 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2594 "Frame address can only be determined for current frame.");
2596 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2597 MFI->setFrameAddressIsTaken(true);
2598 EVT VT = Op.getValueType();
2599 DebugLoc dl = Op.getDebugLoc();
2600 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2601 IsN64 ? Mips::FP_64 : Mips::FP, VT);
2605 SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2606 SelectionDAG &DAG) const {
2608 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2609 "Return address can be determined only for current frame.");
2611 MachineFunction &MF = DAG.getMachineFunction();
2612 MachineFrameInfo *MFI = MF.getFrameInfo();
2613 MVT VT = Op.getSimpleValueType();
2614 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2615 MFI->setReturnAddressIsTaken(true);
2617 // Return RA, which contains the return address. Mark it an implicit live-in.
2618 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2619 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2622 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2623 // generated from __builtin_eh_return (offset, handler)
2624 // The effect of this is to adjust the stack pointer by "offset"
2625 // and then branch to "handler".
2626 SDValue MipsTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2628 MachineFunction &MF = DAG.getMachineFunction();
2629 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2631 MipsFI->setCallsEhReturn();
2632 SDValue Chain = Op.getOperand(0);
2633 SDValue Offset = Op.getOperand(1);
2634 SDValue Handler = Op.getOperand(2);
2635 DebugLoc DL = Op.getDebugLoc();
2636 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2638 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2639 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2640 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
2641 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
2642 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2643 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2644 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2645 DAG.getRegister(OffsetReg, Ty),
2646 DAG.getRegister(AddrReg, getPointerTy()),
2650 // TODO: set SType according to the desired memory barrier behavior.
2652 MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2654 DebugLoc dl = Op.getDebugLoc();
2655 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2656 DAG.getConstant(SType, MVT::i32));
2659 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2660 SelectionDAG &DAG) const {
2661 // FIXME: Need pseudo-fence for 'singlethread' fences
2662 // FIXME: Set SType for weaker fences where supported/appropriate.
2664 DebugLoc dl = Op.getDebugLoc();
2665 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2666 DAG.getConstant(SType, MVT::i32));
2669 SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2670 SelectionDAG &DAG) const {
2671 DebugLoc DL = Op.getDebugLoc();
2672 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2673 SDValue Shamt = Op.getOperand(2);
2676 // lo = (shl lo, shamt)
2677 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2680 // hi = (shl lo, shamt[4:0])
2681 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2682 DAG.getConstant(-1, MVT::i32));
2683 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2684 DAG.getConstant(1, MVT::i32));
2685 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2687 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2688 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2689 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2690 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2691 DAG.getConstant(0x20, MVT::i32));
2692 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2693 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2694 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2696 SDValue Ops[2] = {Lo, Hi};
2697 return DAG.getMergeValues(Ops, 2, DL);
2700 SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2702 DebugLoc DL = Op.getDebugLoc();
2703 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2704 SDValue Shamt = Op.getOperand(2);
2707 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2709 // hi = (sra hi, shamt)
2711 // hi = (srl hi, shamt)
2714 // lo = (sra hi, shamt[4:0])
2715 // hi = (sra hi, 31)
2717 // lo = (srl hi, shamt[4:0])
2719 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2720 DAG.getConstant(-1, MVT::i32));
2721 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2722 DAG.getConstant(1, MVT::i32));
2723 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2724 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2725 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2726 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2728 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2729 DAG.getConstant(0x20, MVT::i32));
2730 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2731 DAG.getConstant(31, MVT::i32));
2732 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2733 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2734 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2737 SDValue Ops[2] = {Lo, Hi};
2738 return DAG.getMergeValues(Ops, 2, DL);
2741 static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2742 SDValue Chain, SDValue Src, unsigned Offset) {
2743 SDValue Ptr = LD->getBasePtr();
2744 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2745 EVT BasePtrVT = Ptr.getValueType();
2746 DebugLoc DL = LD->getDebugLoc();
2747 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2750 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2751 DAG.getConstant(Offset, BasePtrVT));
2753 SDValue Ops[] = { Chain, Ptr, Src };
2754 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2755 LD->getMemOperand());
2758 // Expand an unaligned 32 or 64-bit integer load node.
2759 SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2760 LoadSDNode *LD = cast<LoadSDNode>(Op);
2761 EVT MemVT = LD->getMemoryVT();
2763 // Return if load is aligned or if MemVT is neither i32 nor i64.
2764 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2765 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2768 bool IsLittle = Subtarget->isLittle();
2769 EVT VT = Op.getValueType();
2770 ISD::LoadExtType ExtType = LD->getExtensionType();
2771 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2773 assert((VT == MVT::i32) || (VT == MVT::i64));
2776 // (set dst, (i64 (load baseptr)))
2778 // (set tmp, (ldl (add baseptr, 7), undef))
2779 // (set dst, (ldr baseptr, tmp))
2780 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2781 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2783 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2787 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2789 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2793 // (set dst, (i32 (load baseptr))) or
2794 // (set dst, (i64 (sextload baseptr))) or
2795 // (set dst, (i64 (extload baseptr)))
2797 // (set tmp, (lwl (add baseptr, 3), undef))
2798 // (set dst, (lwr baseptr, tmp))
2799 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2800 (ExtType == ISD::EXTLOAD))
2803 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2806 // (set dst, (i64 (zextload baseptr)))
2808 // (set tmp0, (lwl (add baseptr, 3), undef))
2809 // (set tmp1, (lwr baseptr, tmp0))
2810 // (set tmp2, (shl tmp1, 32))
2811 // (set dst, (srl tmp2, 32))
2812 DebugLoc DL = LD->getDebugLoc();
2813 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2814 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2815 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2816 SDValue Ops[] = { SRL, LWR.getValue(1) };
2817 return DAG.getMergeValues(Ops, 2, DL);
2820 static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2821 SDValue Chain, unsigned Offset) {
2822 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2823 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2824 DebugLoc DL = SD->getDebugLoc();
2825 SDVTList VTList = DAG.getVTList(MVT::Other);
2828 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2829 DAG.getConstant(Offset, BasePtrVT));
2831 SDValue Ops[] = { Chain, Value, Ptr };
2832 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2833 SD->getMemOperand());
2836 // Expand an unaligned 32 or 64-bit integer store node.
2837 SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2838 StoreSDNode *SD = cast<StoreSDNode>(Op);
2839 EVT MemVT = SD->getMemoryVT();
2841 // Return if store is aligned or if MemVT is neither i32 nor i64.
2842 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2843 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2846 bool IsLittle = Subtarget->isLittle();
2847 SDValue Value = SD->getValue(), Chain = SD->getChain();
2848 EVT VT = Value.getValueType();
2851 // (store val, baseptr) or
2852 // (truncstore val, baseptr)
2854 // (swl val, (add baseptr, 3))
2855 // (swr val, baseptr)
2856 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2857 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2859 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2862 assert(VT == MVT::i64);
2865 // (store val, baseptr)
2867 // (sdl val, (add baseptr, 7))
2868 // (sdr val, baseptr)
2869 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2870 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2873 // This function expands mips intrinsic nodes which have 64-bit input operands
2874 // or output values.
2876 // out64 = intrinsic-node in64
2878 // lo = copy (extract-element (in64, 0))
2879 // hi = copy (extract-element (in64, 1))
2880 // mips-specific-node
2883 // out64 = merge-values (v0, v1)
2885 static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2886 unsigned Opc, bool HasI64In, bool HasI64Out) {
2887 DebugLoc DL = Op.getDebugLoc();
2888 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2889 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2890 SmallVector<SDValue, 3> Ops;
2893 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2894 Op->getOperand(1 + HasChainIn),
2895 DAG.getConstant(0, MVT::i32));
2896 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2897 Op->getOperand(1 + HasChainIn),
2898 DAG.getConstant(1, MVT::i32));
2900 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2901 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2903 Ops.push_back(Chain);
2904 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2905 Ops.push_back(Chain.getValue(1));
2907 Ops.push_back(Chain);
2908 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2912 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2913 Ops.begin(), Ops.size());
2915 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2916 Ops.begin(), Ops.size());
2917 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2919 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2921 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2926 SDValue Vals[] = { Out, OutHi.getValue(1) };
2927 return DAG.getMergeValues(Vals, 2, DL);
2930 SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2931 SelectionDAG &DAG) const {
2932 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2935 case Intrinsic::mips_shilo:
2936 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2937 case Intrinsic::mips_dpau_h_qbl:
2938 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2939 case Intrinsic::mips_dpau_h_qbr:
2940 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2941 case Intrinsic::mips_dpsu_h_qbl:
2942 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2943 case Intrinsic::mips_dpsu_h_qbr:
2944 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2945 case Intrinsic::mips_dpa_w_ph:
2946 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2947 case Intrinsic::mips_dps_w_ph:
2948 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2949 case Intrinsic::mips_dpax_w_ph:
2950 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2951 case Intrinsic::mips_dpsx_w_ph:
2952 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2953 case Intrinsic::mips_mulsa_w_ph:
2954 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2955 case Intrinsic::mips_mult:
2956 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2957 case Intrinsic::mips_multu:
2958 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2959 case Intrinsic::mips_madd:
2960 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2961 case Intrinsic::mips_maddu:
2962 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2963 case Intrinsic::mips_msub:
2964 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2965 case Intrinsic::mips_msubu:
2966 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2970 SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2971 SelectionDAG &DAG) const {
2972 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2975 case Intrinsic::mips_extp:
2976 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2977 case Intrinsic::mips_extpdp:
2978 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2979 case Intrinsic::mips_extr_w:
2980 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2981 case Intrinsic::mips_extr_r_w:
2982 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2983 case Intrinsic::mips_extr_rs_w:
2984 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2985 case Intrinsic::mips_extr_s_h:
2986 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2987 case Intrinsic::mips_mthlip:
2988 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2989 case Intrinsic::mips_mulsaq_s_w_ph:
2990 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2991 case Intrinsic::mips_maq_s_w_phl:
2992 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2993 case Intrinsic::mips_maq_s_w_phr:
2994 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2995 case Intrinsic::mips_maq_sa_w_phl:
2996 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2997 case Intrinsic::mips_maq_sa_w_phr:
2998 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2999 case Intrinsic::mips_dpaq_s_w_ph:
3000 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
3001 case Intrinsic::mips_dpsq_s_w_ph:
3002 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
3003 case Intrinsic::mips_dpaq_sa_l_w:
3004 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
3005 case Intrinsic::mips_dpsq_sa_l_w:
3006 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
3007 case Intrinsic::mips_dpaqx_s_w_ph:
3008 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
3009 case Intrinsic::mips_dpaqx_sa_w_ph:
3010 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
3011 case Intrinsic::mips_dpsqx_s_w_ph:
3012 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
3013 case Intrinsic::mips_dpsqx_sa_w_ph:
3014 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
3018 SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
3019 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
3020 || cast<ConstantSDNode>
3021 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
3022 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
3026 // (add (frameaddr 0), (frame_to_args_offset))
3027 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
3028 // (add FrameObject, 0)
3029 // where FrameObject is a fixed StackObject with offset 0 which points to
3030 // the old stack pointer.
3031 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3032 EVT ValTy = Op->getValueType(0);
3033 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
3034 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
3035 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
3036 DAG.getConstant(0, ValTy));
3039 //===----------------------------------------------------------------------===//
3040 // Calling Convention Implementation
3041 //===----------------------------------------------------------------------===//
3043 //===----------------------------------------------------------------------===//
3044 // TODO: Implement a generic logic using tblgen that can support this.
3045 // Mips O32 ABI rules:
3047 // i32 - Passed in A0, A1, A2, A3 and stack
3048 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
3049 // an argument. Otherwise, passed in A1, A2, A3 and stack.
3050 // f64 - Only passed in two aliased f32 registers if no int reg has been used
3051 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
3052 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
3055 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
3056 //===----------------------------------------------------------------------===//
3058 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
3059 MVT LocVT, CCValAssign::LocInfo LocInfo,
3060 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3062 static const unsigned IntRegsSize=4, FloatRegsSize=2;
3064 static const uint16_t IntRegs[] = {
3065 Mips::A0, Mips::A1, Mips::A2, Mips::A3
3067 static const uint16_t F32Regs[] = {
3068 Mips::F12, Mips::F14
3070 static const uint16_t F64Regs[] = {
3074 // Do not process byval args here.
3075 if (ArgFlags.isByVal())
3078 // Promote i8 and i16
3079 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3081 if (ArgFlags.isSExt())
3082 LocInfo = CCValAssign::SExt;
3083 else if (ArgFlags.isZExt())
3084 LocInfo = CCValAssign::ZExt;
3086 LocInfo = CCValAssign::AExt;
3091 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
3092 // is true: function is vararg, argument is 3rd or higher, there is previous
3093 // argument which is not f32 or f64.
3094 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
3095 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
3096 unsigned OrigAlign = ArgFlags.getOrigAlign();
3097 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
3099 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3100 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3101 // If this is the first part of an i64 arg,
3102 // the allocated register must be either A0 or A2.
3103 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3104 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3106 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3107 // Allocate int register and shadow next int register. If first
3108 // available register is Mips::A1 or Mips::A3, shadow it too.
3109 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3110 if (Reg == Mips::A1 || Reg == Mips::A3)
3111 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3112 State.AllocateReg(IntRegs, IntRegsSize);
3114 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3115 // we are guaranteed to find an available float register
3116 if (ValVT == MVT::f32) {
3117 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
3118 // Shadow int register
3119 State.AllocateReg(IntRegs, IntRegsSize);
3121 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
3122 // Shadow int registers
3123 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
3124 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3125 State.AllocateReg(IntRegs, IntRegsSize);
3126 State.AllocateReg(IntRegs, IntRegsSize);
3129 llvm_unreachable("Cannot handle this ValVT.");
3132 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
3134 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
3136 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3141 #include "MipsGenCallingConv.inc"
3143 //===----------------------------------------------------------------------===//
3144 // Call Calling Convention Implementation
3145 //===----------------------------------------------------------------------===//
3147 static const unsigned O32IntRegsSize = 4;
3149 // Return next O32 integer argument register.
3150 static unsigned getNextIntArgReg(unsigned Reg) {
3151 assert((Reg == Mips::A0) || (Reg == Mips::A2));
3152 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
3155 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3156 /// for tail call optimization.
3157 bool MipsTargetLowering::
3158 IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
3159 unsigned NextStackOffset,
3160 const MipsFunctionInfo& FI) const {
3161 if (!EnableMipsTailCalls)
3164 // No tail call optimization for mips16.
3165 if (Subtarget->inMips16Mode())
3168 // Return false if either the callee or caller has a byval argument.
3169 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
3172 // Return true if the callee's argument area is no larger than the
3174 return NextStackOffset <= FI.getIncomingArgSize();
3178 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3179 SDValue Chain, SDValue Arg, DebugLoc DL,
3180 bool IsTailCall, SelectionDAG &DAG) const {
3182 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
3183 DAG.getIntPtrConstant(Offset));
3184 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
3188 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3189 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3190 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3191 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
3192 /*isVolatile=*/ true, false, 0);
3196 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
3197 // cleaner way to do all of this but it will have to wait until the traditional
3198 // gcc mechanism is completed.
3200 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
3201 // have either arguments or returned values placed in floating point registers,
3202 // we use a set of helper functions. (This includes functions which return type
3203 // complex which on Mips are returned in a pair of floating point registers).
3205 // This is an encoding that we inherited from gcc.
3206 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
3207 // floating point argument registers 1,2 only when the first and optionally
3208 // the second arguments are float (sf) or double (df).
3209 // For Mips16 we are only concerned with the situations where floating point
3210 // arguments are being passed in floating point registers by the ABI, because
3211 // Mips16 mode code cannot execute floating point instructions to load those
3212 // values and hence helper functions are needed.
3213 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
3214 // the helper function suffixs for these are:
3215 // 0, 1, 5, 9, 2, 6, 10
3216 // this suffix can then be calculated as follows:
3217 // for a given argument Arg:
3218 // Arg1x, Arg2x = 1 : Arg is sf
3220 // 0: Arg is neither sf or df
3221 // So this stub is the string for number Arg1x + Arg2x*4.
3222 // However not all numbers between 0 and 10 are possible, we check anyway and
3223 // assert if the impossible exists.
3226 unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber
3227 (ArgListTy &Args) const {
3228 unsigned int resultNum = 0;
3229 if (Args.size() >= 1) {
3230 Type *t = Args[0].Ty;
3231 if (t->isFloatTy()) {
3234 else if (t->isDoubleTy()) {
3239 if (Args.size() >=2) {
3240 Type *t = Args[1].Ty;
3241 if (t->isFloatTy()) {
3244 else if (t->isDoubleTy()) {
3253 // prefixs are attached to stub numbers depending on the return type .
3254 // return type: float sf_
3256 // single complex sc_
3257 // double complext dc_
3261 // The full name of a helper function is__mips16_call_stub +
3262 // return type dependent prefix + stub number
3265 // This is something that probably should be in a different source file and
3266 // perhaps done differently but my main purpose is to not waste runtime
3267 // on something that we can enumerate in the source. Another possibility is
3268 // to have a python script to generate these mapping tables. This will do
3269 // for now. There are a whole series of helper function mapping arrays, one
3270 // for each return type class as outlined above. There there are 11 possible
3271 // entries. Ones with 0 are ones which should never be selected
3273 // All the arrays are similar except for ones which return neither
3274 // sf, df, sc, dc, in which only care about ones which have sf or df as a
3277 #define P_ "__mips16_call_stub_"
3278 #define MAX_STUB_NUMBER 10
3279 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
3280 #define T P "0" , T1
3282 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
3286 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
3290 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
3294 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
3298 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
3304 const char* MipsTargetLowering::
3305 getMips16HelperFunction
3306 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
3307 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
3309 const unsigned int maxStubNum = 10;
3310 assert(stubNum <= maxStubNum);
3311 const bool validStubNum[maxStubNum+1] =
3312 {true, true, true, false, false, true, true, false, false, true, true};
3313 assert(validStubNum[stubNum]);
3316 if (RetTy->isFloatTy()) {
3317 result = sfMips16Helper[stubNum];
3319 else if (RetTy ->isDoubleTy()) {
3320 result = dfMips16Helper[stubNum];
3322 else if (RetTy->isStructTy()) {
3323 // check if it's complex
3324 if (RetTy->getNumContainedTypes() == 2) {
3325 if ((RetTy->getContainedType(0)->isFloatTy()) &&
3326 (RetTy->getContainedType(1)->isFloatTy())) {
3327 result = scMips16Helper[stubNum];
3329 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
3330 (RetTy->getContainedType(1)->isDoubleTy())) {
3331 result = dcMips16Helper[stubNum];
3334 llvm_unreachable("Uncovered condition");
3338 llvm_unreachable("Uncovered condition");
3346 result = vMips16Helper[stubNum];
3352 /// LowerCall - functions arguments are copied from virtual regs to
3353 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3355 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3356 SmallVectorImpl<SDValue> &InVals) const {
3357 SelectionDAG &DAG = CLI.DAG;
3358 DebugLoc &dl = CLI.DL;
3359 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3360 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3361 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3362 SDValue Chain = CLI.Chain;
3363 SDValue Callee = CLI.Callee;
3364 bool &isTailCall = CLI.IsTailCall;
3365 CallingConv::ID CallConv = CLI.CallConv;
3366 bool isVarArg = CLI.IsVarArg;
3368 const char* mips16HelperFunction = 0;
3369 bool needMips16Helper = false;
3371 if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat &&
3374 // currently we don't have symbols tagged with the mips16 or mips32
3375 // qualifier so we will assume that we don't know what kind it is.
3376 // and generate the helper
3378 bool lookupHelper = true;
3379 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3380 if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {
3381 lookupHelper = false;
3384 if (lookupHelper) mips16HelperFunction =
3385 getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper);
3388 MachineFunction &MF = DAG.getMachineFunction();
3389 MachineFrameInfo *MFI = MF.getFrameInfo();
3390 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
3391 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
3393 // Analyze operands of the call, assigning locations to each operand.
3394 SmallVector<CCValAssign, 16> ArgLocs;
3395 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3396 getTargetMachine(), ArgLocs, *DAG.getContext());
3397 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3399 MipsCCInfo.analyzeCallOperands(Outs, isVarArg,
3400 getTargetMachine().Options.UseSoftFloat,
3401 Callee.getNode(), CLI.Args);
3403 // Get a count of how many bytes are to be pushed on the stack.
3404 unsigned NextStackOffset = CCInfo.getNextStackOffset();
3406 // Check if it's really possible to do a tail call.
3409 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
3410 *MF.getInfo<MipsFunctionInfo>());
3415 // Chain is the output chain of the last Load/Store or CopyToReg node.
3416 // ByValChain is the output chain of the last Memcpy node created for copying
3417 // byval arguments to the stack.
3418 unsigned StackAlignment = TFL->getStackAlignment();
3419 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
3420 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
3423 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
3425 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
3426 IsN64 ? Mips::SP_64 : Mips::SP,
3429 // With EABI is it possible to have 16 args on registers.
3430 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
3431 SmallVector<SDValue, 8> MemOpChains;
3432 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3434 // Walk the register/memloc assignments, inserting copies/loads.
3435 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3436 SDValue Arg = OutVals[i];
3437 CCValAssign &VA = ArgLocs[i];
3438 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3439 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3442 if (Flags.isByVal()) {
3443 assert(Flags.getByValSize() &&
3444 "ByVal args of size 0 should have been ignored by front-end.");
3445 assert(ByValArg != MipsCCInfo.byval_end());
3446 assert(!isTailCall &&
3447 "Do not tail-call optimize if there is a byval argument.");
3448 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3449 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
3454 // Promote the value if needed.
3455 switch (VA.getLocInfo()) {
3456 default: llvm_unreachable("Unknown loc info!");
3457 case CCValAssign::Full:
3458 if (VA.isRegLoc()) {
3459 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3460 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3461 (ValVT == MVT::i64 && LocVT == MVT::f64))
3462 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
3463 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3464 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3465 Arg, DAG.getConstant(0, MVT::i32));
3466 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3467 Arg, DAG.getConstant(1, MVT::i32));
3468 if (!Subtarget->isLittle())
3470 unsigned LocRegLo = VA.getLocReg();
3471 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3472 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3473 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3478 case CCValAssign::SExt:
3479 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
3481 case CCValAssign::ZExt:
3482 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
3484 case CCValAssign::AExt:
3485 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
3489 // Arguments that can be passed on register must be kept at
3490 // RegsToPass vector
3491 if (VA.isRegLoc()) {
3492 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3496 // Register can't get to this point...
3497 assert(VA.isMemLoc());
3499 // emit ISD::STORE whichs stores the
3500 // parameter value to a stack Location
3501 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3502 Chain, Arg, dl, isTailCall, DAG));
3505 // Transform all store nodes into one single node because all store
3506 // nodes are independent of each other.
3507 if (!MemOpChains.empty())
3508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3509 &MemOpChains[0], MemOpChains.size());
3511 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3512 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3513 // node so that legalize doesn't hack it.
3514 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
3515 bool GlobalOrExternal = false, InternalLinkage = false;
3518 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3520 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3522 if (InternalLinkage)
3523 Callee = getAddrLocal(Callee, DAG, HasMips64);
3525 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3526 MipsII::MO_CALL_LO16);
3528 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3530 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3531 MipsII::MO_NO_FLAG);
3532 GlobalOrExternal = true;
3534 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3535 if (!IsN64 && !IsPIC) // !N64 && static
3536 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3537 MipsII::MO_NO_FLAG);
3539 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3540 MipsII::MO_CALL_LO16);
3542 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3544 GlobalOrExternal = true;
3547 SDValue JumpTarget = Callee;
3549 // T9 should contain the address of the callee function if
3550 // -reloction-model=pic or it is an indirect call.
3551 if (IsPICCall || !GlobalOrExternal) {
3552 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3553 unsigned V0Reg = Mips::V0;
3554 if (needMips16Helper) {
3555 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
3556 JumpTarget = DAG.getExternalSymbol(
3557 mips16HelperFunction, getPointerTy());
3558 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
3561 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
3563 if (!Subtarget->inMips16Mode())
3564 JumpTarget = SDValue();
3568 // Insert node "GP copy globalreg" before call to function.
3570 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3571 // in PIC mode) allow symbols to be resolved via lazy binding.
3572 // The lazy binding stub requires GP to point to the GOT.
3573 if (IsPICCall && !InternalLinkage) {
3574 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3575 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3576 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3579 // Build a sequence of copy-to-reg nodes chained together with token
3580 // chain and flag operands which copy the outgoing args into registers.
3581 // The InFlag in necessary since all emitted instructions must be
3585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3586 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3587 RegsToPass[i].second, InFlag);
3588 InFlag = Chain.getValue(1);
3591 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
3592 // = Chain, Callee, Reg#1, Reg#2, ...
3594 // Returns a chain & a flag for retval copy to use.
3595 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3596 SmallVector<SDValue, 8> Ops(1, Chain);
3598 if (JumpTarget.getNode())
3599 Ops.push_back(JumpTarget);
3601 // Add argument registers to the end of the list so that they are
3602 // known live into the call.
3603 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3604 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3605 RegsToPass[i].second.getValueType()));
3607 // Add a register mask operand representing the call-preserved registers.
3608 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3609 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3610 assert(Mask && "Missing call preserved mask for calling convention");
3611 Ops.push_back(DAG.getRegisterMask(Mask));
3613 if (InFlag.getNode())
3614 Ops.push_back(InFlag);
3617 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
3619 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
3620 InFlag = Chain.getValue(1);
3622 // Create the CALLSEQ_END node.
3623 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3624 DAG.getIntPtrConstant(0, true), InFlag);
3625 InFlag = Chain.getValue(1);
3627 // Handle result values, copying them out of physregs into vregs that we
3629 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3630 Ins, dl, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
3633 /// LowerCallResult - Lower the result values of a call into the
3634 /// appropriate copies out of appropriate physical registers.
3636 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3637 CallingConv::ID CallConv, bool isVarArg,
3638 const SmallVectorImpl<ISD::InputArg> &Ins,
3639 DebugLoc dl, SelectionDAG &DAG,
3640 SmallVectorImpl<SDValue> &InVals,
3641 const SDNode *CallNode,
3642 const Type *RetTy) const {
3643 // Assign locations to each value returned by this call.
3644 SmallVector<CCValAssign, 16> RVLocs;
3645 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3646 getTargetMachine(), RVLocs, *DAG.getContext());
3647 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3649 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat,
3652 // Copy all of the result registers out of their specified physreg.
3653 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3654 SDValue Val = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3655 RVLocs[i].getLocVT(), InFlag);
3656 Chain = Val.getValue(1);
3657 InFlag = Val.getValue(2);
3659 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
3660 Val = DAG.getNode(ISD::BITCAST, dl, RVLocs[i].getValVT(), Val);
3662 InVals.push_back(Val);
3668 //===----------------------------------------------------------------------===//
3669 // Formal Arguments Calling Convention Implementation
3670 //===----------------------------------------------------------------------===//
3671 /// LowerFormalArguments - transform physical registers into virtual registers
3672 /// and generate load operations for arguments places on the stack.
3674 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3675 CallingConv::ID CallConv,
3677 const SmallVectorImpl<ISD::InputArg> &Ins,
3678 DebugLoc dl, SelectionDAG &DAG,
3679 SmallVectorImpl<SDValue> &InVals)
3681 MachineFunction &MF = DAG.getMachineFunction();
3682 MachineFrameInfo *MFI = MF.getFrameInfo();
3683 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3685 MipsFI->setVarArgsFrameIndex(0);
3687 // Used with vargs to acumulate store chains.
3688 std::vector<SDValue> OutChains;
3690 // Assign locations to all of the incoming arguments.
3691 SmallVector<CCValAssign, 16> ArgLocs;
3692 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3693 getTargetMachine(), ArgLocs, *DAG.getContext());
3694 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3695 Function::const_arg_iterator FuncArg =
3696 DAG.getMachineFunction().getFunction()->arg_begin();
3697 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat;
3699 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
3700 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3701 MipsCCInfo.hasByValArg());
3703 unsigned CurArgIdx = 0;
3704 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3707 CCValAssign &VA = ArgLocs[i];
3708 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3709 CurArgIdx = Ins[i].OrigArgIndex;
3710 EVT ValVT = VA.getValVT();
3711 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3712 bool IsRegLoc = VA.isRegLoc();
3714 if (Flags.isByVal()) {
3715 assert(Flags.getByValSize() &&
3716 "ByVal args of size 0 should have been ignored by front-end.");
3717 assert(ByValArg != MipsCCInfo.byval_end());
3718 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3719 MipsCCInfo, *ByValArg);
3724 // Arguments stored on registers
3726 EVT RegVT = VA.getLocVT();
3727 unsigned ArgReg = VA.getLocReg();
3728 const TargetRegisterClass *RC;
3730 if (RegVT == MVT::i32)
3731 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
3732 &Mips::CPURegsRegClass;
3733 else if (RegVT == MVT::i64)
3734 RC = &Mips::CPU64RegsRegClass;
3735 else if (RegVT == MVT::f32)
3736 RC = &Mips::FGR32RegClass;
3737 else if (RegVT == MVT::f64)
3738 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3740 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3742 // Transform the arguments stored on
3743 // physical registers into virtual ones
3744 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3745 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3747 // If this is an 8 or 16-bit value, it has been passed promoted
3748 // to 32 bits. Insert an assert[sz]ext to capture this, then
3749 // truncate to the right size.
3750 if (VA.getLocInfo() != CCValAssign::Full) {
3751 unsigned Opcode = 0;
3752 if (VA.getLocInfo() == CCValAssign::SExt)
3753 Opcode = ISD::AssertSext;
3754 else if (VA.getLocInfo() == CCValAssign::ZExt)
3755 Opcode = ISD::AssertZext;
3757 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3758 DAG.getValueType(ValVT));
3759 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3762 // Handle floating point arguments passed in integer registers and
3763 // long double arguments passed in floating point registers.
3764 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3765 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3766 (RegVT == MVT::f64 && ValVT == MVT::i64))
3767 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3768 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3769 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3770 getNextIntArgReg(ArgReg), RC);
3771 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3772 if (!Subtarget->isLittle())
3773 std::swap(ArgValue, ArgValue2);
3774 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3775 ArgValue, ArgValue2);
3778 InVals.push_back(ArgValue);
3779 } else { // VA.isRegLoc()
3782 assert(VA.isMemLoc());
3784 // The stack pointer offset is relative to the caller stack frame.
3785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3786 VA.getLocMemOffset(), true);
3788 // Create load nodes to retrieve arguments from the stack
3789 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3790 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3791 MachinePointerInfo::getFixedStack(FI),
3792 false, false, false, 0));
3796 // The mips ABIs for returning structs by value requires that we copy
3797 // the sret argument into $v0 for the return. Save the argument into
3798 // a virtual register so that we can access it from the return points.
3799 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3800 unsigned Reg = MipsFI->getSRetReturnReg();
3802 Reg = MF.getRegInfo().
3803 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3804 MipsFI->setSRetReturnReg(Reg);
3806 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3807 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3811 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3813 // All stores are grouped in one node to allow the matching between
3814 // the size of Ins and InVals. This only happens when on varg functions
3815 if (!OutChains.empty()) {
3816 OutChains.push_back(Chain);
3817 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3818 &OutChains[0], OutChains.size());
3824 //===----------------------------------------------------------------------===//
3825 // Return Value Calling Convention Implementation
3826 //===----------------------------------------------------------------------===//
3829 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3830 MachineFunction &MF, bool isVarArg,
3831 const SmallVectorImpl<ISD::OutputArg> &Outs,
3832 LLVMContext &Context) const {
3833 SmallVector<CCValAssign, 16> RVLocs;
3834 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3836 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3840 MipsTargetLowering::LowerReturn(SDValue Chain,
3841 CallingConv::ID CallConv, bool isVarArg,
3842 const SmallVectorImpl<ISD::OutputArg> &Outs,
3843 const SmallVectorImpl<SDValue> &OutVals,
3844 DebugLoc dl, SelectionDAG &DAG) const {
3845 // CCValAssign - represent the assignment of
3846 // the return value to a location
3847 SmallVector<CCValAssign, 16> RVLocs;
3848 MachineFunction &MF = DAG.getMachineFunction();
3850 // CCState - Info about the registers and stack slot.
3851 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs,
3853 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3855 // Analize return values.
3856 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat,
3857 MF.getFunction()->getReturnType());
3860 SmallVector<SDValue, 4> RetOps(1, Chain);
3862 // Copy the result values into the output registers.
3863 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3864 SDValue Val = OutVals[i];
3865 CCValAssign &VA = RVLocs[i];
3866 assert(VA.isRegLoc() && "Can only return in registers!");
3868 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
3869 Val = DAG.getNode(ISD::BITCAST, dl, RVLocs[i].getLocVT(), Val);
3871 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag);
3873 // Guarantee that all emitted copies are stuck together with flags.
3874 Flag = Chain.getValue(1);
3875 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3878 // The mips ABIs for returning structs by value requires that we copy
3879 // the sret argument into $v0 for the return. We saved the argument into
3880 // a virtual register in the entry block, so now we copy the value out
3882 if (MF.getFunction()->hasStructRetAttr()) {
3883 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3884 unsigned Reg = MipsFI->getSRetReturnReg();
3887 llvm_unreachable("sret virtual register not created in the entry block");
3888 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3889 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3891 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3892 Flag = Chain.getValue(1);
3893 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3896 RetOps[0] = Chain; // Update chain.
3898 // Add the flag if we have it.
3900 RetOps.push_back(Flag);
3902 // Return on Mips is always a "jr $ra"
3903 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, &RetOps[0], RetOps.size());
3906 //===----------------------------------------------------------------------===//
3907 // Mips Inline Assembly Support
3908 //===----------------------------------------------------------------------===//
3910 /// getConstraintType - Given a constraint letter, return the type of
3911 /// constraint it is for this target.
3912 MipsTargetLowering::ConstraintType MipsTargetLowering::
3913 getConstraintType(const std::string &Constraint) const
3915 // Mips specific constrainy
3916 // GCC config/mips/constraints.md
3918 // 'd' : An address register. Equivalent to r
3919 // unless generating MIPS16 code.
3920 // 'y' : Equivalent to r; retained for
3921 // backwards compatibility.
3922 // 'c' : A register suitable for use in an indirect
3923 // jump. This will always be $25 for -mabicalls.
3924 // 'l' : The lo register. 1 word storage.
3925 // 'x' : The hilo register pair. Double word storage.
3926 if (Constraint.size() == 1) {
3927 switch (Constraint[0]) {
3935 return C_RegisterClass;
3940 return TargetLowering::getConstraintType(Constraint);
3943 /// Examine constraint type and operand type and determine a weight value.
3944 /// This object must already have been set up with the operand type
3945 /// and the current alternative constraint selected.
3946 TargetLowering::ConstraintWeight
3947 MipsTargetLowering::getSingleConstraintMatchWeight(
3948 AsmOperandInfo &info, const char *constraint) const {
3949 ConstraintWeight weight = CW_Invalid;
3950 Value *CallOperandVal = info.CallOperandVal;
3951 // If we don't have a value, we can't do a match,
3952 // but allow it at the lowest weight.
3953 if (CallOperandVal == NULL)
3955 Type *type = CallOperandVal->getType();
3956 // Look at the constraint type.
3957 switch (*constraint) {
3959 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3963 if (type->isIntegerTy())
3964 weight = CW_Register;
3967 if (type->isFloatTy())
3968 weight = CW_Register;
3970 case 'c': // $25 for indirect jumps
3971 case 'l': // lo register
3972 case 'x': // hilo register pair
3973 if (type->isIntegerTy())
3974 weight = CW_SpecificReg;
3976 case 'I': // signed 16 bit immediate
3977 case 'J': // integer zero
3978 case 'K': // unsigned 16 bit immediate
3979 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3980 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3981 case 'O': // signed 15 bit immediate (+- 16383)
3982 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3983 if (isa<ConstantInt>(CallOperandVal))
3984 weight = CW_Constant;
3993 /// Given a register class constraint, like 'r', if this corresponds directly
3994 /// to an LLVM register class, return a register of 0 and the register class
3996 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3997 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3999 if (Constraint.size() == 1) {
4000 switch (Constraint[0]) {
4001 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
4002 case 'y': // Same as 'r'. Exists for compatibility.
4004 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
4005 if (Subtarget->inMips16Mode())
4006 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4007 return std::make_pair(0U, &Mips::CPURegsRegClass);
4009 if (VT == MVT::i64 && !HasMips64)
4010 return std::make_pair(0U, &Mips::CPURegsRegClass);
4011 if (VT == MVT::i64 && HasMips64)
4012 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
4013 // This will generate an error message
4014 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
4017 return std::make_pair(0U, &Mips::FGR32RegClass);
4018 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
4019 if (Subtarget->isFP64bit())
4020 return std::make_pair(0U, &Mips::FGR64RegClass);
4021 return std::make_pair(0U, &Mips::AFGR64RegClass);
4024 case 'c': // register suitable for indirect jump
4026 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
4027 assert(VT == MVT::i64 && "Unexpected type.");
4028 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
4029 case 'l': // register suitable for indirect jump
4031 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
4032 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
4033 case 'x': // register suitable for indirect jump
4034 // Fixme: Not triggering the use of both hi and low
4035 // This will generate an error message
4036 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
4039 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4042 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4043 /// vector. If it is invalid, don't add anything to Ops.
4044 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4045 std::string &Constraint,
4046 std::vector<SDValue>&Ops,
4047 SelectionDAG &DAG) const {
4048 SDValue Result(0, 0);
4050 // Only support length 1 constraints for now.
4051 if (Constraint.length() > 1) return;
4053 char ConstraintLetter = Constraint[0];
4054 switch (ConstraintLetter) {
4055 default: break; // This will fall through to the generic implementation
4056 case 'I': // Signed 16 bit constant
4057 // If this fails, the parent routine will give an error
4058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4059 EVT Type = Op.getValueType();
4060 int64_t Val = C->getSExtValue();
4061 if (isInt<16>(Val)) {
4062 Result = DAG.getTargetConstant(Val, Type);
4067 case 'J': // integer zero
4068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4069 EVT Type = Op.getValueType();
4070 int64_t Val = C->getZExtValue();
4072 Result = DAG.getTargetConstant(0, Type);
4077 case 'K': // unsigned 16 bit immediate
4078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4079 EVT Type = Op.getValueType();
4080 uint64_t Val = (uint64_t)C->getZExtValue();
4081 if (isUInt<16>(Val)) {
4082 Result = DAG.getTargetConstant(Val, Type);
4087 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4088 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4089 EVT Type = Op.getValueType();
4090 int64_t Val = C->getSExtValue();
4091 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4092 Result = DAG.getTargetConstant(Val, Type);
4097 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4099 EVT Type = Op.getValueType();
4100 int64_t Val = C->getSExtValue();
4101 if ((Val >= -65535) && (Val <= -1)) {
4102 Result = DAG.getTargetConstant(Val, Type);
4107 case 'O': // signed 15 bit immediate
4108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4109 EVT Type = Op.getValueType();
4110 int64_t Val = C->getSExtValue();
4111 if ((isInt<15>(Val))) {
4112 Result = DAG.getTargetConstant(Val, Type);
4117 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4119 EVT Type = Op.getValueType();
4120 int64_t Val = C->getSExtValue();
4121 if ((Val <= 65535) && (Val >= 1)) {
4122 Result = DAG.getTargetConstant(Val, Type);
4129 if (Result.getNode()) {
4130 Ops.push_back(Result);
4134 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4138 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
4139 // No global is ever allowed as a base.
4144 case 0: // "r+i" or just "i", depending on HasBaseReg.
4147 if (!AM.HasBaseReg) // allow "r+i".
4149 return false; // disallow "r+r" or "r+r+i".
4158 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4159 // The Mips target isn't yet aware of offsets.
4163 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4165 bool IsMemset, bool ZeroMemset,
4167 MachineFunction &MF) const {
4168 if (Subtarget->hasMips64())
4174 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4175 if (VT != MVT::f32 && VT != MVT::f64)
4177 if (Imm.isNegZero())
4179 return Imm.isZero();
4182 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4184 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4186 return TargetLowering::getJumpTableEncoding();
4189 /// This function returns true if CallSym is a long double emulation routine.
4190 static bool isF128SoftLibCall(const char *CallSym) {
4191 const char *const LibCalls[] =
4192 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
4193 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
4194 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
4195 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
4196 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
4197 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
4198 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
4199 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
4202 const char * const *End = LibCalls + array_lengthof(LibCalls);
4204 // Check that LibCalls is sorted alphabetically.
4208 for (const char * const *I = LibCalls; I < End - 1; ++I)
4209 assert(Comp(*I, *(I + 1)));
4212 return std::binary_search(LibCalls, End, CallSym, ltstr());
4215 /// This function returns true if Ty is fp128 or i128 which was originally a
4217 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
4218 if (Ty->isFP128Ty())
4221 const ExternalSymbolSDNode *ES =
4222 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
4224 // If the Ty is i128 and the function being called is a long double emulation
4225 // routine, then the original type is f128.
4226 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
4229 MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, bool IsO32_,
4231 : CCInfo(Info), CallConv(CC), IsO32(IsO32_) {
4232 // Pre-allocate reserved argument area.
4233 CCInfo.AllocateStack(reservedArgArea(), 1);
4236 void MipsTargetLowering::MipsCC::
4237 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
4238 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
4239 std::vector<ArgListEntry> &FuncArgs) {
4240 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
4241 "CallingConv::Fast shouldn't be used for vararg functions.");
4243 unsigned NumOpnds = Args.size();
4244 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
4246 for (unsigned I = 0; I != NumOpnds; ++I) {
4247 MVT ArgVT = Args[I].VT;
4248 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4251 if (ArgFlags.isByVal()) {
4252 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4256 if (IsVarArg && !Args[I].IsFixed)
4257 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4259 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
4261 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
4266 dbgs() << "Call operand #" << I << " has unhandled type "
4267 << EVT(ArgVT).getEVTString();
4269 llvm_unreachable(0);
4274 void MipsTargetLowering::MipsCC::
4275 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
4276 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
4277 unsigned NumArgs = Args.size();
4278 llvm::CCAssignFn *FixedFn = fixedArgFn();
4279 unsigned CurArgIdx = 0;
4281 for (unsigned I = 0; I != NumArgs; ++I) {
4282 MVT ArgVT = Args[I].VT;
4283 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4284 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
4285 CurArgIdx = Args[I].OrigArgIndex;
4287 if (ArgFlags.isByVal()) {
4288 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4292 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
4294 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
4298 dbgs() << "Formal Arg #" << I << " has unhandled type "
4299 << EVT(ArgVT).getEVTString();
4301 llvm_unreachable(0);
4305 template<typename Ty>
4306 void MipsTargetLowering::MipsCC::
4307 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
4308 const SDNode *CallNode, const Type *RetTy) const {
4311 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
4312 Fn = RetCC_F128Soft;
4316 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
4317 MVT VT = RetVals[I].VT;
4318 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
4319 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
4321 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
4323 dbgs() << "Call result #" << I << " has unhandled type "
4324 << EVT(VT).getEVTString() << '\n';
4326 llvm_unreachable(0);
4331 void MipsTargetLowering::MipsCC::
4332 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
4333 const SDNode *CallNode, const Type *RetTy) const {
4334 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
4337 void MipsTargetLowering::MipsCC::
4338 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
4339 const Type *RetTy) const {
4340 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
4344 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
4346 CCValAssign::LocInfo LocInfo,
4347 ISD::ArgFlagsTy ArgFlags) {
4348 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
4350 struct ByValArgInfo ByVal;
4351 unsigned RegSize = regSize();
4352 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
4353 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
4356 if (useRegsForByval())
4357 allocateRegs(ByVal, ByValSize, Align);
4359 // Allocate space on caller's stack.
4360 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
4362 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
4364 ByValArgs.push_back(ByVal);
4367 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
4368 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
4371 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
4372 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
4375 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
4376 return IsO32 ? O32IntRegs : Mips64IntRegs;
4379 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
4380 if (CallConv == CallingConv::Fast)
4381 return CC_Mips_FastCC;
4383 return IsO32 ? CC_MipsO32 : CC_MipsN;
4386 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
4387 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
4390 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
4391 return IsO32 ? O32IntRegs : Mips64DPRegs;
4394 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
4397 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
4398 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
4399 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
4400 "Byval argument's size and alignment should be a multiple of"
4403 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
4405 // If Align > RegSize, the first arg register must be even.
4406 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
4407 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
4411 // Mark the registers allocated.
4412 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
4413 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
4414 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4417 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
4418 const SDNode *CallNode,
4419 bool IsSoftFloat) const {
4420 if (IsSoftFloat || IsO32)
4423 // Check if the original type was fp128.
4424 if (originalTypeIsF128(OrigTy, CallNode)) {
4425 assert(VT == MVT::i64);
4432 void MipsTargetLowering::
4433 copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
4434 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4435 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4436 const MipsCC &CC, const ByValArgInfo &ByVal) const {
4437 MachineFunction &MF = DAG.getMachineFunction();
4438 MachineFrameInfo *MFI = MF.getFrameInfo();
4439 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
4440 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4444 FrameObjOffset = (int)CC.reservedArgArea() -
4445 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
4447 FrameObjOffset = ByVal.Address;
4449 // Create frame object.
4450 EVT PtrTy = getPointerTy();
4451 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4452 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4453 InVals.push_back(FIN);
4458 // Copy arg registers.
4459 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
4460 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4462 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
4463 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
4464 unsigned VReg = AddLiveIn(MF, ArgReg, RC);
4465 unsigned Offset = I * CC.regSize();
4466 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4467 DAG.getConstant(Offset, PtrTy));
4468 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4469 StorePtr, MachinePointerInfo(FuncArg, Offset),
4471 OutChains.push_back(Store);
4475 // Copy byVal arg to registers and stack.
4476 void MipsTargetLowering::
4477 passByValArg(SDValue Chain, DebugLoc DL,
4478 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
4479 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
4480 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
4481 const MipsCC &CC, const ByValArgInfo &ByVal,
4482 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
4483 unsigned ByValSize = Flags.getByValSize();
4484 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
4485 unsigned RegSize = CC.regSize();
4486 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
4487 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
4489 if (ByVal.NumRegs) {
4490 const uint16_t *ArgRegs = CC.intArgRegs();
4491 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
4494 // Copy words to registers.
4495 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
4496 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4497 DAG.getConstant(Offset, PtrTy));
4498 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4499 MachinePointerInfo(), false, false, false,
4501 MemOpChains.push_back(LoadVal.getValue(1));
4502 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4503 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4506 // Return if the struct has been fully copied.
4507 if (ByValSize == Offset)
4510 // Copy the remainder of the byval argument with sub-word loads and shifts.
4511 if (LeftoverBytes) {
4512 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
4513 "Size of the remainder should be smaller than RegSize.");
4516 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
4517 Offset < ByValSize; LoadSize /= 2) {
4518 unsigned RemSize = ByValSize - Offset;
4520 if (RemSize < LoadSize)
4524 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4525 DAG.getConstant(Offset, PtrTy));
4527 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
4528 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
4529 false, false, Alignment);
4530 MemOpChains.push_back(LoadVal.getValue(1));
4532 // Shift the loaded value.
4536 Shamt = TotalSizeLoaded;
4538 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
4540 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4541 DAG.getConstant(Shamt, MVT::i32));
4544 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4549 TotalSizeLoaded += LoadSize;
4550 Alignment = std::min(Alignment, LoadSize);
4553 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4554 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4559 // Copy remainder of byval arg to it with memcpy.
4560 unsigned MemCpySize = ByValSize - Offset;
4561 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4562 DAG.getConstant(Offset, PtrTy));
4563 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4564 DAG.getIntPtrConstant(ByVal.Address));
4565 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4566 DAG.getConstant(MemCpySize, PtrTy), Alignment,
4567 /*isVolatile=*/false, /*AlwaysInline=*/false,
4568 MachinePointerInfo(0), MachinePointerInfo(0));
4569 MemOpChains.push_back(Chain);
4573 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4574 const MipsCC &CC, SDValue Chain,
4575 DebugLoc DL, SelectionDAG &DAG) const {
4576 unsigned NumRegs = CC.numIntArgRegs();
4577 const uint16_t *ArgRegs = CC.intArgRegs();
4578 const CCState &CCInfo = CC.getCCInfo();
4579 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
4580 unsigned RegSize = CC.regSize();
4581 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
4582 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4583 MachineFunction &MF = DAG.getMachineFunction();
4584 MachineFrameInfo *MFI = MF.getFrameInfo();
4585 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4587 // Offset of the first variable argument from stack pointer.
4591 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
4594 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
4596 // Record the frame index of the first variable argument
4597 // which is a value necessary to VASTART.
4598 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4599 MipsFI->setVarArgsFrameIndex(FI);
4601 // Copy the integer registers that have not been used for argument passing
4602 // to the argument register save area. For O32, the save area is allocated
4603 // in the caller's stack frame, while for N32/64, it is allocated in the
4604 // callee's stack frame.
4605 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
4606 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
4607 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4608 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4609 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
4610 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
4611 MachinePointerInfo(), false, false, 0);
4612 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
4613 OutChains.push_back(Store);