1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::GPRel : return "MipsISD::GPRel";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::CMov : return "MipsISD::CMov";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
49 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
50 case MipsISD::FPCmp : return "MipsISD::FPCmp";
51 default : return NULL;
56 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
58 Subtarget = &TM.getSubtarget<MipsSubtarget>();
60 // Mips does not have i1 type, so use i32 for
61 // setcc operations results (slt, sgt, ...).
62 setSetCCResultContents(ZeroOrOneSetCCResult);
64 // JumpTable targets must use GOT when using PIC_
65 setUsesGlobalOffsetTable(true);
67 // Set up the register classes
68 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 // When dealing with single precision only, use libcalls
71 if (!Subtarget->isSingleFloat()) {
72 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
73 if (!Subtarget->isFP64bit())
74 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
76 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
95 setOperationAction(ISD::RET, MVT::Other, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::i32, Custom);
100 setOperationAction(ISD::SETCC, MVT::f32, Custom);
101 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
102 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
104 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
105 // with operands comming from setcc fp comparions. This is necessary since
106 // the result from these setcc are in a flag registers (FCR31).
107 setOperationAction(ISD::AND, MVT::i32, Custom);
108 setOperationAction(ISD::OR, MVT::i32, Custom);
110 // Operations not directly supported by Mips.
111 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
112 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
115 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
117 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
118 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
119 setOperationAction(ISD::ROTL, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
121 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
125 // We don't have line number support yet.
126 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
127 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
128 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
129 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
131 // Use the default for now
132 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
133 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
134 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
136 if (Subtarget->isSingleFloat())
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
139 if (!Subtarget->hasSEInReg()) {
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
144 if (!Subtarget->hasBitCount())
145 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
147 if (!Subtarget->hasSwap())
148 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
150 setStackPointerRegisterToSaveRestore(Mips::SP);
151 computeRegisterProperties();
155 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
160 SDValue MipsTargetLowering::
161 LowerOperation(SDValue Op, SelectionDAG &DAG)
163 switch (Op.getOpcode())
165 case ISD::AND: return LowerANDOR(Op, DAG);
166 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
167 case ISD::CALL: return LowerCALL(Op, DAG);
168 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
169 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
170 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
171 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
172 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
173 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
174 case ISD::OR: return LowerANDOR(Op, DAG);
175 case ISD::RET: return LowerRET(Op, DAG);
176 case ISD::SELECT: return LowerSELECT(Op, DAG);
177 case ISD::SETCC: return LowerSETCC(Op, DAG);
182 //===----------------------------------------------------------------------===//
183 // Lower helper functions
184 //===----------------------------------------------------------------------===//
186 // AddLiveIn - This helper function adds the specified physical register to the
187 // MachineFunction as a live in value. It also creates a corresponding
188 // virtual register for it.
190 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
192 assert(RC->contains(PReg) && "Not the correct regclass!");
193 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
194 MF.getRegInfo().addLiveIn(PReg, VReg);
198 // A address must be loaded from a small section if its size is less than the
199 // small section size threshold. Data in this section must be addressed using
201 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
202 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
205 // Discover if this global address can be placed into small data/bss section.
206 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
208 const TargetData *TD = getTargetData();
209 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
214 const Type *Ty = GV->getType()->getElementType();
215 unsigned Size = TD->getABITypeSize(Ty);
217 // if this is a internal constant string, there is a special
218 // section for it, but not in small data/bss.
219 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
220 Constant *C = GVA->getInitializer();
221 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
222 if (CVA && CVA->isCString())
226 return IsInSmallSection(Size);
229 // Get fp branch code (not opcode) from condition code.
230 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
231 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
232 return Mips::BRANCH_T;
234 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
235 return Mips::BRANCH_F;
237 return Mips::BRANCH_INVALID;
240 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
243 assert(0 && "Unknown branch code");
244 case Mips::BRANCH_T : return Mips::BC1T;
245 case Mips::BRANCH_F : return Mips::BC1F;
246 case Mips::BRANCH_TL : return Mips::BC1TL;
247 case Mips::BRANCH_FL : return Mips::BC1FL;
251 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
253 default: assert(0 && "Unknown fp condition code!");
255 case ISD::SETOEQ: return Mips::FCOND_EQ;
256 case ISD::SETUNE: return Mips::FCOND_OGL;
258 case ISD::SETOLT: return Mips::FCOND_OLT;
260 case ISD::SETOGT: return Mips::FCOND_OGT;
262 case ISD::SETOLE: return Mips::FCOND_OLE;
264 case ISD::SETOGE: return Mips::FCOND_OGE;
265 case ISD::SETULT: return Mips::FCOND_ULT;
266 case ISD::SETULE: return Mips::FCOND_ULE;
267 case ISD::SETUGT: return Mips::FCOND_UGT;
268 case ISD::SETUGE: return Mips::FCOND_UGE;
269 case ISD::SETUO: return Mips::FCOND_UN;
270 case ISD::SETO: return Mips::FCOND_OR;
272 case ISD::SETONE: return Mips::FCOND_NEQ;
273 case ISD::SETUEQ: return Mips::FCOND_UEQ;
278 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
279 MachineBasicBlock *BB)
281 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
282 bool isFPCmp = false;
284 switch (MI->getOpcode()) {
285 default: assert(false && "Unexpected instr type to insert");
286 case Mips::Select_FCC:
287 case Mips::Select_FCC_SO32:
288 case Mips::Select_FCC_AS32:
289 case Mips::Select_FCC_D32:
290 isFPCmp = true; // FALL THROUGH
291 case Mips::Select_CC:
292 case Mips::Select_CC_SO32:
293 case Mips::Select_CC_AS32:
294 case Mips::Select_CC_D32: {
295 // To "insert" a SELECT_CC instruction, we actually have to insert the
296 // diamond control-flow pattern. The incoming instruction knows the
297 // destination vreg to set, the condition code register to branch on, the
298 // true/false values to select between, and a branch opcode to use.
299 const BasicBlock *LLVM_BB = BB->getBasicBlock();
300 MachineFunction::iterator It = BB;
307 // bNE r1, r0, copy1MBB
308 // fallthrough --> copy0MBB
309 MachineBasicBlock *thisMBB = BB;
310 MachineFunction *F = BB->getParent();
311 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
312 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
314 // Emit the right instruction according to the type of the operands compared
316 // Find the condiction code present in the setcc operation.
317 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
318 // Get the branch opcode from the branch code.
319 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
320 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
322 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
323 .addReg(Mips::ZERO).addMBB(sinkMBB);
325 F->insert(It, copy0MBB);
326 F->insert(It, sinkMBB);
327 // Update machine-CFG edges by first adding all successors of the current
328 // block to the new block which will contain the Phi node for the select.
329 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
330 e = BB->succ_end(); i != e; ++i)
331 sinkMBB->addSuccessor(*i);
332 // Next, remove all successors of the current block, and add the true
333 // and fallthrough blocks as its successors.
334 while(!BB->succ_empty())
335 BB->removeSuccessor(BB->succ_begin());
336 BB->addSuccessor(copy0MBB);
337 BB->addSuccessor(sinkMBB);
341 // # fallthrough to sinkMBB
344 // Update machine-CFG edges
345 BB->addSuccessor(sinkMBB);
348 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
351 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
352 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
353 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
355 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
361 //===----------------------------------------------------------------------===//
362 // Misc Lower Operation implementation
363 //===----------------------------------------------------------------------===//
365 SDValue MipsTargetLowering::
366 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
368 SDValue Chain = Op.getOperand(0);
369 SDValue Size = Op.getOperand(1);
371 // Get a reference from Mips stack pointer
372 SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
374 // Subtract the dynamic size from the actual stack size to
375 // obtain the new stack size.
376 SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
378 // The Sub result contains the new stack start address, so it
379 // must be placed in the stack pointer register.
380 Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
382 // This node always has two return values: a new stack pointer
384 SDValue Ops[2] = { Sub, Chain };
385 return DAG.getMergeValues(Ops, 2);
388 SDValue MipsTargetLowering::
389 LowerANDOR(SDValue Op, SelectionDAG &DAG)
391 SDValue LHS = Op.getOperand(0);
392 SDValue RHS = Op.getOperand(1);
394 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
397 SDValue True = DAG.getConstant(1, MVT::i32);
398 SDValue False = DAG.getConstant(0, MVT::i32);
400 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
401 LHS, True, False, LHS.getOperand(2));
402 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
403 RHS, True, False, RHS.getOperand(2));
405 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
408 SDValue MipsTargetLowering::
409 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
411 // The first operand is the chain, the second is the condition, the third is
412 // the block to branch to if the condition is true.
413 SDValue Chain = Op.getOperand(0);
414 SDValue Dest = Op.getOperand(2);
416 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
419 SDValue CondRes = Op.getOperand(1);
420 SDValue CCNode = CondRes.getOperand(2);
422 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
423 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
425 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
429 SDValue MipsTargetLowering::
430 LowerSETCC(SDValue Op, SelectionDAG &DAG)
432 // The operands to this are the left and right operands to compare (ops #0,
433 // and #1) and the condition code to compare them with (op #2) as a
435 SDValue LHS = Op.getOperand(0);
436 SDValue RHS = Op.getOperand(1);
438 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
440 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
441 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
444 SDValue MipsTargetLowering::
445 LowerSELECT(SDValue Op, SelectionDAG &DAG)
447 SDValue Cond = Op.getOperand(0);
448 SDValue True = Op.getOperand(1);
449 SDValue False = Op.getOperand(2);
451 // if the incomming condition comes from a integer compare, the select
452 // operation must be SelectCC or a conditional move if the subtarget
454 if (Cond.getOpcode() != MipsISD::FPCmp) {
455 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
457 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
461 // if the incomming condition comes from fpcmp, the select
462 // operation must use FPSelectCC.
463 SDValue CCNode = Cond.getOperand(2);
464 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
465 Cond, True, False, CCNode);
468 SDValue MipsTargetLowering::
469 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
471 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
472 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
474 if (!Subtarget->hasABICall()) {
475 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
476 SDValue Ops[] = { GA };
477 // %gp_rel relocation
478 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
479 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
480 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
481 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
483 // %hi/%lo relocation
484 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
485 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
486 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
488 } else { // Abicall relocations, TODO: make this cleaner.
489 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
490 // On functions and global targets not internal linked only
491 // a load from got/GP is necessary for PIC to work.
492 if (!GV->hasInternalLinkage() || isa<Function>(GV))
494 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
495 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
498 assert(0 && "Dont know how to handle GlobalAddress");
502 SDValue MipsTargetLowering::
503 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
505 assert(0 && "TLS not implemented for MIPS.");
506 return SDValue(); // Not reached
509 SDValue MipsTargetLowering::
510 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
515 MVT PtrVT = Op.getValueType();
516 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
517 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
519 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
520 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
521 SDValue Ops[] = { JTI };
522 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
523 } else // Emit Load from Global Pointer
524 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
526 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
527 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
532 SDValue MipsTargetLowering::
533 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
536 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
537 Constant *C = N->getConstVal();
538 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
541 // FIXME: we should reference the constant pool using small data sections,
542 // but the asm printer currently doens't support this feature without
543 // hacking it. This feature should come soon so we can uncomment the
545 //if (!Subtarget->hasABICall() &&
546 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
547 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
548 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
549 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
550 //} else { // %hi/%lo relocation
551 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
552 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
553 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
559 //===----------------------------------------------------------------------===//
560 // Calling Convention Implementation
562 // The lower operations present on calling convention works on this order:
563 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
564 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
565 // LowerRET (virt regs --> phys regs)
566 // LowerCALL (phys regs --> virt regs)
568 //===----------------------------------------------------------------------===//
570 #include "MipsGenCallingConv.inc"
572 //===----------------------------------------------------------------------===//
573 // CALL Calling Convention Implementation
574 //===----------------------------------------------------------------------===//
576 /// LowerCCCCallTo - functions arguments are copied from virtual
577 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
578 /// CALLSEQ_END are emitted.
579 /// TODO: isVarArg, isTailCall.
580 SDValue MipsTargetLowering::
581 LowerCALL(SDValue Op, SelectionDAG &DAG)
583 MachineFunction &MF = DAG.getMachineFunction();
585 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
586 SDValue Chain = TheCall->getChain();
587 SDValue Callee = TheCall->getCallee();
588 bool isVarArg = TheCall->isVarArg();
589 unsigned CC = TheCall->getCallingConv();
591 MachineFrameInfo *MFI = MF.getFrameInfo();
593 // Analyze operands of the call, assigning locations to each operand.
594 SmallVector<CCValAssign, 16> ArgLocs;
595 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
597 // To meet O32 ABI, Mips must always allocate 16 bytes on
598 // the stack (even if less than 4 are used as arguments)
599 if (Subtarget->isABI_O32()) {
600 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
601 MFI->CreateFixedObject(VTsize, (VTsize*3));
604 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
606 // Get a count of how many bytes are to be pushed on the stack.
607 unsigned NumBytes = CCInfo.getNextStackOffset();
608 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
610 // With EABI is it possible to have 16 args on registers.
611 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
612 SmallVector<SDValue, 8> MemOpChains;
614 // First/LastArgStackLoc contains the first/last
615 // "at stack" argument location.
616 int LastArgStackLoc = 0;
617 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
619 // Walk the register/memloc assignments, inserting copies/loads.
620 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
621 CCValAssign &VA = ArgLocs[i];
623 // Arguments start after the 5 first operands of ISD::CALL
624 SDValue Arg = TheCall->getArg(i);
626 // Promote the value if needed.
627 switch (VA.getLocInfo()) {
628 default: assert(0 && "Unknown loc info!");
629 case CCValAssign::Full: break;
630 case CCValAssign::SExt:
631 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
633 case CCValAssign::ZExt:
634 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
636 case CCValAssign::AExt:
637 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
641 // Arguments that can be passed on register must be kept at
644 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
648 // Register cant get to this point...
649 assert(VA.isMemLoc());
651 // Create the frame index object for this incoming parameter
652 // This guarantees that when allocating Local Area the firsts
653 // 16 bytes which are alwayes reserved won't be overwritten
654 // if O32 ABI is used. For EABI the first address is zero.
655 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
656 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
659 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
661 // emit ISD::STORE whichs stores the
662 // parameter value to a stack Location
663 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
666 // Transform all store nodes into one single node because all store
667 // nodes are independent of each other.
668 if (!MemOpChains.empty())
669 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
670 &MemOpChains[0], MemOpChains.size());
672 // Build a sequence of copy-to-reg nodes chained together with token
673 // chain and flag operands which copy the outgoing args into registers.
674 // The InFlag in necessary since all emited instructions must be
677 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
678 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
679 RegsToPass[i].second, InFlag);
680 InFlag = Chain.getValue(1);
683 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
684 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
685 // node so that legalize doesn't hack it.
686 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
687 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
688 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
689 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
692 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
693 // = Chain, Callee, Reg#1, Reg#2, ...
695 // Returns a chain & a flag for retval copy to use.
696 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
697 SmallVector<SDValue, 8> Ops;
698 Ops.push_back(Chain);
699 Ops.push_back(Callee);
701 // Add argument registers to the end of the list so that they are
702 // known live into the call.
703 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
704 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
705 RegsToPass[i].second.getValueType()));
707 if (InFlag.getNode())
708 Ops.push_back(InFlag);
710 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
711 InFlag = Chain.getValue(1);
713 // Create the CALLSEQ_END node.
714 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
715 DAG.getIntPtrConstant(0, true), InFlag);
716 InFlag = Chain.getValue(1);
718 // Create a stack location to hold GP when PIC is used. This stack
719 // location is used on function prologue to save GP and also after all
720 // emited CALL's to restore GP.
721 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
722 // Function can have an arbitrary number of calls, so
723 // hold the LastArgStackLoc with the biggest offset.
725 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
726 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
727 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
728 // Create the frame index only once. SPOffset here can be anything
729 // (this will be fixed on processFunctionBeforeFrameFinalized)
730 if (MipsFI->getGPStackOffset() == -1) {
731 FI = MFI->CreateFixedObject(4, 0);
734 MipsFI->setGPStackOffset(LastArgStackLoc);
738 FI = MipsFI->getGPFI();
739 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
740 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
741 Chain = GPLoad.getValue(1);
742 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
743 GPLoad, SDValue(0,0));
744 InFlag = Chain.getValue(1);
747 // Handle result values, copying them out of physregs into vregs that we
749 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
752 /// LowerCallResult - Lower the result values of an ISD::CALL into the
753 /// appropriate copies out of appropriate physical registers. This assumes that
754 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
755 /// being lowered. Returns a SDNode with the same number of values as the
757 SDNode *MipsTargetLowering::
758 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
759 unsigned CallingConv, SelectionDAG &DAG) {
761 bool isVarArg = TheCall->isVarArg();
763 // Assign locations to each value returned by this call.
764 SmallVector<CCValAssign, 16> RVLocs;
765 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
767 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
768 SmallVector<SDValue, 8> ResultVals;
770 // Copy all of the result registers out of their specified physreg.
771 for (unsigned i = 0; i != RVLocs.size(); ++i) {
772 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
773 RVLocs[i].getValVT(), InFlag).getValue(1);
774 InFlag = Chain.getValue(2);
775 ResultVals.push_back(Chain.getValue(0));
778 ResultVals.push_back(Chain);
780 // Merge everything together with a MERGE_VALUES node.
781 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
782 ResultVals.size()).getNode();
785 //===----------------------------------------------------------------------===//
786 // FORMAL_ARGUMENTS Calling Convention Implementation
787 //===----------------------------------------------------------------------===//
789 /// LowerFORMAL_ARGUMENTS - transform physical registers into
790 /// virtual registers and generate load operations for
791 /// arguments places on the stack.
793 SDValue MipsTargetLowering::
794 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
796 SDValue Root = Op.getOperand(0);
797 MachineFunction &MF = DAG.getMachineFunction();
798 MachineFrameInfo *MFI = MF.getFrameInfo();
799 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
801 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
802 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
804 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
806 // GP must be live into PIC and non-PIC call target.
807 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
809 // Assign locations to all of the incoming arguments.
810 SmallVector<CCValAssign, 16> ArgLocs;
811 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
813 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
814 SmallVector<SDValue, 16> ArgValues;
817 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
819 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
821 CCValAssign &VA = ArgLocs[i];
823 // Arguments stored on registers
825 MVT RegVT = VA.getLocVT();
826 TargetRegisterClass *RC = 0;
828 if (RegVT == MVT::i32)
829 RC = Mips::CPURegsRegisterClass;
830 else if (RegVT == MVT::f32) {
831 if (Subtarget->isSingleFloat())
832 RC = Mips::FGR32RegisterClass;
834 RC = Mips::AFGR32RegisterClass;
835 } else if (RegVT == MVT::f64) {
836 if (!Subtarget->isSingleFloat())
837 RC = Mips::AFGR64RegisterClass;
839 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
841 // Transform the arguments stored on
842 // physical registers into virtual ones
843 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
844 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
846 // If this is an 8 or 16-bit value, it is really passed promoted
847 // to 32 bits. Insert an assert[sz]ext to capture this, then
848 // truncate to the right size.
849 if (VA.getLocInfo() == CCValAssign::SExt)
850 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
851 DAG.getValueType(VA.getValVT()));
852 else if (VA.getLocInfo() == CCValAssign::ZExt)
853 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
854 DAG.getValueType(VA.getValVT()));
856 if (VA.getLocInfo() != CCValAssign::Full)
857 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
859 ArgValues.push_back(ArgValue);
861 // To meet ABI, when VARARGS are passed on registers, the registers
862 // must have their values written to the caller stack frame.
863 if ((isVarArg) && (Subtarget->isABI_O32())) {
864 if (StackPtr.getNode() == 0)
865 StackPtr = DAG.getRegister(StackReg, getPointerTy());
867 // The stack pointer offset is relative to the caller stack frame.
868 // Since the real stack size is unknown here, a negative SPOffset
869 // is used so there's a way to adjust these offsets when the stack
870 // size get known (on EliminateFrameIndex). A dummy SPOffset is
871 // used instead of a direct negative address (which is recorded to
872 // be used on emitPrologue) to avoid mis-calc of the first stack
873 // offset on PEI::calculateFrameObjectOffsets.
874 // Arguments are always 32-bit.
875 int FI = MFI->CreateFixedObject(4, 0);
876 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
877 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
879 // emit ISD::STORE whichs stores the
880 // parameter value to a stack Location
881 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
884 } else { // VA.isRegLoc()
887 assert(VA.isMemLoc());
889 // The stack pointer offset is relative to the caller stack frame.
890 // Since the real stack size is unknown here, a negative SPOffset
891 // is used so there's a way to adjust these offsets when the stack
892 // size get known (on EliminateFrameIndex). A dummy SPOffset is
893 // used instead of a direct negative address (which is recorded to
894 // be used on emitPrologue) to avoid mis-calc of the first stack
895 // offset on PEI::calculateFrameObjectOffsets.
896 // Arguments are always 32-bit.
897 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
898 int FI = MFI->CreateFixedObject(ArgSize, 0);
899 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
900 (FirstStackArgLoc + VA.getLocMemOffset())));
902 // Create load nodes to retrieve arguments from the stack
903 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
904 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
908 // The mips ABIs for returning structs by value requires that we copy
909 // the sret argument into $v0 for the return. Save the argument into
910 // a virtual register so that we can access it from the return points.
911 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
912 unsigned Reg = MipsFI->getSRetReturnReg();
914 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
915 MipsFI->setSRetReturnReg(Reg);
917 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
918 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
921 ArgValues.push_back(Root);
923 // Return the new list of results.
924 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
925 ArgValues.size()).getValue(Op.getResNo());
928 //===----------------------------------------------------------------------===//
929 // Return Value Calling Convention Implementation
930 //===----------------------------------------------------------------------===//
932 SDValue MipsTargetLowering::
933 LowerRET(SDValue Op, SelectionDAG &DAG)
935 // CCValAssign - represent the assignment of
936 // the return value to a location
937 SmallVector<CCValAssign, 16> RVLocs;
938 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
939 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
941 // CCState - Info about the registers and stack slot.
942 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
944 // Analize return values of ISD::RET
945 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
947 // If this is the first return lowered for this function, add
948 // the regs to the liveout set for the function.
949 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
950 for (unsigned i = 0; i != RVLocs.size(); ++i)
951 if (RVLocs[i].isRegLoc())
952 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
955 // The chain is always operand #0
956 SDValue Chain = Op.getOperand(0);
959 // Copy the result values into the output registers.
960 for (unsigned i = 0; i != RVLocs.size(); ++i) {
961 CCValAssign &VA = RVLocs[i];
962 assert(VA.isRegLoc() && "Can only return in registers!");
964 // ISD::RET => ret chain, (regnum1,val1), ...
965 // So i*2+1 index only the regnums
966 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
968 // guarantee that all emitted copies are
969 // stuck together, avoiding something bad
970 Flag = Chain.getValue(1);
973 // The mips ABIs for returning structs by value requires that we copy
974 // the sret argument into $v0 for the return. We saved the argument into
975 // a virtual register in the entry block, so now we copy the value out
977 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
978 MachineFunction &MF = DAG.getMachineFunction();
979 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
980 unsigned Reg = MipsFI->getSRetReturnReg();
983 assert(0 && "sret virtual register not created in the entry block");
984 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
986 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
987 Flag = Chain.getValue(1);
990 // Return on Mips is always a "jr $ra"
992 return DAG.getNode(MipsISD::Ret, MVT::Other,
993 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
995 return DAG.getNode(MipsISD::Ret, MVT::Other,
996 Chain, DAG.getRegister(Mips::RA, MVT::i32));
999 //===----------------------------------------------------------------------===//
1000 // Mips Inline Assembly Support
1001 //===----------------------------------------------------------------------===//
1003 /// getConstraintType - Given a constraint letter, return the type of
1004 /// constraint it is for this target.
1005 MipsTargetLowering::ConstraintType MipsTargetLowering::
1006 getConstraintType(const std::string &Constraint) const
1008 // Mips specific constrainy
1009 // GCC config/mips/constraints.md
1011 // 'd' : An address register. Equivalent to r
1012 // unless generating MIPS16 code.
1013 // 'y' : Equivalent to r; retained for
1014 // backwards compatibility.
1015 // 'f' : Floating Point registers.
1016 if (Constraint.size() == 1) {
1017 switch (Constraint[0]) {
1022 return C_RegisterClass;
1026 return TargetLowering::getConstraintType(Constraint);
1029 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1030 /// return a list of registers that can be used to satisfy the constraint.
1031 /// This should only be used for C_RegisterClass constraints.
1032 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1033 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1035 if (Constraint.size() == 1) {
1036 switch (Constraint[0]) {
1038 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1040 if (VT == MVT::f32) {
1041 if (Subtarget->isSingleFloat())
1042 return std::make_pair(0U, Mips::FGR32RegisterClass);
1044 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1047 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1048 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1051 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1054 /// Given a register class constraint, like 'r', if this corresponds directly
1055 /// to an LLVM register class, return a register of 0 and the register class
1057 std::vector<unsigned> MipsTargetLowering::
1058 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1061 if (Constraint.size() != 1)
1062 return std::vector<unsigned>();
1064 switch (Constraint[0]) {
1067 // GCC Mips Constraint Letters
1070 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1071 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1072 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1076 if (VT == MVT::f32) {
1077 if (Subtarget->isSingleFloat())
1078 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1079 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1080 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1081 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1082 Mips::F30, Mips::F31, 0);
1084 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1085 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1086 Mips::F28, Mips::F30, 0);
1090 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1091 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1092 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1093 Mips::D14, Mips::D15, 0);
1095 return std::vector<unsigned>();