1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::Ret : return "MipsISD::Ret";
45 default : return NULL;
50 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
52 // Mips does not have i1 type, so use i32 for
53 // setcc operations results (slt, sgt, ...).
54 setSetCCResultType(MVT::i32);
55 setSetCCResultContents(ZeroOrOneSetCCResult);
57 // Set up the register classes
58 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
61 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
62 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
63 setOperationAction(ISD::RET, MVT::Other, Custom);
65 // Load extented operations for i1 types must be promoted
66 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
67 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 // Store operations for i1 types must be promoted
71 setStoreXAction(MVT::i1, Promote);
73 // Mips does not have these NodeTypes below.
74 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
75 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
78 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 // Mips not supported intrinsics.
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
85 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
86 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
87 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
88 setOperationAction(ISD::ROTL , MVT::i32, Expand);
89 setOperationAction(ISD::ROTR , MVT::i32, Expand);
90 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
92 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
93 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
94 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
96 // We don't have line number support yet.
97 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
98 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
99 setOperationAction(ISD::LABEL, MVT::Other, Expand);
101 // Use the default for now
102 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
103 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
105 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand);
107 setStackPointerRegisterToSaveRestore(Mips::SP);
108 computeRegisterProperties();
112 SDOperand MipsTargetLowering::
113 LowerOperation(SDOperand Op, SelectionDAG &DAG)
115 switch (Op.getOpcode())
117 case ISD::CALL: return LowerCALL(Op, DAG);
118 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
119 case ISD::RET: return LowerRET(Op, DAG);
120 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
121 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
122 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
127 //===----------------------------------------------------------------------===//
128 // Lower helper functions
129 //===----------------------------------------------------------------------===//
131 // AddLiveIn - This helper function adds the specified physical register to the
132 // MachineFunction as a live in value. It also creates a corresponding
133 // virtual register for it.
135 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
137 assert(RC->contains(PReg) && "Not the correct regclass!");
138 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
139 MF.addLiveIn(PReg, VReg);
143 // Set up a frame object for the return address.
144 //SDOperand MipsTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
145 // if (ReturnAddrIndex == 0) {
146 // MachineFunction &MF = DAG.getMachineFunction();
147 // ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, 0);
150 // return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
154 //===----------------------------------------------------------------------===//
155 // Misc Lower Operation implementation
156 //===----------------------------------------------------------------------===//
157 SDOperand MipsTargetLowering::
158 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
160 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
162 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
163 SDOperand Hi = DAG.getNode(MipsISD::Hi, MVT::i32, GA);
164 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
166 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
169 SDOperand MipsTargetLowering::
170 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
172 assert(0 && "TLS not implemented for MIPS.");
175 //===----------------------------------------------------------------------===//
176 // Calling Convention Implementation
178 // The lower operations present on calling convention works on this order:
179 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
180 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
181 // LowerRET (virt regs --> phys regs)
182 // LowerCALL (phys regs --> virt regs)
184 //===----------------------------------------------------------------------===//
186 #include "MipsGenCallingConv.inc"
188 //===----------------------------------------------------------------------===//
189 // CALL Calling Convention Implementation
190 //===----------------------------------------------------------------------===//
192 /// Mips custom CALL implementation
193 SDOperand MipsTargetLowering::
194 LowerCALL(SDOperand Op, SelectionDAG &DAG)
196 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
198 // By now, only CallingConv::C implemented
202 assert(0 && "Unsupported calling convention");
203 case CallingConv::Fast:
205 return LowerCCCCallTo(Op, DAG, CallingConv);
209 /// LowerCCCCallTo - functions arguments are copied from virtual
210 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
211 /// CALLSEQ_END are emitted.
212 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
213 SDOperand MipsTargetLowering::
214 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
216 MachineFunction &MF = DAG.getMachineFunction();
217 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
219 SDOperand Chain = Op.getOperand(0);
220 SDOperand Callee = Op.getOperand(4);
221 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
223 MachineFrameInfo *MFI = MF.getFrameInfo();
225 // Analyze operands of the call, assigning locations to each operand.
226 SmallVector<CCValAssign, 16> ArgLocs;
227 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
229 // To meet ABI, Mips must always allocate 16 bytes on
230 // the stack (even if less than 4 are used as arguments)
231 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
232 MFI->CreateFixedObject(VTsize, -(VTsize*3));
234 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
236 // Get a count of how many bytes are to be pushed on the stack.
237 unsigned NumBytes = CCInfo.getNextStackOffset();
238 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
241 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
242 SmallVector<SDOperand, 8> MemOpChains;
246 // Walk the register/memloc assignments, inserting copies/loads.
247 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
248 CCValAssign &VA = ArgLocs[i];
250 // Arguments start after the 5 first operands of ISD::CALL
251 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
253 // Promote the value if needed.
254 switch (VA.getLocInfo()) {
255 default: assert(0 && "Unknown loc info!");
256 case CCValAssign::Full: break;
257 case CCValAssign::SExt:
258 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
260 case CCValAssign::ZExt:
261 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
263 case CCValAssign::AExt:
264 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
268 // Arguments that can be passed on register,
269 // must be kept at RegsToPass vector
271 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
274 assert(VA.isMemLoc());
276 if (StackPtr.Val == 0)
277 StackPtr = DAG.getRegister(StackReg, getPointerTy());
279 // Create the frame index object for this incoming parameter
280 // This guarantees that when allocating Local Area our room
281 // will not be overwritten.
282 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
283 -(16 + VA.getLocMemOffset()) );
285 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
287 // emit ISD::STORE whichs stores the
288 // parameter value to a stack Location
289 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
293 // Transform all store nodes into one single node because
294 // all store nodes are independent of each other.
295 if (!MemOpChains.empty())
296 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
297 &MemOpChains[0], MemOpChains.size());
299 // Build a sequence of copy-to-reg nodes chained together with token
300 // chain and flag operands which copy the outgoing args into registers.
301 // The InFlag in necessary since all emited instructions must be
304 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
305 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
306 RegsToPass[i].second, InFlag);
307 InFlag = Chain.getValue(1);
310 // If the callee is a GlobalAddress node (quite common, every direct
311 // call is) turn it into a TargetGlobalAddress node so that legalize
313 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
314 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
316 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
317 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
319 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
320 // = Chain, Callee, Reg#1, Reg#2, ...
322 // Returns a chain & a flag for retval copy to use.
323 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
324 SmallVector<SDOperand, 8> Ops;
325 Ops.push_back(Chain);
326 Ops.push_back(Callee);
328 // Add argument registers to the end of the list so that they are
329 // known live into the call.
330 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
331 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
332 RegsToPass[i].second.getValueType()));
335 Ops.push_back(InFlag);
337 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
338 InFlag = Chain.getValue(1);
340 // Create the CALLSEQ_END node.
341 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
343 Ops.push_back(Chain);
344 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
345 Ops.push_back(InFlag);
346 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
347 InFlag = Chain.getValue(1);
349 // Handle result values, copying them out of physregs into vregs that we
351 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
354 /// LowerCallResult - Lower the result values of an ISD::CALL into the
355 /// appropriate copies out of appropriate physical registers. This assumes that
356 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
357 /// being lowered. Returns a SDNode with the same number of values as the
359 SDNode *MipsTargetLowering::
360 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
361 unsigned CallingConv, SelectionDAG &DAG) {
363 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
365 // Assign locations to each value returned by this call.
366 SmallVector<CCValAssign, 16> RVLocs;
367 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
369 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
370 SmallVector<SDOperand, 8> ResultVals;
376 // Copy all of the result registers out of their specified physreg.
377 for (unsigned i = 0; i != RVLocs.size(); ++i) {
378 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
379 RVLocs[i].getValVT(), InFlag).getValue(1);
380 InFlag = Chain.getValue(2);
381 ResultVals.push_back(Chain.getValue(0));
384 // Merge everything together with a MERGE_VALUES node.
385 ResultVals.push_back(Chain);
386 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
387 &ResultVals[0], ResultVals.size()).Val;
390 //===----------------------------------------------------------------------===//
391 // FORMAL_ARGUMENTS Calling Convention Implementation
392 //===----------------------------------------------------------------------===//
394 /// Mips custom FORMAL_ARGUMENTS implementation
395 SDOperand MipsTargetLowering::
396 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
398 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
402 assert(0 && "Unsupported calling convention");
404 return LowerCCCArguments(Op, DAG);
408 /// LowerCCCArguments - transform physical registers into
409 /// virtual registers and generate load operations for
410 /// arguments places on the stack.
411 /// TODO: isVarArg, sret
412 SDOperand MipsTargetLowering::
413 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
415 SDOperand Root = Op.getOperand(0);
416 MachineFunction &MF = DAG.getMachineFunction();
417 MachineFrameInfo *MFI = MF.getFrameInfo();
419 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
420 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
422 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
424 // Assign locations to all of the incoming arguments.
425 SmallVector<CCValAssign, 16> ArgLocs;
426 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
428 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
429 SmallVector<SDOperand, 8> ArgValues;
432 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
434 CCValAssign &VA = ArgLocs[i];
436 // Arguments stored on registers
438 MVT::ValueType RegVT = VA.getLocVT();
439 TargetRegisterClass *RC;
441 if (RegVT == MVT::i32)
442 RC = Mips::CPURegsRegisterClass;
444 assert(0 && "support only Mips::CPURegsRegisterClass");
447 // Transform the arguments stored on
448 // physical registers into virtual ones
449 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
450 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
452 // If this is an 8 or 16-bit value, it is really passed promoted
453 // to 32 bits. Insert an assert[sz]ext to capture this, then
454 // truncate to the right size.
455 if (VA.getLocInfo() == CCValAssign::SExt)
456 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
457 DAG.getValueType(VA.getValVT()));
458 else if (VA.getLocInfo() == CCValAssign::ZExt)
459 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
460 DAG.getValueType(VA.getValVT()));
462 if (VA.getLocInfo() != CCValAssign::Full)
463 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
465 ArgValues.push_back(ArgValue);
467 // To meet ABI, when VARARGS are passed on registers, the registers
468 // containt must be written to the their always reserved home location
472 if (StackPtr.Val == 0)
473 StackPtr = DAG.getRegister(StackReg, getPointerTy());
475 // Create the frame index object for this incoming parameter
476 // The first 16 bytes are reserved.
477 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
479 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
481 // emit ISD::STORE whichs stores the
482 // parameter value to a stack Location
483 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
488 assert(VA.isMemLoc());
490 // Create the frame index object for this incoming parameter...
491 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
492 (16 + VA.getLocMemOffset()));
494 // Create load nodes to retrieve arguments from the stack
495 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
496 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
499 ArgValues.push_back(Root);
501 // Return the new list of results.
502 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
503 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
506 //===----------------------------------------------------------------------===//
507 // Return Value Calling Convention Implementation
508 //===----------------------------------------------------------------------===//
510 SDOperand MipsTargetLowering::
511 LowerRET(SDOperand Op, SelectionDAG &DAG)
513 // CCValAssign - represent the assignment of
514 // the return value to a location
515 SmallVector<CCValAssign, 16> RVLocs;
516 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
517 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
519 // CCState - Info about the registers and stack slot.
520 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
522 // Analize return values of ISD::RET
523 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
525 // If this is the first return lowered for this function, add
526 // the regs to the liveout set for the function.
527 if (DAG.getMachineFunction().liveout_empty()) {
528 for (unsigned i = 0; i != RVLocs.size(); ++i)
529 if (RVLocs[i].isRegLoc())
530 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
533 // The chain is always operand #0
534 SDOperand Chain = Op.getOperand(0);
537 // Copy the result values into the output registers.
538 for (unsigned i = 0; i != RVLocs.size(); ++i) {
539 CCValAssign &VA = RVLocs[i];
540 assert(VA.isRegLoc() && "Can only return in registers!");
542 // ISD::RET => ret chain, (regnum1,val1), ...
543 // So i*2+1 index only the regnums
544 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
545 Op.getOperand(i*2+1), Flag);
547 // guarantee that all emitted copies are
548 // stuck together, avoiding something bad
549 Flag = Chain.getValue(1);
552 // Return on Mips is always a "jr $ra"
554 return DAG.getNode(MipsISD::Ret, MVT::Other,
555 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
557 return DAG.getNode(MipsISD::Ret, MVT::Other,
558 Chain, DAG.getRegister(Mips::RA, MVT::i32));