1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::GPRel : return "MipsISD::GPRel";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::CMov : return "MipsISD::CMov";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
49 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
50 case MipsISD::FPCmp : return "MipsISD::FPCmp";
51 case MipsISD::FPRound : return "MipsISD::FPRound";
52 default : return NULL;
57 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
59 Subtarget = &TM.getSubtarget<MipsSubtarget>();
61 // Mips does not have i1 type, so use i32 for
62 // setcc operations results (slt, sgt, ...).
63 setBooleanContents(ZeroOrOneBooleanContent);
65 // JumpTable targets must use GOT when using PIC_
66 setUsesGlobalOffsetTable(true);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat())
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addLegalFPImmediate(APFloat(+0.0f));
80 // Load extented operations for i1 types must be promoted
81 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 // Used by legalize types to correctly generate the setcc result.
86 // Without this, every float setcc comes with a AND/OR with the result,
87 // we don't want this, since the fpcmp result goes to a flag register,
88 // which is used implicitly by brcond and select operations.
89 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
91 // Mips Custom Operations
92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
94 setOperationAction(ISD::RET, MVT::Other, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
96 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::f32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Custom);
99 setOperationAction(ISD::SELECT, MVT::i32, Custom);
100 setOperationAction(ISD::SETCC, MVT::f32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f64, Custom);
102 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
103 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
107 // with operands comming from setcc fp comparions. This is necessary since
108 // the result from these setcc are in a flag registers (FCR31).
109 setOperationAction(ISD::AND, MVT::i32, Custom);
110 setOperationAction(ISD::OR, MVT::i32, Custom);
112 // Operations not directly supported by Mips.
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
115 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
117 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
120 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
121 setOperationAction(ISD::ROTL, MVT::i32, Expand);
122 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
126 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
128 // We don't have line number support yet.
129 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
130 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
131 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
132 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
134 // Use the default for now
135 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
136 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
137 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
139 if (Subtarget->isSingleFloat())
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
142 if (!Subtarget->hasSEInReg()) {
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 if (!Subtarget->hasBitCount())
148 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
150 if (!Subtarget->hasSwap())
151 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
153 setStackPointerRegisterToSaveRestore(Mips::SP);
154 computeRegisterProperties();
158 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
163 SDValue MipsTargetLowering::
164 LowerOperation(SDValue Op, SelectionDAG &DAG)
166 switch (Op.getOpcode())
168 case ISD::AND: return LowerANDOR(Op, DAG);
169 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
170 case ISD::CALL: return LowerCALL(Op, DAG);
171 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
172 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
173 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
174 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
175 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
176 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
177 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
178 case ISD::OR: return LowerANDOR(Op, DAG);
179 case ISD::RET: return LowerRET(Op, DAG);
180 case ISD::SELECT: return LowerSELECT(Op, DAG);
181 case ISD::SETCC: return LowerSETCC(Op, DAG);
186 //===----------------------------------------------------------------------===//
187 // Lower helper functions
188 //===----------------------------------------------------------------------===//
190 // AddLiveIn - This helper function adds the specified physical register to the
191 // MachineFunction as a live in value. It also creates a corresponding
192 // virtual register for it.
194 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
196 assert(RC->contains(PReg) && "Not the correct regclass!");
197 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
198 MF.getRegInfo().addLiveIn(PReg, VReg);
202 // A address must be loaded from a small section if its size is less than the
203 // small section size threshold. Data in this section must be addressed using
205 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
206 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
209 // Discover if this global address can be placed into small data/bss section.
210 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
212 const TargetData *TD = getTargetData();
213 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
218 const Type *Ty = GV->getType()->getElementType();
219 unsigned Size = TD->getTypeAllocSize(Ty);
221 // if this is a internal constant string, there is a special
222 // section for it, but not in small data/bss.
223 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
224 Constant *C = GVA->getInitializer();
225 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
226 if (CVA && CVA->isCString())
230 return IsInSmallSection(Size);
233 // Get fp branch code (not opcode) from condition code.
234 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
235 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
236 return Mips::BRANCH_T;
238 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
239 return Mips::BRANCH_F;
241 return Mips::BRANCH_INVALID;
244 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
247 assert(0 && "Unknown branch code");
248 case Mips::BRANCH_T : return Mips::BC1T;
249 case Mips::BRANCH_F : return Mips::BC1F;
250 case Mips::BRANCH_TL : return Mips::BC1TL;
251 case Mips::BRANCH_FL : return Mips::BC1FL;
255 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
257 default: assert(0 && "Unknown fp condition code!");
259 case ISD::SETOEQ: return Mips::FCOND_EQ;
260 case ISD::SETUNE: return Mips::FCOND_OGL;
262 case ISD::SETOLT: return Mips::FCOND_OLT;
264 case ISD::SETOGT: return Mips::FCOND_OGT;
266 case ISD::SETOLE: return Mips::FCOND_OLE;
268 case ISD::SETOGE: return Mips::FCOND_OGE;
269 case ISD::SETULT: return Mips::FCOND_ULT;
270 case ISD::SETULE: return Mips::FCOND_ULE;
271 case ISD::SETUGT: return Mips::FCOND_UGT;
272 case ISD::SETUGE: return Mips::FCOND_UGE;
273 case ISD::SETUO: return Mips::FCOND_UN;
274 case ISD::SETO: return Mips::FCOND_OR;
276 case ISD::SETONE: return Mips::FCOND_NEQ;
277 case ISD::SETUEQ: return Mips::FCOND_UEQ;
282 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
283 MachineBasicBlock *BB) const {
284 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
285 bool isFPCmp = false;
286 DebugLoc dl = MI->getDebugLoc();
288 switch (MI->getOpcode()) {
289 default: assert(false && "Unexpected instr type to insert");
290 case Mips::Select_FCC:
291 case Mips::Select_FCC_S32:
292 case Mips::Select_FCC_D32:
293 isFPCmp = true; // FALL THROUGH
294 case Mips::Select_CC:
295 case Mips::Select_CC_S32:
296 case Mips::Select_CC_D32: {
297 // To "insert" a SELECT_CC instruction, we actually have to insert the
298 // diamond control-flow pattern. The incoming instruction knows the
299 // destination vreg to set, the condition code register to branch on, the
300 // true/false values to select between, and a branch opcode to use.
301 const BasicBlock *LLVM_BB = BB->getBasicBlock();
302 MachineFunction::iterator It = BB;
309 // bNE r1, r0, copy1MBB
310 // fallthrough --> copy0MBB
311 MachineBasicBlock *thisMBB = BB;
312 MachineFunction *F = BB->getParent();
313 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
314 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
316 // Emit the right instruction according to the type of the operands compared
318 // Find the condiction code present in the setcc operation.
319 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
320 // Get the branch opcode from the branch code.
321 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
322 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
324 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
325 .addReg(Mips::ZERO).addMBB(sinkMBB);
327 F->insert(It, copy0MBB);
328 F->insert(It, sinkMBB);
329 // Update machine-CFG edges by first adding all successors of the current
330 // block to the new block which will contain the Phi node for the select.
331 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
332 e = BB->succ_end(); i != e; ++i)
333 sinkMBB->addSuccessor(*i);
334 // Next, remove all successors of the current block, and add the true
335 // and fallthrough blocks as its successors.
336 while(!BB->succ_empty())
337 BB->removeSuccessor(BB->succ_begin());
338 BB->addSuccessor(copy0MBB);
339 BB->addSuccessor(sinkMBB);
343 // # fallthrough to sinkMBB
346 // Update machine-CFG edges
347 BB->addSuccessor(sinkMBB);
350 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
353 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
354 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
355 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
357 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
363 //===----------------------------------------------------------------------===//
364 // Misc Lower Operation implementation
365 //===----------------------------------------------------------------------===//
367 SDValue MipsTargetLowering::
368 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
370 if (!Subtarget->isMips1())
373 MachineFunction &MF = DAG.getMachineFunction();
374 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
376 SDValue Chain = DAG.getEntryNode();
377 DebugLoc dl = Op.getDebugLoc();
378 SDValue Src = Op.getOperand(0);
380 // Set the condition register
381 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
382 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
383 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
385 SDValue Cst = DAG.getConstant(3, MVT::i32);
386 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
387 Cst = DAG.getConstant(2, MVT::i32);
388 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
390 SDValue InFlag(0, 0);
391 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
393 // Emit the round instruction and bit convert to integer
394 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
395 Src, CondReg.getValue(1));
396 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
400 SDValue MipsTargetLowering::
401 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
403 SDValue Chain = Op.getOperand(0);
404 SDValue Size = Op.getOperand(1);
405 DebugLoc dl = Op.getDebugLoc();
407 // Get a reference from Mips stack pointer
408 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
410 // Subtract the dynamic size from the actual stack size to
411 // obtain the new stack size.
412 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
414 // The Sub result contains the new stack start address, so it
415 // must be placed in the stack pointer register.
416 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
418 // This node always has two return values: a new stack pointer
420 SDValue Ops[2] = { Sub, Chain };
421 return DAG.getMergeValues(Ops, 2, dl);
424 SDValue MipsTargetLowering::
425 LowerANDOR(SDValue Op, SelectionDAG &DAG)
427 SDValue LHS = Op.getOperand(0);
428 SDValue RHS = Op.getOperand(1);
429 DebugLoc dl = Op.getDebugLoc();
431 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
434 SDValue True = DAG.getConstant(1, MVT::i32);
435 SDValue False = DAG.getConstant(0, MVT::i32);
437 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
438 LHS, True, False, LHS.getOperand(2));
439 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
440 RHS, True, False, RHS.getOperand(2));
442 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
445 SDValue MipsTargetLowering::
446 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
448 // The first operand is the chain, the second is the condition, the third is
449 // the block to branch to if the condition is true.
450 SDValue Chain = Op.getOperand(0);
451 SDValue Dest = Op.getOperand(2);
452 DebugLoc dl = Op.getDebugLoc();
454 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
457 SDValue CondRes = Op.getOperand(1);
458 SDValue CCNode = CondRes.getOperand(2);
460 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
461 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
463 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
467 SDValue MipsTargetLowering::
468 LowerSETCC(SDValue Op, SelectionDAG &DAG)
470 // The operands to this are the left and right operands to compare (ops #0,
471 // and #1) and the condition code to compare them with (op #2) as a
473 SDValue LHS = Op.getOperand(0);
474 SDValue RHS = Op.getOperand(1);
475 DebugLoc dl = Op.getDebugLoc();
477 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
479 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
480 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
483 SDValue MipsTargetLowering::
484 LowerSELECT(SDValue Op, SelectionDAG &DAG)
486 SDValue Cond = Op.getOperand(0);
487 SDValue True = Op.getOperand(1);
488 SDValue False = Op.getOperand(2);
489 DebugLoc dl = Op.getDebugLoc();
491 // if the incomming condition comes from a integer compare, the select
492 // operation must be SelectCC or a conditional move if the subtarget
494 if (Cond.getOpcode() != MipsISD::FPCmp) {
495 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
497 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
501 // if the incomming condition comes from fpcmp, the select
502 // operation must use FPSelectCC.
503 SDValue CCNode = Cond.getOperand(2);
504 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
505 Cond, True, False, CCNode);
508 SDValue MipsTargetLowering::
509 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
511 // FIXME there isn't actually debug info here
512 DebugLoc dl = Op.getDebugLoc();
513 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
514 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
516 if (!Subtarget->hasABICall()) {
517 SDVTList VTs = DAG.getVTList(MVT::i32);
518 SDValue Ops[] = { GA };
519 // %gp_rel relocation
520 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
521 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
522 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
523 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
525 // %hi/%lo relocation
526 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
527 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
528 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
530 } else { // Abicall relocations, TODO: make this cleaner.
531 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
532 DAG.getEntryNode(), GA, NULL, 0);
533 // On functions and global targets not internal linked only
534 // a load from got/GP is necessary for PIC to work.
535 if (!GV->hasLocalLinkage() || isa<Function>(GV))
537 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
538 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
541 assert(0 && "Dont know how to handle GlobalAddress");
545 SDValue MipsTargetLowering::
546 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
548 assert(0 && "TLS not implemented for MIPS.");
549 return SDValue(); // Not reached
552 SDValue MipsTargetLowering::
553 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
557 // FIXME there isn't actually debug info here
558 DebugLoc dl = Op.getDebugLoc();
560 MVT PtrVT = Op.getValueType();
561 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
562 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
564 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
565 SDVTList VTs = DAG.getVTList(MVT::i32);
566 SDValue Ops[] = { JTI };
567 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
568 } else // Emit Load from Global Pointer
569 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
571 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
572 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
577 SDValue MipsTargetLowering::
578 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
581 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
582 Constant *C = N->getConstVal();
583 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
584 // FIXME there isn't actually debug info here
585 DebugLoc dl = Op.getDebugLoc();
588 // FIXME: we should reference the constant pool using small data sections,
589 // but the asm printer currently doens't support this feature without
590 // hacking it. This feature should come soon so we can uncomment the
592 //if (!Subtarget->hasABICall() &&
593 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
594 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
595 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
596 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
597 //} else { // %hi/%lo relocation
598 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
599 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
600 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
606 //===----------------------------------------------------------------------===//
607 // Calling Convention Implementation
609 // The lower operations present on calling convention works on this order:
610 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
611 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
612 // LowerRET (virt regs --> phys regs)
613 // LowerCALL (phys regs --> virt regs)
615 //===----------------------------------------------------------------------===//
617 #include "MipsGenCallingConv.inc"
619 //===----------------------------------------------------------------------===//
620 // TODO: Implement a generic logic using tblgen that can support this.
621 // Mips O32 ABI rules:
623 // i32 - Passed in A0, A1, A2, A3 and stack
624 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
625 // an argument. Otherwise, passed in A1, A2, A3 and stack.
626 // f64 - Only passed in two aliased f32 registers if no int reg has been used
627 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
628 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
630 //===----------------------------------------------------------------------===//
632 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
633 MVT LocVT, CCValAssign::LocInfo LocInfo,
634 ISD::ArgFlagsTy ArgFlags, CCState &State) {
636 static const unsigned IntRegsSize=4, FloatRegsSize=2;
638 static const unsigned IntRegs[] = {
639 Mips::A0, Mips::A1, Mips::A2, Mips::A3
641 static const unsigned F32Regs[] = {
644 static const unsigned F64Regs[] = {
649 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
650 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
652 // Promote i8 and i16
653 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
655 if (ArgFlags.isSExt())
656 LocInfo = CCValAssign::SExt;
657 else if (ArgFlags.isZExt())
658 LocInfo = CCValAssign::ZExt;
660 LocInfo = CCValAssign::AExt;
663 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
664 Reg = State.AllocateReg(IntRegs, IntRegsSize);
669 if (ValVT.isFloatingPoint() && !IntRegUsed) {
670 if (ValVT == MVT::f32)
671 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
673 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
676 if (ValVT == MVT::f64 && IntRegUsed) {
677 if (UnallocIntReg != IntRegsSize) {
678 // If we hit register A3 as the first not allocated, we must
679 // mark it as allocated (shadow) and use the stack instead.
680 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
682 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
683 State.AllocateReg(UnallocIntReg);
689 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
690 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
691 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
693 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
695 return false; // CC must always match
698 //===----------------------------------------------------------------------===//
699 // CALL Calling Convention Implementation
700 //===----------------------------------------------------------------------===//
702 /// LowerCALL - functions arguments are copied from virtual regs to
703 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
704 /// TODO: isVarArg, isTailCall.
705 SDValue MipsTargetLowering::
706 LowerCALL(SDValue Op, SelectionDAG &DAG)
708 MachineFunction &MF = DAG.getMachineFunction();
710 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
711 SDValue Chain = TheCall->getChain();
712 SDValue Callee = TheCall->getCallee();
713 bool isVarArg = TheCall->isVarArg();
714 unsigned CC = TheCall->getCallingConv();
715 DebugLoc dl = TheCall->getDebugLoc();
717 MachineFrameInfo *MFI = MF.getFrameInfo();
719 // Analyze operands of the call, assigning locations to each operand.
720 SmallVector<CCValAssign, 16> ArgLocs;
721 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
723 // To meet O32 ABI, Mips must always allocate 16 bytes on
724 // the stack (even if less than 4 are used as arguments)
725 if (Subtarget->isABI_O32()) {
726 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
727 MFI->CreateFixedObject(VTsize, (VTsize*3));
728 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
730 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
732 // Get a count of how many bytes are to be pushed on the stack.
733 unsigned NumBytes = CCInfo.getNextStackOffset();
734 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
736 // With EABI is it possible to have 16 args on registers.
737 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
738 SmallVector<SDValue, 8> MemOpChains;
740 // First/LastArgStackLoc contains the first/last
741 // "at stack" argument location.
742 int LastArgStackLoc = 0;
743 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
745 // Walk the register/memloc assignments, inserting copies/loads.
746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
747 SDValue Arg = TheCall->getArg(i);
748 CCValAssign &VA = ArgLocs[i];
750 // Promote the value if needed.
751 switch (VA.getLocInfo()) {
752 default: assert(0 && "Unknown loc info!");
753 case CCValAssign::Full:
754 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
755 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
756 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
757 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
758 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
759 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
760 DAG.getConstant(0, getPointerTy()));
761 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
762 DAG.getConstant(1, getPointerTy()));
763 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
764 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
769 case CCValAssign::SExt:
770 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
772 case CCValAssign::ZExt:
773 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
775 case CCValAssign::AExt:
776 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
780 // Arguments that can be passed on register must be kept at
783 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
787 // Register can't get to this point...
788 assert(VA.isMemLoc());
790 // Create the frame index object for this incoming parameter
791 // This guarantees that when allocating Local Area the firsts
792 // 16 bytes which are alwayes reserved won't be overwritten
793 // if O32 ABI is used. For EABI the first address is zero.
794 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
795 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
798 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
800 // emit ISD::STORE whichs stores the
801 // parameter value to a stack Location
802 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
805 // Transform all store nodes into one single node because all store
806 // nodes are independent of each other.
807 if (!MemOpChains.empty())
808 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
809 &MemOpChains[0], MemOpChains.size());
811 // Build a sequence of copy-to-reg nodes chained together with token
812 // chain and flag operands which copy the outgoing args into registers.
813 // The InFlag in necessary since all emited instructions must be
816 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
817 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
818 RegsToPass[i].second, InFlag);
819 InFlag = Chain.getValue(1);
822 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
823 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
824 // node so that legalize doesn't hack it.
825 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
826 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
827 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
828 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
830 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
831 // = Chain, Callee, Reg#1, Reg#2, ...
833 // Returns a chain & a flag for retval copy to use.
834 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
835 SmallVector<SDValue, 8> Ops;
836 Ops.push_back(Chain);
837 Ops.push_back(Callee);
839 // Add argument registers to the end of the list so that they are
840 // known live into the call.
841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
842 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
843 RegsToPass[i].second.getValueType()));
845 if (InFlag.getNode())
846 Ops.push_back(InFlag);
848 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
849 InFlag = Chain.getValue(1);
851 // Create the CALLSEQ_END node.
852 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
853 DAG.getIntPtrConstant(0, true), InFlag);
854 InFlag = Chain.getValue(1);
856 // Create a stack location to hold GP when PIC is used. This stack
857 // location is used on function prologue to save GP and also after all
858 // emited CALL's to restore GP.
859 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
860 // Function can have an arbitrary number of calls, so
861 // hold the LastArgStackLoc with the biggest offset.
863 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
864 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
865 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
866 // Create the frame index only once. SPOffset here can be anything
867 // (this will be fixed on processFunctionBeforeFrameFinalized)
868 if (MipsFI->getGPStackOffset() == -1) {
869 FI = MFI->CreateFixedObject(4, 0);
872 MipsFI->setGPStackOffset(LastArgStackLoc);
876 FI = MipsFI->getGPFI();
877 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
878 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
879 Chain = GPLoad.getValue(1);
880 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
881 GPLoad, SDValue(0,0));
882 InFlag = Chain.getValue(1);
885 // Handle result values, copying them out of physregs into vregs that we
887 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
890 /// LowerCallResult - Lower the result values of an ISD::CALL into the
891 /// appropriate copies out of appropriate physical registers. This assumes that
892 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
893 /// being lowered. Returns a SDNode with the same number of values as the
895 SDNode *MipsTargetLowering::
896 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
897 unsigned CallingConv, SelectionDAG &DAG) {
899 bool isVarArg = TheCall->isVarArg();
900 DebugLoc dl = TheCall->getDebugLoc();
902 // Assign locations to each value returned by this call.
903 SmallVector<CCValAssign, 16> RVLocs;
904 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
906 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
907 SmallVector<SDValue, 8> ResultVals;
909 // Copy all of the result registers out of their specified physreg.
910 for (unsigned i = 0; i != RVLocs.size(); ++i) {
911 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
912 RVLocs[i].getValVT(), InFlag).getValue(1);
913 InFlag = Chain.getValue(2);
914 ResultVals.push_back(Chain.getValue(0));
917 ResultVals.push_back(Chain);
919 // Merge everything together with a MERGE_VALUES node.
920 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
921 &ResultVals[0], ResultVals.size()).getNode();
924 //===----------------------------------------------------------------------===//
925 // FORMAL_ARGUMENTS Calling Convention Implementation
926 //===----------------------------------------------------------------------===//
928 /// LowerFORMAL_ARGUMENTS - transform physical registers into
929 /// virtual registers and generate load operations for
930 /// arguments places on the stack.
932 SDValue MipsTargetLowering::
933 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
935 SDValue Root = Op.getOperand(0);
936 MachineFunction &MF = DAG.getMachineFunction();
937 MachineFrameInfo *MFI = MF.getFrameInfo();
938 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
939 DebugLoc dl = Op.getDebugLoc();
941 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
942 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
944 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
946 // Assign locations to all of the incoming arguments.
947 SmallVector<CCValAssign, 16> ArgLocs;
948 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
950 if (Subtarget->isABI_O32())
951 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
953 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
955 SmallVector<SDValue, 16> ArgValues;
958 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
960 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
961 CCValAssign &VA = ArgLocs[i];
963 // Arguments stored on registers
965 MVT RegVT = VA.getLocVT();
966 TargetRegisterClass *RC = 0;
968 if (RegVT == MVT::i32)
969 RC = Mips::CPURegsRegisterClass;
970 else if (RegVT == MVT::f32)
971 RC = Mips::FGR32RegisterClass;
972 else if (RegVT == MVT::f64) {
973 if (!Subtarget->isSingleFloat())
974 RC = Mips::AFGR64RegisterClass;
976 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
978 // Transform the arguments stored on
979 // physical registers into virtual ones
980 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
981 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
983 // If this is an 8 or 16-bit value, it has been passed promoted
984 // to 32 bits. Insert an assert[sz]ext to capture this, then
985 // truncate to the right size.
986 if (VA.getLocInfo() != CCValAssign::Full) {
988 if (VA.getLocInfo() == CCValAssign::SExt)
989 Opcode = ISD::AssertSext;
990 else if (VA.getLocInfo() == CCValAssign::ZExt)
991 Opcode = ISD::AssertZext;
993 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
994 DAG.getValueType(VA.getValVT()));
995 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
998 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
999 if (Subtarget->isABI_O32()) {
1000 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1001 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1002 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1003 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1004 VA.getLocReg()+1, RC);
1005 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
1006 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1007 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1008 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1012 ArgValues.push_back(ArgValue);
1014 // To meet ABI, when VARARGS are passed on registers, the registers
1015 // must have their values written to the caller stack frame.
1016 if ((isVarArg) && (Subtarget->isABI_O32())) {
1017 if (StackPtr.getNode() == 0)
1018 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1020 // The stack pointer offset is relative to the caller stack frame.
1021 // Since the real stack size is unknown here, a negative SPOffset
1022 // is used so there's a way to adjust these offsets when the stack
1023 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1024 // used instead of a direct negative address (which is recorded to
1025 // be used on emitPrologue) to avoid mis-calc of the first stack
1026 // offset on PEI::calculateFrameObjectOffsets.
1027 // Arguments are always 32-bit.
1028 int FI = MFI->CreateFixedObject(4, 0);
1029 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1030 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1032 // emit ISD::STORE whichs stores the
1033 // parameter value to a stack Location
1034 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1037 } else { // VA.isRegLoc()
1040 assert(VA.isMemLoc());
1042 // The stack pointer offset is relative to the caller stack frame.
1043 // Since the real stack size is unknown here, a negative SPOffset
1044 // is used so there's a way to adjust these offsets when the stack
1045 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1046 // used instead of a direct negative address (which is recorded to
1047 // be used on emitPrologue) to avoid mis-calc of the first stack
1048 // offset on PEI::calculateFrameObjectOffsets.
1049 // Arguments are always 32-bit.
1050 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1051 int FI = MFI->CreateFixedObject(ArgSize, 0);
1052 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1053 (FirstStackArgLoc + VA.getLocMemOffset())));
1055 // Create load nodes to retrieve arguments from the stack
1056 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1057 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1061 // The mips ABIs for returning structs by value requires that we copy
1062 // the sret argument into $v0 for the return. Save the argument into
1063 // a virtual register so that we can access it from the return points.
1064 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1065 unsigned Reg = MipsFI->getSRetReturnReg();
1067 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1068 MipsFI->setSRetReturnReg(Reg);
1070 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1071 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1074 ArgValues.push_back(Root);
1076 // Return the new list of results.
1077 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1078 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1081 //===----------------------------------------------------------------------===//
1082 // Return Value Calling Convention Implementation
1083 //===----------------------------------------------------------------------===//
1085 SDValue MipsTargetLowering::
1086 LowerRET(SDValue Op, SelectionDAG &DAG)
1088 // CCValAssign - represent the assignment of
1089 // the return value to a location
1090 SmallVector<CCValAssign, 16> RVLocs;
1091 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1092 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1093 DebugLoc dl = Op.getDebugLoc();
1095 // CCState - Info about the registers and stack slot.
1096 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
1098 // Analize return values of ISD::RET
1099 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1101 // If this is the first return lowered for this function, add
1102 // the regs to the liveout set for the function.
1103 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1104 for (unsigned i = 0; i != RVLocs.size(); ++i)
1105 if (RVLocs[i].isRegLoc())
1106 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1109 // The chain is always operand #0
1110 SDValue Chain = Op.getOperand(0);
1113 // Copy the result values into the output registers.
1114 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1115 CCValAssign &VA = RVLocs[i];
1116 assert(VA.isRegLoc() && "Can only return in registers!");
1118 // ISD::RET => ret chain, (regnum1,val1), ...
1119 // So i*2+1 index only the regnums
1120 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1121 Op.getOperand(i*2+1), Flag);
1123 // guarantee that all emitted copies are
1124 // stuck together, avoiding something bad
1125 Flag = Chain.getValue(1);
1128 // The mips ABIs for returning structs by value requires that we copy
1129 // the sret argument into $v0 for the return. We saved the argument into
1130 // a virtual register in the entry block, so now we copy the value out
1132 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1133 MachineFunction &MF = DAG.getMachineFunction();
1134 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1135 unsigned Reg = MipsFI->getSRetReturnReg();
1138 assert(0 && "sret virtual register not created in the entry block");
1139 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1141 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1142 Flag = Chain.getValue(1);
1145 // Return on Mips is always a "jr $ra"
1147 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1148 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1150 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1151 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1154 //===----------------------------------------------------------------------===//
1155 // Mips Inline Assembly Support
1156 //===----------------------------------------------------------------------===//
1158 /// getConstraintType - Given a constraint letter, return the type of
1159 /// constraint it is for this target.
1160 MipsTargetLowering::ConstraintType MipsTargetLowering::
1161 getConstraintType(const std::string &Constraint) const
1163 // Mips specific constrainy
1164 // GCC config/mips/constraints.md
1166 // 'd' : An address register. Equivalent to r
1167 // unless generating MIPS16 code.
1168 // 'y' : Equivalent to r; retained for
1169 // backwards compatibility.
1170 // 'f' : Floating Point registers.
1171 if (Constraint.size() == 1) {
1172 switch (Constraint[0]) {
1177 return C_RegisterClass;
1181 return TargetLowering::getConstraintType(Constraint);
1184 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1185 /// return a list of registers that can be used to satisfy the constraint.
1186 /// This should only be used for C_RegisterClass constraints.
1187 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1188 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1190 if (Constraint.size() == 1) {
1191 switch (Constraint[0]) {
1193 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1196 return std::make_pair(0U, Mips::FGR32RegisterClass);
1198 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1199 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1202 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1205 /// Given a register class constraint, like 'r', if this corresponds directly
1206 /// to an LLVM register class, return a register of 0 and the register class
1208 std::vector<unsigned> MipsTargetLowering::
1209 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1212 if (Constraint.size() != 1)
1213 return std::vector<unsigned>();
1215 switch (Constraint[0]) {
1218 // GCC Mips Constraint Letters
1221 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1222 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1223 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1227 if (VT == MVT::f32) {
1228 if (Subtarget->isSingleFloat())
1229 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1230 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1231 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1232 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1233 Mips::F30, Mips::F31, 0);
1235 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1236 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1237 Mips::F28, Mips::F30, 0);
1241 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1242 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1243 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1244 Mips::D14, Mips::D15, 0);
1246 return std::vector<unsigned>();
1250 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1251 // The Mips target isn't yet aware of offsets.