1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::CMov : return "MipsISD::CMov";
45 case MipsISD::SelectCC : return "MipsISD::SelectCC";
46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
48 case MipsISD::FPCmp : return "MipsISD::FPCmp";
49 case MipsISD::FPRound : return "MipsISD::FPRound";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM)
56 : TargetLowering(TM, new MipsTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
63 // JumpTable targets must use GOT when using PIC_
64 setUsesGlobalOffsetTable(true);
66 // Set up the register classes
67 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
68 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
70 // When dealing with single precision only, use libcalls
71 if (!Subtarget->isSingleFloat())
72 if (!Subtarget->isFP64bit())
73 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
75 // Load extented operations for i1 types must be promoted
76 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
80 // MIPS doesn't have extending float->double load/store
81 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
82 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
84 // Used by legalize types to correctly generate the setcc result.
85 // Without this, every float setcc comes with a AND/OR with the result,
86 // we don't want this, since the fpcmp result goes to a flag register,
87 // which is used implicitly by brcond and select operations.
88 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
90 // Mips Custom Operations
91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
92 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
93 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
94 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
95 setOperationAction(ISD::SELECT, MVT::f32, Custom);
96 setOperationAction(ISD::SELECT, MVT::f64, Custom);
97 setOperationAction(ISD::SELECT, MVT::i32, Custom);
98 setOperationAction(ISD::SETCC, MVT::f32, Custom);
99 setOperationAction(ISD::SETCC, MVT::f64, Custom);
100 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
101 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
102 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
104 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
105 // with operands comming from setcc fp comparions. This is necessary since
106 // the result from these setcc are in a flag registers (FCR31).
107 setOperationAction(ISD::AND, MVT::i32, Custom);
108 setOperationAction(ISD::OR, MVT::i32, Custom);
110 // Operations not directly supported by Mips.
111 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
112 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
115 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
117 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
118 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
119 setOperationAction(ISD::ROTL, MVT::i32, Expand);
120 setOperationAction(ISD::ROTR, MVT::i32, Expand);
121 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
122 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
125 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
126 setOperationAction(ISD::FSIN, MVT::f32, Expand);
127 setOperationAction(ISD::FCOS, MVT::f32, Expand);
128 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
129 setOperationAction(ISD::FPOW, MVT::f32, Expand);
130 setOperationAction(ISD::FLOG, MVT::f32, Expand);
131 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
132 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
133 setOperationAction(ISD::FEXP, MVT::f32, Expand);
135 // We don't have line number support yet.
136 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
137 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
138 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
139 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
141 // Use the default for now
142 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
143 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
144 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
146 if (Subtarget->isSingleFloat())
147 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
149 if (!Subtarget->hasSEInReg()) {
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
154 if (!Subtarget->hasBitCount())
155 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
157 if (!Subtarget->hasSwap())
158 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
160 setStackPointerRegisterToSaveRestore(Mips::SP);
161 computeRegisterProperties();
164 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
168 /// getFunctionAlignment - Return the Log2 alignment of this function.
169 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
173 SDValue MipsTargetLowering::
174 LowerOperation(SDValue Op, SelectionDAG &DAG)
176 switch (Op.getOpcode())
178 case ISD::AND: return LowerANDOR(Op, DAG);
179 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
180 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
181 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
182 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
183 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
184 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
185 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
186 case ISD::OR: return LowerANDOR(Op, DAG);
187 case ISD::SELECT: return LowerSELECT(Op, DAG);
188 case ISD::SETCC: return LowerSETCC(Op, DAG);
193 //===----------------------------------------------------------------------===//
194 // Lower helper functions
195 //===----------------------------------------------------------------------===//
197 // AddLiveIn - This helper function adds the specified physical register to the
198 // MachineFunction as a live in value. It also creates a corresponding
199 // virtual register for it.
201 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
203 assert(RC->contains(PReg) && "Not the correct regclass!");
204 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
205 MF.getRegInfo().addLiveIn(PReg, VReg);
209 // Get fp branch code (not opcode) from condition code.
210 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
211 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
212 return Mips::BRANCH_T;
214 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
215 return Mips::BRANCH_F;
217 return Mips::BRANCH_INVALID;
220 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
223 llvm_unreachable("Unknown branch code");
224 case Mips::BRANCH_T : return Mips::BC1T;
225 case Mips::BRANCH_F : return Mips::BC1F;
226 case Mips::BRANCH_TL : return Mips::BC1TL;
227 case Mips::BRANCH_FL : return Mips::BC1FL;
231 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
233 default: llvm_unreachable("Unknown fp condition code!");
235 case ISD::SETOEQ: return Mips::FCOND_EQ;
236 case ISD::SETUNE: return Mips::FCOND_OGL;
238 case ISD::SETOLT: return Mips::FCOND_OLT;
240 case ISD::SETOGT: return Mips::FCOND_OGT;
242 case ISD::SETOLE: return Mips::FCOND_OLE;
244 case ISD::SETOGE: return Mips::FCOND_OGE;
245 case ISD::SETULT: return Mips::FCOND_ULT;
246 case ISD::SETULE: return Mips::FCOND_ULE;
247 case ISD::SETUGT: return Mips::FCOND_UGT;
248 case ISD::SETUGE: return Mips::FCOND_UGE;
249 case ISD::SETUO: return Mips::FCOND_UN;
250 case ISD::SETO: return Mips::FCOND_OR;
252 case ISD::SETONE: return Mips::FCOND_NEQ;
253 case ISD::SETUEQ: return Mips::FCOND_UEQ;
258 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *BB,
260 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
261 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
262 bool isFPCmp = false;
263 DebugLoc dl = MI->getDebugLoc();
265 switch (MI->getOpcode()) {
266 default: assert(false && "Unexpected instr type to insert");
267 case Mips::Select_FCC:
268 case Mips::Select_FCC_S32:
269 case Mips::Select_FCC_D32:
270 isFPCmp = true; // FALL THROUGH
271 case Mips::Select_CC:
272 case Mips::Select_CC_S32:
273 case Mips::Select_CC_D32: {
274 // To "insert" a SELECT_CC instruction, we actually have to insert the
275 // diamond control-flow pattern. The incoming instruction knows the
276 // destination vreg to set, the condition code register to branch on, the
277 // true/false values to select between, and a branch opcode to use.
278 const BasicBlock *LLVM_BB = BB->getBasicBlock();
279 MachineFunction::iterator It = BB;
286 // bNE r1, r0, copy1MBB
287 // fallthrough --> copy0MBB
288 MachineBasicBlock *thisMBB = BB;
289 MachineFunction *F = BB->getParent();
290 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
291 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
293 // Emit the right instruction according to the type of the operands compared
295 // Find the condiction code present in the setcc operation.
296 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
297 // Get the branch opcode from the branch code.
298 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
299 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
301 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
302 .addReg(Mips::ZERO).addMBB(sinkMBB);
304 F->insert(It, copy0MBB);
305 F->insert(It, sinkMBB);
306 // Update machine-CFG edges by first adding all successors of the current
307 // block to the new block which will contain the Phi node for the select.
308 // Also inform sdisel of the edge changes.
309 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
310 e = BB->succ_end(); i != e; ++i) {
311 EM->insert(std::make_pair(*i, sinkMBB));
312 sinkMBB->addSuccessor(*i);
314 // Next, remove all successors of the current block, and add the true
315 // and fallthrough blocks as its successors.
316 while(!BB->succ_empty())
317 BB->removeSuccessor(BB->succ_begin());
318 BB->addSuccessor(copy0MBB);
319 BB->addSuccessor(sinkMBB);
323 // # fallthrough to sinkMBB
326 // Update machine-CFG edges
327 BB->addSuccessor(sinkMBB);
330 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
333 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
334 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
335 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
337 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
343 //===----------------------------------------------------------------------===//
344 // Misc Lower Operation implementation
345 //===----------------------------------------------------------------------===//
347 SDValue MipsTargetLowering::
348 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
350 if (!Subtarget->isMips1())
353 MachineFunction &MF = DAG.getMachineFunction();
354 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
356 SDValue Chain = DAG.getEntryNode();
357 DebugLoc dl = Op.getDebugLoc();
358 SDValue Src = Op.getOperand(0);
360 // Set the condition register
361 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
362 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
363 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
365 SDValue Cst = DAG.getConstant(3, MVT::i32);
366 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
367 Cst = DAG.getConstant(2, MVT::i32);
368 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
370 SDValue InFlag(0, 0);
371 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
373 // Emit the round instruction and bit convert to integer
374 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
375 Src, CondReg.getValue(1));
376 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
380 SDValue MipsTargetLowering::
381 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
383 SDValue Chain = Op.getOperand(0);
384 SDValue Size = Op.getOperand(1);
385 DebugLoc dl = Op.getDebugLoc();
387 // Get a reference from Mips stack pointer
388 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
390 // Subtract the dynamic size from the actual stack size to
391 // obtain the new stack size.
392 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
394 // The Sub result contains the new stack start address, so it
395 // must be placed in the stack pointer register.
396 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
398 // This node always has two return values: a new stack pointer
400 SDValue Ops[2] = { Sub, Chain };
401 return DAG.getMergeValues(Ops, 2, dl);
404 SDValue MipsTargetLowering::
405 LowerANDOR(SDValue Op, SelectionDAG &DAG)
407 SDValue LHS = Op.getOperand(0);
408 SDValue RHS = Op.getOperand(1);
409 DebugLoc dl = Op.getDebugLoc();
411 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
414 SDValue True = DAG.getConstant(1, MVT::i32);
415 SDValue False = DAG.getConstant(0, MVT::i32);
417 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
418 LHS, True, False, LHS.getOperand(2));
419 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
420 RHS, True, False, RHS.getOperand(2));
422 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
425 SDValue MipsTargetLowering::
426 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
428 // The first operand is the chain, the second is the condition, the third is
429 // the block to branch to if the condition is true.
430 SDValue Chain = Op.getOperand(0);
431 SDValue Dest = Op.getOperand(2);
432 DebugLoc dl = Op.getDebugLoc();
434 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
437 SDValue CondRes = Op.getOperand(1);
438 SDValue CCNode = CondRes.getOperand(2);
440 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
441 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
443 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
447 SDValue MipsTargetLowering::
448 LowerSETCC(SDValue Op, SelectionDAG &DAG)
450 // The operands to this are the left and right operands to compare (ops #0,
451 // and #1) and the condition code to compare them with (op #2) as a
453 SDValue LHS = Op.getOperand(0);
454 SDValue RHS = Op.getOperand(1);
455 DebugLoc dl = Op.getDebugLoc();
457 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
459 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
460 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
463 SDValue MipsTargetLowering::
464 LowerSELECT(SDValue Op, SelectionDAG &DAG)
466 SDValue Cond = Op.getOperand(0);
467 SDValue True = Op.getOperand(1);
468 SDValue False = Op.getOperand(2);
469 DebugLoc dl = Op.getDebugLoc();
471 // if the incomming condition comes from a integer compare, the select
472 // operation must be SelectCC or a conditional move if the subtarget
474 if (Cond.getOpcode() != MipsISD::FPCmp) {
475 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
477 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
481 // if the incomming condition comes from fpcmp, the select
482 // operation must use FPSelectCC.
483 SDValue CCNode = Cond.getOperand(2);
484 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
485 Cond, True, False, CCNode);
488 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
489 // FIXME there isn't actually debug info here
490 DebugLoc dl = Op.getDebugLoc();
491 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
493 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
494 SDVTList VTs = DAG.getVTList(MVT::i32);
496 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
498 // %gp_rel relocation
499 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
500 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
502 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
503 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
504 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
506 // %hi/%lo relocation
507 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
508 MipsII::MO_ABS_HILO);
509 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
510 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
511 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
514 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
516 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
517 DAG.getEntryNode(), GA, NULL, 0);
518 // On functions and global targets not internal linked only
519 // a load from got/GP is necessary for PIC to work.
520 if (!GV->hasLocalLinkage() || isa<Function>(GV))
522 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
523 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
526 llvm_unreachable("Dont know how to handle GlobalAddress");
530 SDValue MipsTargetLowering::
531 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
533 llvm_unreachable("TLS not implemented for MIPS.");
534 return SDValue(); // Not reached
537 SDValue MipsTargetLowering::
538 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
542 // FIXME there isn't actually debug info here
543 DebugLoc dl = Op.getDebugLoc();
544 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
545 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
547 EVT PtrVT = Op.getValueType();
548 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
550 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
553 SDValue Ops[] = { JTI };
554 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
555 } else // Emit Load from Global Pointer
556 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
558 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
559 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
564 SDValue MipsTargetLowering::
565 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
568 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
569 Constant *C = N->getConstVal();
570 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
571 MipsII::MO_ABS_HILO);
572 // FIXME there isn't actually debug info here
573 DebugLoc dl = Op.getDebugLoc();
576 // FIXME: we should reference the constant pool using small data sections,
577 // but the asm printer currently doens't support this feature without
578 // hacking it. This feature should come soon so we can uncomment the
580 //if (IsInSmallSection(C->getType())) {
581 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
582 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
583 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
584 //} else { // %hi/%lo relocation
585 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
586 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
587 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
593 //===----------------------------------------------------------------------===//
594 // Calling Convention Implementation
595 //===----------------------------------------------------------------------===//
597 #include "MipsGenCallingConv.inc"
599 //===----------------------------------------------------------------------===//
600 // TODO: Implement a generic logic using tblgen that can support this.
601 // Mips O32 ABI rules:
603 // i32 - Passed in A0, A1, A2, A3 and stack
604 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
605 // an argument. Otherwise, passed in A1, A2, A3 and stack.
606 // f64 - Only passed in two aliased f32 registers if no int reg has been used
607 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
608 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
610 //===----------------------------------------------------------------------===//
612 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
613 EVT LocVT, CCValAssign::LocInfo LocInfo,
614 ISD::ArgFlagsTy ArgFlags, CCState &State) {
616 static const unsigned IntRegsSize=4, FloatRegsSize=2;
618 static const unsigned IntRegs[] = {
619 Mips::A0, Mips::A1, Mips::A2, Mips::A3
621 static const unsigned F32Regs[] = {
624 static const unsigned F64Regs[] = {
629 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
630 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
632 // Promote i8 and i16
633 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
635 if (ArgFlags.isSExt())
636 LocInfo = CCValAssign::SExt;
637 else if (ArgFlags.isZExt())
638 LocInfo = CCValAssign::ZExt;
640 LocInfo = CCValAssign::AExt;
643 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
644 Reg = State.AllocateReg(IntRegs, IntRegsSize);
649 if (ValVT.isFloatingPoint() && !IntRegUsed) {
650 if (ValVT == MVT::f32)
651 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
653 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
656 if (ValVT == MVT::f64 && IntRegUsed) {
657 if (UnallocIntReg != IntRegsSize) {
658 // If we hit register A3 as the first not allocated, we must
659 // mark it as allocated (shadow) and use the stack instead.
660 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
662 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
663 State.AllocateReg(UnallocIntReg);
669 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
670 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
671 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
675 return false; // CC must always match
678 //===----------------------------------------------------------------------===//
679 // Call Calling Convention Implementation
680 //===----------------------------------------------------------------------===//
682 /// LowerCall - functions arguments are copied from virtual regs to
683 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
684 /// TODO: isVarArg, isTailCall.
686 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
687 CallingConv::ID CallConv, bool isVarArg,
689 const SmallVectorImpl<ISD::OutputArg> &Outs,
690 const SmallVectorImpl<ISD::InputArg> &Ins,
691 DebugLoc dl, SelectionDAG &DAG,
692 SmallVectorImpl<SDValue> &InVals) {
694 MachineFunction &MF = DAG.getMachineFunction();
695 MachineFrameInfo *MFI = MF.getFrameInfo();
696 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
698 // Analyze operands of the call, assigning locations to each operand.
699 SmallVector<CCValAssign, 16> ArgLocs;
700 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
703 // To meet O32 ABI, Mips must always allocate 16 bytes on
704 // the stack (even if less than 4 are used as arguments)
705 if (Subtarget->isABI_O32()) {
706 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
707 MFI->CreateFixedObject(VTsize, (VTsize*3));
708 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
710 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
712 // Get a count of how many bytes are to be pushed on the stack.
713 unsigned NumBytes = CCInfo.getNextStackOffset();
714 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
716 // With EABI is it possible to have 16 args on registers.
717 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
718 SmallVector<SDValue, 8> MemOpChains;
720 // First/LastArgStackLoc contains the first/last
721 // "at stack" argument location.
722 int LastArgStackLoc = 0;
723 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
725 // Walk the register/memloc assignments, inserting copies/loads.
726 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
727 SDValue Arg = Outs[i].Val;
728 CCValAssign &VA = ArgLocs[i];
730 // Promote the value if needed.
731 switch (VA.getLocInfo()) {
732 default: llvm_unreachable("Unknown loc info!");
733 case CCValAssign::Full:
734 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
735 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
736 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
737 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
738 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
739 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
740 DAG.getConstant(0, getPointerTy()));
741 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
742 DAG.getConstant(1, getPointerTy()));
743 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
744 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
749 case CCValAssign::SExt:
750 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
752 case CCValAssign::ZExt:
753 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
755 case CCValAssign::AExt:
756 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
760 // Arguments that can be passed on register must be kept at
763 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
767 // Register can't get to this point...
768 assert(VA.isMemLoc());
770 // Create the frame index object for this incoming parameter
771 // This guarantees that when allocating Local Area the firsts
772 // 16 bytes which are alwayes reserved won't be overwritten
773 // if O32 ABI is used. For EABI the first address is zero.
774 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
775 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
778 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
780 // emit ISD::STORE whichs stores the
781 // parameter value to a stack Location
782 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
785 // Transform all store nodes into one single node because all store
786 // nodes are independent of each other.
787 if (!MemOpChains.empty())
788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
789 &MemOpChains[0], MemOpChains.size());
791 // Build a sequence of copy-to-reg nodes chained together with token
792 // chain and flag operands which copy the outgoing args into registers.
793 // The InFlag in necessary since all emited instructions must be
796 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
797 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
798 RegsToPass[i].second, InFlag);
799 InFlag = Chain.getValue(1);
802 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
803 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
804 // node so that legalize doesn't hack it.
805 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
806 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
807 Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
808 getPointerTy(), 0, OpFlag);
809 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
810 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
811 getPointerTy(), OpFlag);
813 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
814 // = Chain, Callee, Reg#1, Reg#2, ...
816 // Returns a chain & a flag for retval copy to use.
817 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
818 SmallVector<SDValue, 8> Ops;
819 Ops.push_back(Chain);
820 Ops.push_back(Callee);
822 // Add argument registers to the end of the list so that they are
823 // known live into the call.
824 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
825 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
826 RegsToPass[i].second.getValueType()));
828 if (InFlag.getNode())
829 Ops.push_back(InFlag);
831 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
832 InFlag = Chain.getValue(1);
834 // Create the CALLSEQ_END node.
835 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
836 DAG.getIntPtrConstant(0, true), InFlag);
837 InFlag = Chain.getValue(1);
839 // Create a stack location to hold GP when PIC is used. This stack
840 // location is used on function prologue to save GP and also after all
841 // emited CALL's to restore GP.
843 // Function can have an arbitrary number of calls, so
844 // hold the LastArgStackLoc with the biggest offset.
846 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
847 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
848 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
849 // Create the frame index only once. SPOffset here can be anything
850 // (this will be fixed on processFunctionBeforeFrameFinalized)
851 if (MipsFI->getGPStackOffset() == -1) {
852 FI = MFI->CreateFixedObject(4, 0);
855 MipsFI->setGPStackOffset(LastArgStackLoc);
859 FI = MipsFI->getGPFI();
860 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
861 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
862 Chain = GPLoad.getValue(1);
863 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
864 GPLoad, SDValue(0,0));
865 InFlag = Chain.getValue(1);
868 // Handle result values, copying them out of physregs into vregs that we
870 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
871 Ins, dl, DAG, InVals);
874 /// LowerCallResult - Lower the result values of a call into the
875 /// appropriate copies out of appropriate physical registers.
877 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
878 CallingConv::ID CallConv, bool isVarArg,
879 const SmallVectorImpl<ISD::InputArg> &Ins,
880 DebugLoc dl, SelectionDAG &DAG,
881 SmallVectorImpl<SDValue> &InVals) {
883 // Assign locations to each value returned by this call.
884 SmallVector<CCValAssign, 16> RVLocs;
885 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
886 RVLocs, *DAG.getContext());
888 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
890 // Copy all of the result registers out of their specified physreg.
891 for (unsigned i = 0; i != RVLocs.size(); ++i) {
892 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
893 RVLocs[i].getValVT(), InFlag).getValue(1);
894 InFlag = Chain.getValue(2);
895 InVals.push_back(Chain.getValue(0));
901 //===----------------------------------------------------------------------===//
902 // Formal Arguments Calling Convention Implementation
903 //===----------------------------------------------------------------------===//
905 /// LowerFormalArguments - transform physical registers into
906 /// virtual registers and generate load operations for
907 /// arguments places on the stack.
910 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
911 CallingConv::ID CallConv, bool isVarArg,
912 const SmallVectorImpl<ISD::InputArg>
914 DebugLoc dl, SelectionDAG &DAG,
915 SmallVectorImpl<SDValue> &InVals) {
917 MachineFunction &MF = DAG.getMachineFunction();
918 MachineFrameInfo *MFI = MF.getFrameInfo();
919 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
921 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
923 // Assign locations to all of the incoming arguments.
924 SmallVector<CCValAssign, 16> ArgLocs;
925 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
926 ArgLocs, *DAG.getContext());
928 if (Subtarget->isABI_O32())
929 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
931 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
935 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
938 CCValAssign &VA = ArgLocs[i];
940 // Arguments stored on registers
942 EVT RegVT = VA.getLocVT();
943 TargetRegisterClass *RC = 0;
945 if (RegVT == MVT::i32)
946 RC = Mips::CPURegsRegisterClass;
947 else if (RegVT == MVT::f32)
948 RC = Mips::FGR32RegisterClass;
949 else if (RegVT == MVT::f64) {
950 if (!Subtarget->isSingleFloat())
951 RC = Mips::AFGR64RegisterClass;
953 llvm_unreachable("RegVT not supported by LowerFormalArguments Lowering");
955 // Transform the arguments stored on
956 // physical registers into virtual ones
957 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
958 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
960 // If this is an 8 or 16-bit value, it has been passed promoted
961 // to 32 bits. Insert an assert[sz]ext to capture this, then
962 // truncate to the right size.
963 if (VA.getLocInfo() != CCValAssign::Full) {
965 if (VA.getLocInfo() == CCValAssign::SExt)
966 Opcode = ISD::AssertSext;
967 else if (VA.getLocInfo() == CCValAssign::ZExt)
968 Opcode = ISD::AssertZext;
970 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
971 DAG.getValueType(VA.getValVT()));
972 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
975 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
976 if (Subtarget->isABI_O32()) {
977 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
978 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
979 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
980 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
981 VA.getLocReg()+1, RC);
982 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
983 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
984 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
985 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
989 InVals.push_back(ArgValue);
991 // To meet ABI, when VARARGS are passed on registers, the registers
992 // must have their values written to the caller stack frame.
993 if ((isVarArg) && (Subtarget->isABI_O32())) {
994 if (StackPtr.getNode() == 0)
995 StackPtr = DAG.getRegister(StackReg, getPointerTy());
997 // The stack pointer offset is relative to the caller stack frame.
998 // Since the real stack size is unknown here, a negative SPOffset
999 // is used so there's a way to adjust these offsets when the stack
1000 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1001 // used instead of a direct negative address (which is recorded to
1002 // be used on emitPrologue) to avoid mis-calc of the first stack
1003 // offset on PEI::calculateFrameObjectOffsets.
1004 // Arguments are always 32-bit.
1005 int FI = MFI->CreateFixedObject(4, 0);
1006 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1007 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1009 // emit ISD::STORE whichs stores the
1010 // parameter value to a stack Location
1011 InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1014 } else { // VA.isRegLoc()
1017 assert(VA.isMemLoc());
1019 // The stack pointer offset is relative to the caller stack frame.
1020 // Since the real stack size is unknown here, a negative SPOffset
1021 // is used so there's a way to adjust these offsets when the stack
1022 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1023 // used instead of a direct negative address (which is recorded to
1024 // be used on emitPrologue) to avoid mis-calc of the first stack
1025 // offset on PEI::calculateFrameObjectOffsets.
1026 // Arguments are always 32-bit.
1027 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1028 int FI = MFI->CreateFixedObject(ArgSize, 0);
1029 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1030 (FirstStackArgLoc + VA.getLocMemOffset())));
1032 // Create load nodes to retrieve arguments from the stack
1033 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1034 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1038 // The mips ABIs for returning structs by value requires that we copy
1039 // the sret argument into $v0 for the return. Save the argument into
1040 // a virtual register so that we can access it from the return points.
1041 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1042 unsigned Reg = MipsFI->getSRetReturnReg();
1044 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1045 MipsFI->setSRetReturnReg(Reg);
1047 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1054 //===----------------------------------------------------------------------===//
1055 // Return Value Calling Convention Implementation
1056 //===----------------------------------------------------------------------===//
1059 MipsTargetLowering::LowerReturn(SDValue Chain,
1060 CallingConv::ID CallConv, bool isVarArg,
1061 const SmallVectorImpl<ISD::OutputArg> &Outs,
1062 DebugLoc dl, SelectionDAG &DAG) {
1064 // CCValAssign - represent the assignment of
1065 // the return value to a location
1066 SmallVector<CCValAssign, 16> RVLocs;
1068 // CCState - Info about the registers and stack slot.
1069 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1070 RVLocs, *DAG.getContext());
1072 // Analize return values.
1073 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1075 // If this is the first return lowered for this function, add
1076 // the regs to the liveout set for the function.
1077 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1078 for (unsigned i = 0; i != RVLocs.size(); ++i)
1079 if (RVLocs[i].isRegLoc())
1080 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1085 // Copy the result values into the output registers.
1086 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1087 CCValAssign &VA = RVLocs[i];
1088 assert(VA.isRegLoc() && "Can only return in registers!");
1090 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1093 // guarantee that all emitted copies are
1094 // stuck together, avoiding something bad
1095 Flag = Chain.getValue(1);
1098 // The mips ABIs for returning structs by value requires that we copy
1099 // the sret argument into $v0 for the return. We saved the argument into
1100 // a virtual register in the entry block, so now we copy the value out
1102 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1103 MachineFunction &MF = DAG.getMachineFunction();
1104 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1105 unsigned Reg = MipsFI->getSRetReturnReg();
1108 llvm_unreachable("sret virtual register not created in the entry block");
1109 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1111 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1112 Flag = Chain.getValue(1);
1115 // Return on Mips is always a "jr $ra"
1117 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1118 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1120 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1121 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1124 //===----------------------------------------------------------------------===//
1125 // Mips Inline Assembly Support
1126 //===----------------------------------------------------------------------===//
1128 /// getConstraintType - Given a constraint letter, return the type of
1129 /// constraint it is for this target.
1130 MipsTargetLowering::ConstraintType MipsTargetLowering::
1131 getConstraintType(const std::string &Constraint) const
1133 // Mips specific constrainy
1134 // GCC config/mips/constraints.md
1136 // 'd' : An address register. Equivalent to r
1137 // unless generating MIPS16 code.
1138 // 'y' : Equivalent to r; retained for
1139 // backwards compatibility.
1140 // 'f' : Floating Point registers.
1141 if (Constraint.size() == 1) {
1142 switch (Constraint[0]) {
1147 return C_RegisterClass;
1151 return TargetLowering::getConstraintType(Constraint);
1154 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1155 /// return a list of registers that can be used to satisfy the constraint.
1156 /// This should only be used for C_RegisterClass constraints.
1157 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1158 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1160 if (Constraint.size() == 1) {
1161 switch (Constraint[0]) {
1163 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1166 return std::make_pair(0U, Mips::FGR32RegisterClass);
1168 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1169 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1172 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1175 /// Given a register class constraint, like 'r', if this corresponds directly
1176 /// to an LLVM register class, return a register of 0 and the register class
1178 std::vector<unsigned> MipsTargetLowering::
1179 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1182 if (Constraint.size() != 1)
1183 return std::vector<unsigned>();
1185 switch (Constraint[0]) {
1188 // GCC Mips Constraint Letters
1191 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1192 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1193 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1197 if (VT == MVT::f32) {
1198 if (Subtarget->isSingleFloat())
1199 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1200 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1201 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1202 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1203 Mips::F30, Mips::F31, 0);
1205 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1206 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1207 Mips::F28, Mips::F30, 0);
1211 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1212 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1213 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1214 Mips::D14, Mips::D15, 0);
1216 return std::vector<unsigned>();
1220 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1221 // The Mips target isn't yet aware of offsets.
1225 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm) const {
1226 return Imm.isZero();