1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NumTailCalls, "Number of tail calls");
44 LargeGOT("mxgot", cl::Hidden,
45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
48 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
49 cl::desc("MIPS: Don't trap on integer division by zero."),
52 static const uint16_t O32IntRegs[4] = {
53 Mips::A0, Mips::A1, Mips::A2, Mips::A3
56 static const uint16_t Mips64IntRegs[8] = {
57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
61 static const uint16_t Mips64DPRegs[8] = {
62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
66 // If I is a shifted mask, set the size (Size) and the first bit of the
67 // mask (Pos), and return true.
68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70 if (!isShiftedMask_64(I))
73 Size = CountPopulation_64(I);
74 Pos = countTrailingZeros(I);
78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
83 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
84 EVT Ty = Op.getValueType();
86 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
87 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0,
89 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
90 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
91 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
92 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
93 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
94 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
95 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
96 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
97 N->getOffset(), Flag);
99 llvm_unreachable("Unexpected node type.");
103 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
105 EVT Ty = Op.getValueType();
106 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
107 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
108 return DAG.getNode(ISD::ADD, DL, Ty,
109 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
110 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
113 SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG,
114 bool HasMips64) const {
116 EVT Ty = Op.getValueType();
117 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
118 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
119 getTargetNode(Op, DAG, GOTFlag));
120 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
121 MachinePointerInfo::getGOT(), false, false, false,
123 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
124 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
125 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
128 SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG,
129 unsigned Flag) const {
131 EVT Ty = Op.getValueType();
132 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
133 getTargetNode(Op, DAG, Flag));
134 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
135 MachinePointerInfo::getGOT(), false, false, false, 0);
138 SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
140 unsigned LoFlag) const {
142 EVT Ty = Op.getValueType();
143 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
144 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
145 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
146 getTargetNode(Op, DAG, LoFlag));
147 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
148 MachinePointerInfo::getGOT(), false, false, false, 0);
151 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case MipsISD::JmpLink: return "MipsISD::JmpLink";
154 case MipsISD::TailCall: return "MipsISD::TailCall";
155 case MipsISD::Hi: return "MipsISD::Hi";
156 case MipsISD::Lo: return "MipsISD::Lo";
157 case MipsISD::GPRel: return "MipsISD::GPRel";
158 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
159 case MipsISD::Ret: return "MipsISD::Ret";
160 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
161 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
162 case MipsISD::FPCmp: return "MipsISD::FPCmp";
163 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
164 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
165 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
166 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI";
167 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI";
168 case MipsISD::Mult: return "MipsISD::Mult";
169 case MipsISD::Multu: return "MipsISD::Multu";
170 case MipsISD::MAdd: return "MipsISD::MAdd";
171 case MipsISD::MAddu: return "MipsISD::MAddu";
172 case MipsISD::MSub: return "MipsISD::MSub";
173 case MipsISD::MSubu: return "MipsISD::MSubu";
174 case MipsISD::DivRem: return "MipsISD::DivRem";
175 case MipsISD::DivRemU: return "MipsISD::DivRemU";
176 case MipsISD::DivRem16: return "MipsISD::DivRem16";
177 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
178 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
179 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
180 case MipsISD::Wrapper: return "MipsISD::Wrapper";
181 case MipsISD::Sync: return "MipsISD::Sync";
182 case MipsISD::Ext: return "MipsISD::Ext";
183 case MipsISD::Ins: return "MipsISD::Ins";
184 case MipsISD::LWL: return "MipsISD::LWL";
185 case MipsISD::LWR: return "MipsISD::LWR";
186 case MipsISD::SWL: return "MipsISD::SWL";
187 case MipsISD::SWR: return "MipsISD::SWR";
188 case MipsISD::LDL: return "MipsISD::LDL";
189 case MipsISD::LDR: return "MipsISD::LDR";
190 case MipsISD::SDL: return "MipsISD::SDL";
191 case MipsISD::SDR: return "MipsISD::SDR";
192 case MipsISD::EXTP: return "MipsISD::EXTP";
193 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
194 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
195 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
196 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
197 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
198 case MipsISD::SHILO: return "MipsISD::SHILO";
199 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
200 case MipsISD::MULT: return "MipsISD::MULT";
201 case MipsISD::MULTU: return "MipsISD::MULTU";
202 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
203 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
204 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
205 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
206 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
207 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
208 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
209 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
210 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
211 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
212 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
213 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
214 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
215 default: return NULL;
220 MipsTargetLowering(MipsTargetMachine &TM)
221 : TargetLowering(TM, new MipsTargetObjectFile()),
222 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
223 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
224 IsO32(Subtarget->isABI_O32()) {
225 // Mips does not have i1 type, so use i32 for
226 // setcc operations results (slt, sgt, ...).
227 setBooleanContents(ZeroOrOneBooleanContent);
228 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
230 // Load extented operations for i1 types must be promoted
231 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
232 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // MIPS doesn't have extending float->double load/store
236 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
237 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
239 // Used by legalize types to correctly generate the setcc result.
240 // Without this, every float setcc comes with a AND/OR with the result,
241 // we don't want this, since the fpcmp result goes to a flag register,
242 // which is used implicitly by brcond and select operations.
243 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
245 // Mips Custom Operations
246 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
247 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
248 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
249 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
250 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
251 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
252 setOperationAction(ISD::SELECT, MVT::f32, Custom);
253 setOperationAction(ISD::SELECT, MVT::f64, Custom);
254 setOperationAction(ISD::SELECT, MVT::i32, Custom);
255 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
256 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
257 setOperationAction(ISD::SETCC, MVT::f32, Custom);
258 setOperationAction(ISD::SETCC, MVT::f64, Custom);
259 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
260 setOperationAction(ISD::VASTART, MVT::Other, Custom);
261 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
262 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
265 if (!TM.Options.NoNaNsFPMath) {
266 setOperationAction(ISD::FABS, MVT::f32, Custom);
267 setOperationAction(ISD::FABS, MVT::f64, Custom);
271 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
272 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
273 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
274 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
275 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
276 setOperationAction(ISD::SELECT, MVT::i64, Custom);
277 setOperationAction(ISD::LOAD, MVT::i64, Custom);
278 setOperationAction(ISD::STORE, MVT::i64, Custom);
279 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
283 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
284 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
285 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
288 setOperationAction(ISD::ADD, MVT::i32, Custom);
290 setOperationAction(ISD::ADD, MVT::i64, Custom);
292 setOperationAction(ISD::SDIV, MVT::i32, Expand);
293 setOperationAction(ISD::SREM, MVT::i32, Expand);
294 setOperationAction(ISD::UDIV, MVT::i32, Expand);
295 setOperationAction(ISD::UREM, MVT::i32, Expand);
296 setOperationAction(ISD::SDIV, MVT::i64, Expand);
297 setOperationAction(ISD::SREM, MVT::i64, Expand);
298 setOperationAction(ISD::UDIV, MVT::i64, Expand);
299 setOperationAction(ISD::UREM, MVT::i64, Expand);
301 // Operations not directly supported by Mips.
302 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
303 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
304 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
305 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
306 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
307 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
308 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
309 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
310 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
312 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
313 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
314 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
315 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
316 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
317 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
318 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
319 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
320 setOperationAction(ISD::ROTL, MVT::i32, Expand);
321 setOperationAction(ISD::ROTL, MVT::i64, Expand);
322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
323 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
325 if (!Subtarget->hasMips32r2())
326 setOperationAction(ISD::ROTR, MVT::i32, Expand);
328 if (!Subtarget->hasMips64r2())
329 setOperationAction(ISD::ROTR, MVT::i64, Expand);
331 setOperationAction(ISD::FSIN, MVT::f32, Expand);
332 setOperationAction(ISD::FSIN, MVT::f64, Expand);
333 setOperationAction(ISD::FCOS, MVT::f32, Expand);
334 setOperationAction(ISD::FCOS, MVT::f64, Expand);
335 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
336 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
337 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
338 setOperationAction(ISD::FPOW, MVT::f32, Expand);
339 setOperationAction(ISD::FPOW, MVT::f64, Expand);
340 setOperationAction(ISD::FLOG, MVT::f32, Expand);
341 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
342 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
343 setOperationAction(ISD::FEXP, MVT::f32, Expand);
344 setOperationAction(ISD::FMA, MVT::f32, Expand);
345 setOperationAction(ISD::FMA, MVT::f64, Expand);
346 setOperationAction(ISD::FREM, MVT::f32, Expand);
347 setOperationAction(ISD::FREM, MVT::f64, Expand);
349 if (!TM.Options.NoNaNsFPMath) {
350 setOperationAction(ISD::FNEG, MVT::f32, Expand);
351 setOperationAction(ISD::FNEG, MVT::f64, Expand);
354 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
356 setOperationAction(ISD::VAARG, MVT::Other, Expand);
357 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
358 setOperationAction(ISD::VAEND, MVT::Other, Expand);
360 // Use the default for now
361 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
362 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
364 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
365 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
366 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
367 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
369 setInsertFencesForAtomic(true);
371 if (!Subtarget->hasSEInReg()) {
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
376 if (!Subtarget->hasBitCount()) {
377 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
381 if (!Subtarget->hasSwap()) {
382 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
383 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
387 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
388 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
389 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
390 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
393 setOperationAction(ISD::TRAP, MVT::Other, Legal);
395 setTargetDAGCombine(ISD::SDIVREM);
396 setTargetDAGCombine(ISD::UDIVREM);
397 setTargetDAGCombine(ISD::SELECT);
398 setTargetDAGCombine(ISD::AND);
399 setTargetDAGCombine(ISD::OR);
400 setTargetDAGCombine(ISD::ADD);
402 setMinFunctionAlignment(HasMips64 ? 3 : 2);
404 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
406 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
407 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
409 MaxStoresPerMemcpy = 16;
412 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
413 if (TM.getSubtargetImpl()->inMips16Mode())
414 return llvm::createMips16TargetLowering(TM);
416 return llvm::createMipsSETargetLowering(TM);
419 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
422 return VT.changeVectorElementTypeToInteger();
425 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
426 TargetLowering::DAGCombinerInfo &DCI,
427 const MipsSubtarget *Subtarget) {
428 if (DCI.isBeforeLegalizeOps())
431 EVT Ty = N->getValueType(0);
432 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
433 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
434 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
438 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
439 N->getOperand(0), N->getOperand(1));
440 SDValue InChain = DAG.getEntryNode();
441 SDValue InGlue = DivRem;
444 if (N->hasAnyUseOfValue(0)) {
445 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
447 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
448 InChain = CopyFromLo.getValue(1);
449 InGlue = CopyFromLo.getValue(2);
453 if (N->hasAnyUseOfValue(1)) {
454 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
456 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
462 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
464 default: llvm_unreachable("Unknown fp condition code!");
466 case ISD::SETOEQ: return Mips::FCOND_OEQ;
467 case ISD::SETUNE: return Mips::FCOND_UNE;
469 case ISD::SETOLT: return Mips::FCOND_OLT;
471 case ISD::SETOGT: return Mips::FCOND_OGT;
473 case ISD::SETOLE: return Mips::FCOND_OLE;
475 case ISD::SETOGE: return Mips::FCOND_OGE;
476 case ISD::SETULT: return Mips::FCOND_ULT;
477 case ISD::SETULE: return Mips::FCOND_ULE;
478 case ISD::SETUGT: return Mips::FCOND_UGT;
479 case ISD::SETUGE: return Mips::FCOND_UGE;
480 case ISD::SETUO: return Mips::FCOND_UN;
481 case ISD::SETO: return Mips::FCOND_OR;
483 case ISD::SETONE: return Mips::FCOND_ONE;
484 case ISD::SETUEQ: return Mips::FCOND_UEQ;
489 /// This function returns true if the floating point conditional branches and
490 /// conditional moves which use condition code CC should be inverted.
491 static bool invertFPCondCodeUser(Mips::CondCode CC) {
492 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
495 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
496 "Illegal Condition Code");
501 // Creates and returns an FPCmp node from a setcc node.
502 // Returns Op if setcc is not a floating point comparison.
503 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
504 // must be a SETCC node
505 if (Op.getOpcode() != ISD::SETCC)
508 SDValue LHS = Op.getOperand(0);
510 if (!LHS.getValueType().isFloatingPoint())
513 SDValue RHS = Op.getOperand(1);
516 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
517 // node if necessary.
518 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
520 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
521 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
524 // Creates and returns a CMovFPT/F node.
525 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
526 SDValue False, SDLoc DL) {
527 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
528 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
529 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
531 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
532 True.getValueType(), True, FCC0, False, Cond);
535 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
536 TargetLowering::DAGCombinerInfo &DCI,
537 const MipsSubtarget *Subtarget) {
538 if (DCI.isBeforeLegalizeOps())
541 SDValue SetCC = N->getOperand(0);
543 if ((SetCC.getOpcode() != ISD::SETCC) ||
544 !SetCC.getOperand(0).getValueType().isInteger())
547 SDValue False = N->getOperand(2);
548 EVT FalseTy = False.getValueType();
550 if (!FalseTy.isInteger())
553 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
555 if (!CN || CN->getZExtValue())
559 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
560 SDValue True = N->getOperand(1);
562 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
563 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
565 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
568 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
569 TargetLowering::DAGCombinerInfo &DCI,
570 const MipsSubtarget *Subtarget) {
571 // Pattern match EXT.
572 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
573 // => ext $dst, $src, size, pos
574 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
577 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
578 unsigned ShiftRightOpc = ShiftRight.getOpcode();
580 // Op's first operand must be a shift right.
581 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
584 // The second operand of the shift must be an immediate.
586 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
589 uint64_t Pos = CN->getZExtValue();
590 uint64_t SMPos, SMSize;
592 // Op's second operand must be a shifted mask.
593 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
594 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
597 // Return if the shifted mask does not start at bit 0 or the sum of its size
598 // and Pos exceeds the word's size.
599 EVT ValTy = N->getValueType(0);
600 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
603 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
604 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
605 DAG.getConstant(SMSize, MVT::i32));
608 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
609 TargetLowering::DAGCombinerInfo &DCI,
610 const MipsSubtarget *Subtarget) {
611 // Pattern match INS.
612 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
613 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
614 // => ins $dst, $src, size, pos, $src1
615 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
618 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
619 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
622 // See if Op's first operand matches (and $src1 , mask0).
623 if (And0.getOpcode() != ISD::AND)
626 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
627 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
630 // See if Op's second operand matches (and (shl $src, pos), mask1).
631 if (And1.getOpcode() != ISD::AND)
634 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
635 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
638 // The shift masks must have the same position and size.
639 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
642 SDValue Shl = And1.getOperand(0);
643 if (Shl.getOpcode() != ISD::SHL)
646 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
649 unsigned Shamt = CN->getZExtValue();
651 // Return if the shift amount and the first bit position of mask are not the
653 EVT ValTy = N->getValueType(0);
654 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
657 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
658 DAG.getConstant(SMPos0, MVT::i32),
659 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
662 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
663 TargetLowering::DAGCombinerInfo &DCI,
664 const MipsSubtarget *Subtarget) {
665 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
667 if (DCI.isBeforeLegalizeOps())
670 SDValue Add = N->getOperand(1);
672 if (Add.getOpcode() != ISD::ADD)
675 SDValue Lo = Add.getOperand(1);
677 if ((Lo.getOpcode() != MipsISD::Lo) ||
678 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
681 EVT ValTy = N->getValueType(0);
684 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
686 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
689 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
691 SelectionDAG &DAG = DCI.DAG;
692 unsigned Opc = N->getOpcode();
698 return performDivRemCombine(N, DAG, DCI, Subtarget);
700 return performSELECTCombine(N, DAG, DCI, Subtarget);
702 return performANDCombine(N, DAG, DCI, Subtarget);
704 return performORCombine(N, DAG, DCI, Subtarget);
706 return performADDCombine(N, DAG, DCI, Subtarget);
713 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
714 SmallVectorImpl<SDValue> &Results,
715 SelectionDAG &DAG) const {
716 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
718 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
719 Results.push_back(Res.getValue(I));
723 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
724 SmallVectorImpl<SDValue> &Results,
725 SelectionDAG &DAG) const {
726 return LowerOperationWrapper(N, Results, DAG);
729 SDValue MipsTargetLowering::
730 LowerOperation(SDValue Op, SelectionDAG &DAG) const
732 switch (Op.getOpcode())
734 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
735 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
736 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
737 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
738 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
739 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
740 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
741 case ISD::SELECT: return lowerSELECT(Op, DAG);
742 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
743 case ISD::SETCC: return lowerSETCC(Op, DAG);
744 case ISD::VASTART: return lowerVASTART(Op, DAG);
745 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
746 case ISD::FABS: return lowerFABS(Op, DAG);
747 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
748 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
749 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
750 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
751 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
752 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
753 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
754 case ISD::LOAD: return lowerLOAD(Op, DAG);
755 case ISD::STORE: return lowerSTORE(Op, DAG);
756 case ISD::ADD: return lowerADD(Op, DAG);
757 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
762 //===----------------------------------------------------------------------===//
763 // Lower helper functions
764 //===----------------------------------------------------------------------===//
766 // addLiveIn - This helper function adds the specified physical register to the
767 // MachineFunction as a live in value. It also creates a corresponding
768 // virtual register for it.
770 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
772 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
773 MF.getRegInfo().addLiveIn(PReg, VReg);
777 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
778 MachineBasicBlock &MBB,
779 const TargetInstrInfo &TII,
784 // Insert instruction "teq $divisor_reg, $zero, 7".
785 MachineBasicBlock::iterator I(MI);
786 MachineInstrBuilder MIB;
787 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
788 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
790 // Use the 32-bit sub-register if this is a 64-bit division.
792 MIB->getOperand(0).setSubReg(Mips::sub_32);
798 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
799 MachineBasicBlock *BB) const {
800 switch (MI->getOpcode()) {
802 llvm_unreachable("Unexpected instr type to insert");
803 case Mips::ATOMIC_LOAD_ADD_I8:
804 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
805 case Mips::ATOMIC_LOAD_ADD_I16:
806 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
807 case Mips::ATOMIC_LOAD_ADD_I32:
808 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
809 case Mips::ATOMIC_LOAD_ADD_I64:
810 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
812 case Mips::ATOMIC_LOAD_AND_I8:
813 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
814 case Mips::ATOMIC_LOAD_AND_I16:
815 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
816 case Mips::ATOMIC_LOAD_AND_I32:
817 return emitAtomicBinary(MI, BB, 4, Mips::AND);
818 case Mips::ATOMIC_LOAD_AND_I64:
819 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
821 case Mips::ATOMIC_LOAD_OR_I8:
822 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
823 case Mips::ATOMIC_LOAD_OR_I16:
824 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
825 case Mips::ATOMIC_LOAD_OR_I32:
826 return emitAtomicBinary(MI, BB, 4, Mips::OR);
827 case Mips::ATOMIC_LOAD_OR_I64:
828 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
830 case Mips::ATOMIC_LOAD_XOR_I8:
831 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
832 case Mips::ATOMIC_LOAD_XOR_I16:
833 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
834 case Mips::ATOMIC_LOAD_XOR_I32:
835 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
836 case Mips::ATOMIC_LOAD_XOR_I64:
837 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
839 case Mips::ATOMIC_LOAD_NAND_I8:
840 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
841 case Mips::ATOMIC_LOAD_NAND_I16:
842 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
843 case Mips::ATOMIC_LOAD_NAND_I32:
844 return emitAtomicBinary(MI, BB, 4, 0, true);
845 case Mips::ATOMIC_LOAD_NAND_I64:
846 return emitAtomicBinary(MI, BB, 8, 0, true);
848 case Mips::ATOMIC_LOAD_SUB_I8:
849 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
850 case Mips::ATOMIC_LOAD_SUB_I16:
851 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
852 case Mips::ATOMIC_LOAD_SUB_I32:
853 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
854 case Mips::ATOMIC_LOAD_SUB_I64:
855 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
857 case Mips::ATOMIC_SWAP_I8:
858 return emitAtomicBinaryPartword(MI, BB, 1, 0);
859 case Mips::ATOMIC_SWAP_I16:
860 return emitAtomicBinaryPartword(MI, BB, 2, 0);
861 case Mips::ATOMIC_SWAP_I32:
862 return emitAtomicBinary(MI, BB, 4, 0);
863 case Mips::ATOMIC_SWAP_I64:
864 return emitAtomicBinary(MI, BB, 8, 0);
866 case Mips::ATOMIC_CMP_SWAP_I8:
867 return emitAtomicCmpSwapPartword(MI, BB, 1);
868 case Mips::ATOMIC_CMP_SWAP_I16:
869 return emitAtomicCmpSwapPartword(MI, BB, 2);
870 case Mips::ATOMIC_CMP_SWAP_I32:
871 return emitAtomicCmpSwap(MI, BB, 4);
872 case Mips::ATOMIC_CMP_SWAP_I64:
873 return emitAtomicCmpSwap(MI, BB, 8);
874 case Mips::PseudoSDIV:
875 case Mips::PseudoUDIV:
876 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
877 case Mips::PseudoDSDIV:
878 case Mips::PseudoDUDIV:
879 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
883 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
884 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
886 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
887 unsigned Size, unsigned BinOpcode,
889 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
891 MachineFunction *MF = BB->getParent();
892 MachineRegisterInfo &RegInfo = MF->getRegInfo();
893 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
894 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
895 DebugLoc DL = MI->getDebugLoc();
896 unsigned LL, SC, AND, NOR, ZERO, BEQ;
911 ZERO = Mips::ZERO_64;
915 unsigned OldVal = MI->getOperand(0).getReg();
916 unsigned Ptr = MI->getOperand(1).getReg();
917 unsigned Incr = MI->getOperand(2).getReg();
919 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
920 unsigned AndRes = RegInfo.createVirtualRegister(RC);
921 unsigned Success = RegInfo.createVirtualRegister(RC);
923 // insert new blocks after the current block
924 const BasicBlock *LLVM_BB = BB->getBasicBlock();
925 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
926 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
927 MachineFunction::iterator It = BB;
929 MF->insert(It, loopMBB);
930 MF->insert(It, exitMBB);
932 // Transfer the remainder of BB and its successor edges to exitMBB.
933 exitMBB->splice(exitMBB->begin(), BB,
934 llvm::next(MachineBasicBlock::iterator(MI)),
936 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
940 // fallthrough --> loopMBB
941 BB->addSuccessor(loopMBB);
942 loopMBB->addSuccessor(loopMBB);
943 loopMBB->addSuccessor(exitMBB);
947 // <binop> storeval, oldval, incr
948 // sc success, storeval, 0(ptr)
949 // beq success, $0, loopMBB
951 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
953 // and andres, oldval, incr
954 // nor storeval, $0, andres
955 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
956 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
957 } else if (BinOpcode) {
958 // <binop> storeval, oldval, incr
959 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
963 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
964 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
966 MI->eraseFromParent(); // The instruction is gone now.
972 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
973 MachineBasicBlock *BB,
974 unsigned Size, unsigned BinOpcode,
976 assert((Size == 1 || Size == 2) &&
977 "Unsupported size for EmitAtomicBinaryPartial.");
979 MachineFunction *MF = BB->getParent();
980 MachineRegisterInfo &RegInfo = MF->getRegInfo();
981 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
982 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
983 DebugLoc DL = MI->getDebugLoc();
985 unsigned Dest = MI->getOperand(0).getReg();
986 unsigned Ptr = MI->getOperand(1).getReg();
987 unsigned Incr = MI->getOperand(2).getReg();
989 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
990 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
991 unsigned Mask = RegInfo.createVirtualRegister(RC);
992 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
993 unsigned NewVal = RegInfo.createVirtualRegister(RC);
994 unsigned OldVal = RegInfo.createVirtualRegister(RC);
995 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
996 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
997 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
998 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
999 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1000 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1001 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1002 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1003 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1004 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1005 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1006 unsigned Success = RegInfo.createVirtualRegister(RC);
1008 // insert new blocks after the current block
1009 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1010 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1011 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1012 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1013 MachineFunction::iterator It = BB;
1015 MF->insert(It, loopMBB);
1016 MF->insert(It, sinkMBB);
1017 MF->insert(It, exitMBB);
1019 // Transfer the remainder of BB and its successor edges to exitMBB.
1020 exitMBB->splice(exitMBB->begin(), BB,
1021 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1022 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1024 BB->addSuccessor(loopMBB);
1025 loopMBB->addSuccessor(loopMBB);
1026 loopMBB->addSuccessor(sinkMBB);
1027 sinkMBB->addSuccessor(exitMBB);
1030 // addiu masklsb2,$0,-4 # 0xfffffffc
1031 // and alignedaddr,ptr,masklsb2
1032 // andi ptrlsb2,ptr,3
1033 // sll shiftamt,ptrlsb2,3
1034 // ori maskupper,$0,255 # 0xff
1035 // sll mask,maskupper,shiftamt
1036 // nor mask2,$0,mask
1037 // sll incr2,incr,shiftamt
1039 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1040 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1041 .addReg(Mips::ZERO).addImm(-4);
1042 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1043 .addReg(Ptr).addReg(MaskLSB2);
1044 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1045 if (Subtarget->isLittle()) {
1046 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1048 unsigned Off = RegInfo.createVirtualRegister(RC);
1049 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1050 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1051 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1053 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1054 .addReg(Mips::ZERO).addImm(MaskImm);
1055 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1056 .addReg(MaskUpper).addReg(ShiftAmt);
1057 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1058 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1060 // atomic.load.binop
1062 // ll oldval,0(alignedaddr)
1063 // binop binopres,oldval,incr2
1064 // and newval,binopres,mask
1065 // and maskedoldval0,oldval,mask2
1066 // or storeval,maskedoldval0,newval
1067 // sc success,storeval,0(alignedaddr)
1068 // beq success,$0,loopMBB
1072 // ll oldval,0(alignedaddr)
1073 // and newval,incr2,mask
1074 // and maskedoldval0,oldval,mask2
1075 // or storeval,maskedoldval0,newval
1076 // sc success,storeval,0(alignedaddr)
1077 // beq success,$0,loopMBB
1080 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1082 // and andres, oldval, incr2
1083 // nor binopres, $0, andres
1084 // and newval, binopres, mask
1085 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1086 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1087 .addReg(Mips::ZERO).addReg(AndRes);
1088 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1089 } else if (BinOpcode) {
1090 // <binop> binopres, oldval, incr2
1091 // and newval, binopres, mask
1092 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1093 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1094 } else {// atomic.swap
1095 // and newval, incr2, mask
1096 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1099 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1100 .addReg(OldVal).addReg(Mask2);
1101 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1102 .addReg(MaskedOldVal0).addReg(NewVal);
1103 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1104 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1105 BuildMI(BB, DL, TII->get(Mips::BEQ))
1106 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1109 // and maskedoldval1,oldval,mask
1110 // srl srlres,maskedoldval1,shiftamt
1111 // sll sllres,srlres,24
1112 // sra dest,sllres,24
1114 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1116 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1117 .addReg(OldVal).addReg(Mask);
1118 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1119 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1120 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1121 .addReg(SrlRes).addImm(ShiftImm);
1122 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1123 .addReg(SllRes).addImm(ShiftImm);
1125 MI->eraseFromParent(); // The instruction is gone now.
1131 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1132 MachineBasicBlock *BB,
1133 unsigned Size) const {
1134 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1136 MachineFunction *MF = BB->getParent();
1137 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1138 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1139 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1140 DebugLoc DL = MI->getDebugLoc();
1141 unsigned LL, SC, ZERO, BNE, BEQ;
1153 ZERO = Mips::ZERO_64;
1158 unsigned Dest = MI->getOperand(0).getReg();
1159 unsigned Ptr = MI->getOperand(1).getReg();
1160 unsigned OldVal = MI->getOperand(2).getReg();
1161 unsigned NewVal = MI->getOperand(3).getReg();
1163 unsigned Success = RegInfo.createVirtualRegister(RC);
1165 // insert new blocks after the current block
1166 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1167 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1168 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1169 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1170 MachineFunction::iterator It = BB;
1172 MF->insert(It, loop1MBB);
1173 MF->insert(It, loop2MBB);
1174 MF->insert(It, exitMBB);
1176 // Transfer the remainder of BB and its successor edges to exitMBB.
1177 exitMBB->splice(exitMBB->begin(), BB,
1178 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1179 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1183 // fallthrough --> loop1MBB
1184 BB->addSuccessor(loop1MBB);
1185 loop1MBB->addSuccessor(exitMBB);
1186 loop1MBB->addSuccessor(loop2MBB);
1187 loop2MBB->addSuccessor(loop1MBB);
1188 loop2MBB->addSuccessor(exitMBB);
1192 // bne dest, oldval, exitMBB
1194 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1195 BuildMI(BB, DL, TII->get(BNE))
1196 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1199 // sc success, newval, 0(ptr)
1200 // beq success, $0, loop1MBB
1202 BuildMI(BB, DL, TII->get(SC), Success)
1203 .addReg(NewVal).addReg(Ptr).addImm(0);
1204 BuildMI(BB, DL, TII->get(BEQ))
1205 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1207 MI->eraseFromParent(); // The instruction is gone now.
1213 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1214 MachineBasicBlock *BB,
1215 unsigned Size) const {
1216 assert((Size == 1 || Size == 2) &&
1217 "Unsupported size for EmitAtomicCmpSwapPartial.");
1219 MachineFunction *MF = BB->getParent();
1220 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1221 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1222 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1223 DebugLoc DL = MI->getDebugLoc();
1225 unsigned Dest = MI->getOperand(0).getReg();
1226 unsigned Ptr = MI->getOperand(1).getReg();
1227 unsigned CmpVal = MI->getOperand(2).getReg();
1228 unsigned NewVal = MI->getOperand(3).getReg();
1230 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1231 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1232 unsigned Mask = RegInfo.createVirtualRegister(RC);
1233 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1234 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1235 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1236 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1237 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1238 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1239 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1240 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1241 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1242 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1243 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1244 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1245 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1246 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1247 unsigned Success = RegInfo.createVirtualRegister(RC);
1249 // insert new blocks after the current block
1250 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1251 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1252 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1253 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1254 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1255 MachineFunction::iterator It = BB;
1257 MF->insert(It, loop1MBB);
1258 MF->insert(It, loop2MBB);
1259 MF->insert(It, sinkMBB);
1260 MF->insert(It, exitMBB);
1262 // Transfer the remainder of BB and its successor edges to exitMBB.
1263 exitMBB->splice(exitMBB->begin(), BB,
1264 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1265 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1267 BB->addSuccessor(loop1MBB);
1268 loop1MBB->addSuccessor(sinkMBB);
1269 loop1MBB->addSuccessor(loop2MBB);
1270 loop2MBB->addSuccessor(loop1MBB);
1271 loop2MBB->addSuccessor(sinkMBB);
1272 sinkMBB->addSuccessor(exitMBB);
1274 // FIXME: computation of newval2 can be moved to loop2MBB.
1276 // addiu masklsb2,$0,-4 # 0xfffffffc
1277 // and alignedaddr,ptr,masklsb2
1278 // andi ptrlsb2,ptr,3
1279 // sll shiftamt,ptrlsb2,3
1280 // ori maskupper,$0,255 # 0xff
1281 // sll mask,maskupper,shiftamt
1282 // nor mask2,$0,mask
1283 // andi maskedcmpval,cmpval,255
1284 // sll shiftedcmpval,maskedcmpval,shiftamt
1285 // andi maskednewval,newval,255
1286 // sll shiftednewval,maskednewval,shiftamt
1287 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1288 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1289 .addReg(Mips::ZERO).addImm(-4);
1290 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1291 .addReg(Ptr).addReg(MaskLSB2);
1292 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1293 if (Subtarget->isLittle()) {
1294 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1296 unsigned Off = RegInfo.createVirtualRegister(RC);
1297 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1298 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1299 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1301 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1302 .addReg(Mips::ZERO).addImm(MaskImm);
1303 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1304 .addReg(MaskUpper).addReg(ShiftAmt);
1305 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1306 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1307 .addReg(CmpVal).addImm(MaskImm);
1308 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1309 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1310 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1311 .addReg(NewVal).addImm(MaskImm);
1312 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1313 .addReg(MaskedNewVal).addReg(ShiftAmt);
1316 // ll oldval,0(alginedaddr)
1317 // and maskedoldval0,oldval,mask
1318 // bne maskedoldval0,shiftedcmpval,sinkMBB
1320 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1321 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1322 .addReg(OldVal).addReg(Mask);
1323 BuildMI(BB, DL, TII->get(Mips::BNE))
1324 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1327 // and maskedoldval1,oldval,mask2
1328 // or storeval,maskedoldval1,shiftednewval
1329 // sc success,storeval,0(alignedaddr)
1330 // beq success,$0,loop1MBB
1332 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1333 .addReg(OldVal).addReg(Mask2);
1334 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1335 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1336 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1337 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1338 BuildMI(BB, DL, TII->get(Mips::BEQ))
1339 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1342 // srl srlres,maskedoldval0,shiftamt
1343 // sll sllres,srlres,24
1344 // sra dest,sllres,24
1346 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1348 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1349 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1350 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1351 .addReg(SrlRes).addImm(ShiftImm);
1352 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1353 .addReg(SllRes).addImm(ShiftImm);
1355 MI->eraseFromParent(); // The instruction is gone now.
1360 //===----------------------------------------------------------------------===//
1361 // Misc Lower Operation implementation
1362 //===----------------------------------------------------------------------===//
1363 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1364 SDValue Chain = Op.getOperand(0);
1365 SDValue Table = Op.getOperand(1);
1366 SDValue Index = Op.getOperand(2);
1368 EVT PTy = getPointerTy();
1369 unsigned EntrySize =
1370 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1372 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1373 DAG.getConstant(EntrySize, PTy));
1374 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1376 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1377 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1378 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1380 Chain = Addr.getValue(1);
1382 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
1383 // For PIC, the sequence is:
1384 // BRIND(load(Jumptable + index) + RelocBase)
1385 // RelocBase can be JumpTable, GOT or some sort of global base.
1386 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1387 getPICJumpTableRelocBase(Table, DAG));
1390 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1393 SDValue MipsTargetLowering::
1394 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1396 // The first operand is the chain, the second is the condition, the third is
1397 // the block to branch to if the condition is true.
1398 SDValue Chain = Op.getOperand(0);
1399 SDValue Dest = Op.getOperand(2);
1402 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1404 // Return if flag is not set by a floating point comparison.
1405 if (CondRes.getOpcode() != MipsISD::FPCmp)
1408 SDValue CCNode = CondRes.getOperand(2);
1410 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1411 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1412 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1413 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1414 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1415 FCC0, Dest, CondRes);
1418 SDValue MipsTargetLowering::
1419 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1421 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1423 // Return if flag is not set by a floating point comparison.
1424 if (Cond.getOpcode() != MipsISD::FPCmp)
1427 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1431 SDValue MipsTargetLowering::
1432 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1435 EVT Ty = Op.getOperand(0).getValueType();
1436 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1437 getSetCCResultType(*DAG.getContext(), Ty),
1438 Op.getOperand(0), Op.getOperand(1),
1441 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1445 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1446 SDValue Cond = createFPCmp(DAG, Op);
1448 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1449 "Floating point operand expected.");
1451 SDValue True = DAG.getConstant(1, MVT::i32);
1452 SDValue False = DAG.getConstant(0, MVT::i32);
1454 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1457 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1458 SelectionDAG &DAG) const {
1459 // FIXME there isn't actually debug info here
1461 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1463 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1464 const MipsTargetObjectFile &TLOF =
1465 (const MipsTargetObjectFile&)getObjFileLowering();
1467 // %gp_rel relocation
1468 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1469 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1471 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1472 DAG.getVTList(MVT::i32), &GA, 1);
1473 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1474 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1477 // %hi/%lo relocation
1478 return getAddrNonPIC(Op, DAG);
1481 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1482 return getAddrLocal(Op, DAG, HasMips64);
1485 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
1486 MipsII::MO_GOT_LO16);
1488 return getAddrGlobal(Op, DAG,
1489 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
1492 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1493 SelectionDAG &DAG) const {
1494 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1495 return getAddrNonPIC(Op, DAG);
1497 return getAddrLocal(Op, DAG, HasMips64);
1500 SDValue MipsTargetLowering::
1501 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1503 // If the relocation model is PIC, use the General Dynamic TLS Model or
1504 // Local Dynamic TLS model, otherwise use the Initial Exec or
1505 // Local Exec TLS Model.
1507 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1509 const GlobalValue *GV = GA->getGlobal();
1510 EVT PtrVT = getPointerTy();
1512 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1514 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1515 // General Dynamic and Local Dynamic TLS Model.
1516 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1519 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1520 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1521 getGlobalReg(DAG, PtrVT), TGA);
1522 unsigned PtrSize = PtrVT.getSizeInBits();
1523 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1525 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1529 Entry.Node = Argument;
1531 Args.push_back(Entry);
1533 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1534 false, false, false, false, 0, CallingConv::C,
1535 /*IsTailCall=*/false, /*doesNotRet=*/false,
1536 /*isReturnValueUsed=*/true,
1537 TlsGetAddr, Args, DAG, DL);
1538 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1540 SDValue Ret = CallResult.first;
1542 if (model != TLSModel::LocalDynamic)
1545 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1546 MipsII::MO_DTPREL_HI);
1547 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1548 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1549 MipsII::MO_DTPREL_LO);
1550 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1551 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1552 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1556 if (model == TLSModel::InitialExec) {
1557 // Initial Exec TLS Model
1558 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1559 MipsII::MO_GOTTPREL);
1560 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1562 Offset = DAG.getLoad(PtrVT, DL,
1563 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1564 false, false, false, 0);
1566 // Local Exec TLS Model
1567 assert(model == TLSModel::LocalExec);
1568 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1569 MipsII::MO_TPREL_HI);
1570 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1571 MipsII::MO_TPREL_LO);
1572 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1573 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1574 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1577 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1578 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1581 SDValue MipsTargetLowering::
1582 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1584 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1585 return getAddrNonPIC(Op, DAG);
1587 return getAddrLocal(Op, DAG, HasMips64);
1590 SDValue MipsTargetLowering::
1591 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1593 // gp_rel relocation
1594 // FIXME: we should reference the constant pool using small data sections,
1595 // but the asm printer currently doesn't support this feature without
1596 // hacking it. This feature should come soon so we can uncomment the
1598 //if (IsInSmallSection(C->getType())) {
1599 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1600 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1601 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1603 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1604 return getAddrNonPIC(Op, DAG);
1606 return getAddrLocal(Op, DAG, HasMips64);
1609 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1610 MachineFunction &MF = DAG.getMachineFunction();
1611 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1614 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1617 // vastart just stores the address of the VarArgsFrameIndex slot into the
1618 // memory location argument.
1619 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1620 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1621 MachinePointerInfo(SV), false, false, 0);
1624 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1625 EVT TyX = Op.getOperand(0).getValueType();
1626 EVT TyY = Op.getOperand(1).getValueType();
1627 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1628 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1632 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1634 SDValue X = (TyX == MVT::f32) ?
1635 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1636 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1638 SDValue Y = (TyY == MVT::f32) ?
1639 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1640 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1644 // ext E, Y, 31, 1 ; extract bit31 of Y
1645 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1646 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1647 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1650 // srl SrlX, SllX, 1
1652 // sll SllY, SrlX, 31
1653 // or Or, SrlX, SllY
1654 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1655 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1656 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1657 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1658 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1661 if (TyX == MVT::f32)
1662 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1664 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1665 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1666 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1669 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1670 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1671 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1672 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1673 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1676 // Bitcast to integer nodes.
1677 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1678 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1681 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1682 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1683 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1684 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1686 if (WidthX > WidthY)
1687 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1688 else if (WidthY > WidthX)
1689 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1691 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1692 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1693 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1696 // (d)sll SllX, X, 1
1697 // (d)srl SrlX, SllX, 1
1698 // (d)srl SrlY, Y, width(Y)-1
1699 // (d)sll SllY, SrlX, width(Y)-1
1700 // or Or, SrlX, SllY
1701 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1702 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1703 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1704 DAG.getConstant(WidthY - 1, MVT::i32));
1706 if (WidthX > WidthY)
1707 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1708 else if (WidthY > WidthX)
1709 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1711 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1712 DAG.getConstant(WidthX - 1, MVT::i32));
1713 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1714 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1718 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1719 if (Subtarget->hasMips64())
1720 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
1722 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
1725 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1726 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1729 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1731 SDValue X = (Op.getValueType() == MVT::f32) ?
1732 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1733 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1738 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1739 DAG.getRegister(Mips::ZERO, MVT::i32),
1740 DAG.getConstant(31, MVT::i32), Const1, X);
1742 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1743 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1746 if (Op.getValueType() == MVT::f32)
1747 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1749 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1750 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1751 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1754 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1755 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1758 // Bitcast to integer node.
1759 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1763 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1764 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1765 DAG.getConstant(63, MVT::i32), Const1, X);
1767 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1768 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1771 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1775 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
1776 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1777 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1779 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1782 SDValue MipsTargetLowering::
1783 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1785 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1786 "Frame address can only be determined for current frame.");
1788 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1789 MFI->setFrameAddressIsTaken(true);
1790 EVT VT = Op.getValueType();
1792 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1793 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1797 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1798 SelectionDAG &DAG) const {
1800 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1801 "Return address can be determined only for current frame.");
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 MachineFrameInfo *MFI = MF.getFrameInfo();
1805 MVT VT = Op.getSimpleValueType();
1806 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1807 MFI->setReturnAddressIsTaken(true);
1809 // Return RA, which contains the return address. Mark it an implicit live-in.
1810 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1811 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1814 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1815 // generated from __builtin_eh_return (offset, handler)
1816 // The effect of this is to adjust the stack pointer by "offset"
1817 // and then branch to "handler".
1818 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1820 MachineFunction &MF = DAG.getMachineFunction();
1821 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1823 MipsFI->setCallsEhReturn();
1824 SDValue Chain = Op.getOperand(0);
1825 SDValue Offset = Op.getOperand(1);
1826 SDValue Handler = Op.getOperand(2);
1828 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
1830 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1831 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1832 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1833 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
1834 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1835 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1836 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1837 DAG.getRegister(OffsetReg, Ty),
1838 DAG.getRegister(AddrReg, getPointerTy()),
1842 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1843 SelectionDAG &DAG) const {
1844 // FIXME: Need pseudo-fence for 'singlethread' fences
1845 // FIXME: Set SType for weaker fences where supported/appropriate.
1848 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1849 DAG.getConstant(SType, MVT::i32));
1852 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1853 SelectionDAG &DAG) const {
1855 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1856 SDValue Shamt = Op.getOperand(2);
1859 // lo = (shl lo, shamt)
1860 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1863 // hi = (shl lo, shamt[4:0])
1864 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1865 DAG.getConstant(-1, MVT::i32));
1866 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1867 DAG.getConstant(1, MVT::i32));
1868 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1870 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1871 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1872 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1873 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1874 DAG.getConstant(0x20, MVT::i32));
1875 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1876 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1877 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1879 SDValue Ops[2] = {Lo, Hi};
1880 return DAG.getMergeValues(Ops, 2, DL);
1883 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1886 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1887 SDValue Shamt = Op.getOperand(2);
1890 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1892 // hi = (sra hi, shamt)
1894 // hi = (srl hi, shamt)
1897 // lo = (sra hi, shamt[4:0])
1898 // hi = (sra hi, 31)
1900 // lo = (srl hi, shamt[4:0])
1902 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1903 DAG.getConstant(-1, MVT::i32));
1904 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1905 DAG.getConstant(1, MVT::i32));
1906 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1907 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1908 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1909 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1911 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1912 DAG.getConstant(0x20, MVT::i32));
1913 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1914 DAG.getConstant(31, MVT::i32));
1915 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1916 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1917 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
1920 SDValue Ops[2] = {Lo, Hi};
1921 return DAG.getMergeValues(Ops, 2, DL);
1924 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
1925 SDValue Chain, SDValue Src, unsigned Offset) {
1926 SDValue Ptr = LD->getBasePtr();
1927 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
1928 EVT BasePtrVT = Ptr.getValueType();
1930 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1933 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1934 DAG.getConstant(Offset, BasePtrVT));
1936 SDValue Ops[] = { Chain, Ptr, Src };
1937 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
1938 LD->getMemOperand());
1941 // Expand an unaligned 32 or 64-bit integer load node.
1942 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1943 LoadSDNode *LD = cast<LoadSDNode>(Op);
1944 EVT MemVT = LD->getMemoryVT();
1946 // Return if load is aligned or if MemVT is neither i32 nor i64.
1947 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
1948 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
1951 bool IsLittle = Subtarget->isLittle();
1952 EVT VT = Op.getValueType();
1953 ISD::LoadExtType ExtType = LD->getExtensionType();
1954 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
1956 assert((VT == MVT::i32) || (VT == MVT::i64));
1959 // (set dst, (i64 (load baseptr)))
1961 // (set tmp, (ldl (add baseptr, 7), undef))
1962 // (set dst, (ldr baseptr, tmp))
1963 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
1964 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1966 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
1970 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
1972 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
1976 // (set dst, (i32 (load baseptr))) or
1977 // (set dst, (i64 (sextload baseptr))) or
1978 // (set dst, (i64 (extload baseptr)))
1980 // (set tmp, (lwl (add baseptr, 3), undef))
1981 // (set dst, (lwr baseptr, tmp))
1982 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
1983 (ExtType == ISD::EXTLOAD))
1986 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
1989 // (set dst, (i64 (zextload baseptr)))
1991 // (set tmp0, (lwl (add baseptr, 3), undef))
1992 // (set tmp1, (lwr baseptr, tmp0))
1993 // (set tmp2, (shl tmp1, 32))
1994 // (set dst, (srl tmp2, 32))
1996 SDValue Const32 = DAG.getConstant(32, MVT::i32);
1997 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
1998 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
1999 SDValue Ops[] = { SRL, LWR.getValue(1) };
2000 return DAG.getMergeValues(Ops, 2, DL);
2003 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2004 SDValue Chain, unsigned Offset) {
2005 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2006 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2008 SDVTList VTList = DAG.getVTList(MVT::Other);
2011 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2012 DAG.getConstant(Offset, BasePtrVT));
2014 SDValue Ops[] = { Chain, Value, Ptr };
2015 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2016 SD->getMemOperand());
2019 // Expand an unaligned 32 or 64-bit integer store node.
2020 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2022 SDValue Value = SD->getValue(), Chain = SD->getChain();
2023 EVT VT = Value.getValueType();
2026 // (store val, baseptr) or
2027 // (truncstore val, baseptr)
2029 // (swl val, (add baseptr, 3))
2030 // (swr val, baseptr)
2031 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2032 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2034 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2037 assert(VT == MVT::i64);
2040 // (store val, baseptr)
2042 // (sdl val, (add baseptr, 7))
2043 // (sdr val, baseptr)
2044 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2045 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2048 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2049 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2050 SDValue Val = SD->getValue();
2052 if (Val.getOpcode() != ISD::FP_TO_SINT)
2055 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2056 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2059 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2060 SD->getPointerInfo(), SD->isVolatile(),
2061 SD->isNonTemporal(), SD->getAlignment());
2064 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2065 StoreSDNode *SD = cast<StoreSDNode>(Op);
2066 EVT MemVT = SD->getMemoryVT();
2068 // Lower unaligned integer stores.
2069 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2070 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2071 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
2073 return lowerFP_TO_SINT_STORE(SD, DAG);
2076 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2077 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2078 || cast<ConstantSDNode>
2079 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2080 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2084 // (add (frameaddr 0), (frame_to_args_offset))
2085 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2086 // (add FrameObject, 0)
2087 // where FrameObject is a fixed StackObject with offset 0 which points to
2088 // the old stack pointer.
2089 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2090 EVT ValTy = Op->getValueType(0);
2091 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2092 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2093 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2094 DAG.getConstant(0, ValTy));
2097 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2098 SelectionDAG &DAG) const {
2099 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2100 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2102 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2105 //===----------------------------------------------------------------------===//
2106 // Calling Convention Implementation
2107 //===----------------------------------------------------------------------===//
2109 //===----------------------------------------------------------------------===//
2110 // TODO: Implement a generic logic using tblgen that can support this.
2111 // Mips O32 ABI rules:
2113 // i32 - Passed in A0, A1, A2, A3 and stack
2114 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2115 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2116 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2117 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2118 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2121 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2122 //===----------------------------------------------------------------------===//
2124 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2125 MVT LocVT, CCValAssign::LocInfo LocInfo,
2126 ISD::ArgFlagsTy ArgFlags, CCState &State,
2127 const uint16_t *F64Regs) {
2129 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2131 static const uint16_t IntRegs[] = {
2132 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2134 static const uint16_t F32Regs[] = {
2135 Mips::F12, Mips::F14
2138 // Do not process byval args here.
2139 if (ArgFlags.isByVal())
2142 // Promote i8 and i16
2143 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2145 if (ArgFlags.isSExt())
2146 LocInfo = CCValAssign::SExt;
2147 else if (ArgFlags.isZExt())
2148 LocInfo = CCValAssign::ZExt;
2150 LocInfo = CCValAssign::AExt;
2155 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2156 // is true: function is vararg, argument is 3rd or higher, there is previous
2157 // argument which is not f32 or f64.
2158 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2159 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2160 unsigned OrigAlign = ArgFlags.getOrigAlign();
2161 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2163 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2164 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2165 // If this is the first part of an i64 arg,
2166 // the allocated register must be either A0 or A2.
2167 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2168 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2170 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2171 // Allocate int register and shadow next int register. If first
2172 // available register is Mips::A1 or Mips::A3, shadow it too.
2173 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2174 if (Reg == Mips::A1 || Reg == Mips::A3)
2175 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2176 State.AllocateReg(IntRegs, IntRegsSize);
2178 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2179 // we are guaranteed to find an available float register
2180 if (ValVT == MVT::f32) {
2181 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2182 // Shadow int register
2183 State.AllocateReg(IntRegs, IntRegsSize);
2185 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2186 // Shadow int registers
2187 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2188 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2189 State.AllocateReg(IntRegs, IntRegsSize);
2190 State.AllocateReg(IntRegs, IntRegsSize);
2193 llvm_unreachable("Cannot handle this ValVT.");
2196 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2198 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2200 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2205 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2206 MVT LocVT, CCValAssign::LocInfo LocInfo,
2207 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2208 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 };
2210 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2213 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2214 MVT LocVT, CCValAssign::LocInfo LocInfo,
2215 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2216 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 };
2218 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2221 #include "MipsGenCallingConv.inc"
2223 //===----------------------------------------------------------------------===//
2224 // Call Calling Convention Implementation
2225 //===----------------------------------------------------------------------===//
2227 static const unsigned O32IntRegsSize = 4;
2229 // Return next O32 integer argument register.
2230 static unsigned getNextIntArgReg(unsigned Reg) {
2231 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2232 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2236 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2237 SDValue Chain, SDValue Arg, SDLoc DL,
2238 bool IsTailCall, SelectionDAG &DAG) const {
2240 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2241 DAG.getIntPtrConstant(Offset));
2242 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2246 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2247 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2248 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2249 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2250 /*isVolatile=*/ true, false, 0);
2253 void MipsTargetLowering::
2254 getOpndList(SmallVectorImpl<SDValue> &Ops,
2255 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2256 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2257 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2258 // Insert node "GP copy globalreg" before call to function.
2260 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2261 // in PIC mode) allow symbols to be resolved via lazy binding.
2262 // The lazy binding stub requires GP to point to the GOT.
2263 if (IsPICCall && !InternalLinkage) {
2264 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2265 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2266 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2269 // Build a sequence of copy-to-reg nodes chained together with token
2270 // chain and flag operands which copy the outgoing args into registers.
2271 // The InFlag in necessary since all emitted instructions must be
2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2276 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2277 RegsToPass[i].second, InFlag);
2278 InFlag = Chain.getValue(1);
2281 // Add argument registers to the end of the list so that they are
2282 // known live into the call.
2283 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2284 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2285 RegsToPass[i].second.getValueType()));
2287 // Add a register mask operand representing the call-preserved registers.
2288 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2289 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2290 assert(Mask && "Missing call preserved mask for calling convention");
2291 if (Subtarget->inMips16HardFloat()) {
2292 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2293 llvm::StringRef Sym = G->getGlobal()->getName();
2294 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2295 if (F->hasFnAttribute("__Mips16RetHelper")) {
2296 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2300 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2302 if (InFlag.getNode())
2303 Ops.push_back(InFlag);
2306 /// LowerCall - functions arguments are copied from virtual regs to
2307 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2309 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2310 SmallVectorImpl<SDValue> &InVals) const {
2311 SelectionDAG &DAG = CLI.DAG;
2313 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2314 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2315 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2316 SDValue Chain = CLI.Chain;
2317 SDValue Callee = CLI.Callee;
2318 bool &IsTailCall = CLI.IsTailCall;
2319 CallingConv::ID CallConv = CLI.CallConv;
2320 bool IsVarArg = CLI.IsVarArg;
2322 MachineFunction &MF = DAG.getMachineFunction();
2323 MachineFrameInfo *MFI = MF.getFrameInfo();
2324 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2325 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2327 // Analyze operands of the call, assigning locations to each operand.
2328 SmallVector<CCValAssign, 16> ArgLocs;
2329 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2330 getTargetMachine(), ArgLocs, *DAG.getContext());
2331 MipsCC::SpecialCallingConvType SpecialCallingConv =
2332 getSpecialCallingConv(Callee);
2333 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo,
2334 SpecialCallingConv);
2336 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2337 getTargetMachine().Options.UseSoftFloat,
2338 Callee.getNode(), CLI.Args);
2340 // Get a count of how many bytes are to be pushed on the stack.
2341 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2343 // Check if it's really possible to do a tail call.
2346 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2347 *MF.getInfo<MipsFunctionInfo>());
2352 // Chain is the output chain of the last Load/Store or CopyToReg node.
2353 // ByValChain is the output chain of the last Memcpy node created for copying
2354 // byval arguments to the stack.
2355 unsigned StackAlignment = TFL->getStackAlignment();
2356 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2357 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2360 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2362 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
2363 IsN64 ? Mips::SP_64 : Mips::SP,
2366 // With EABI is it possible to have 16 args on registers.
2367 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2368 SmallVector<SDValue, 8> MemOpChains;
2369 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2371 // Walk the register/memloc assignments, inserting copies/loads.
2372 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2373 SDValue Arg = OutVals[i];
2374 CCValAssign &VA = ArgLocs[i];
2375 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2376 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2379 if (Flags.isByVal()) {
2380 assert(Flags.getByValSize() &&
2381 "ByVal args of size 0 should have been ignored by front-end.");
2382 assert(ByValArg != MipsCCInfo.byval_end());
2383 assert(!IsTailCall &&
2384 "Do not tail-call optimize if there is a byval argument.");
2385 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2386 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2391 // Promote the value if needed.
2392 switch (VA.getLocInfo()) {
2393 default: llvm_unreachable("Unknown loc info!");
2394 case CCValAssign::Full:
2395 if (VA.isRegLoc()) {
2396 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2397 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2398 (ValVT == MVT::i64 && LocVT == MVT::f64))
2399 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2400 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2401 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2402 Arg, DAG.getConstant(0, MVT::i32));
2403 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2404 Arg, DAG.getConstant(1, MVT::i32));
2405 if (!Subtarget->isLittle())
2407 unsigned LocRegLo = VA.getLocReg();
2408 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2409 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2410 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2415 case CCValAssign::SExt:
2416 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2418 case CCValAssign::ZExt:
2419 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2421 case CCValAssign::AExt:
2422 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2426 // Arguments that can be passed on register must be kept at
2427 // RegsToPass vector
2428 if (VA.isRegLoc()) {
2429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2433 // Register can't get to this point...
2434 assert(VA.isMemLoc());
2436 // emit ISD::STORE whichs stores the
2437 // parameter value to a stack Location
2438 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2439 Chain, Arg, DL, IsTailCall, DAG));
2442 // Transform all store nodes into one single node because all store
2443 // nodes are independent of each other.
2444 if (!MemOpChains.empty())
2445 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2446 &MemOpChains[0], MemOpChains.size());
2448 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2449 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2450 // node so that legalize doesn't hack it.
2451 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2452 bool GlobalOrExternal = false, InternalLinkage = false;
2455 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2457 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2459 if (InternalLinkage)
2460 Callee = getAddrLocal(Callee, DAG, HasMips64);
2462 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2463 MipsII::MO_CALL_LO16);
2465 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2467 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2468 MipsII::MO_NO_FLAG);
2469 GlobalOrExternal = true;
2471 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2472 if (!IsN64 && !IsPIC) // !N64 && static
2473 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2474 MipsII::MO_NO_FLAG);
2476 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2477 MipsII::MO_CALL_LO16);
2479 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2481 GlobalOrExternal = true;
2484 SmallVector<SDValue, 8> Ops(1, Chain);
2485 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2487 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2488 CLI, Callee, Chain);
2491 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
2493 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
2494 SDValue InFlag = Chain.getValue(1);
2496 // Create the CALLSEQ_END node.
2497 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2498 DAG.getIntPtrConstant(0, true), InFlag, DL);
2499 InFlag = Chain.getValue(1);
2501 // Handle result values, copying them out of physregs into vregs that we
2503 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2504 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2507 /// LowerCallResult - Lower the result values of a call into the
2508 /// appropriate copies out of appropriate physical registers.
2510 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2511 CallingConv::ID CallConv, bool IsVarArg,
2512 const SmallVectorImpl<ISD::InputArg> &Ins,
2513 SDLoc DL, SelectionDAG &DAG,
2514 SmallVectorImpl<SDValue> &InVals,
2515 const SDNode *CallNode,
2516 const Type *RetTy) const {
2517 // Assign locations to each value returned by this call.
2518 SmallVector<CCValAssign, 16> RVLocs;
2519 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2520 getTargetMachine(), RVLocs, *DAG.getContext());
2521 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2523 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat,
2526 // Copy all of the result registers out of their specified physreg.
2527 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2528 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2529 RVLocs[i].getLocVT(), InFlag);
2530 Chain = Val.getValue(1);
2531 InFlag = Val.getValue(2);
2533 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2534 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2536 InVals.push_back(Val);
2542 //===----------------------------------------------------------------------===//
2543 // Formal Arguments Calling Convention Implementation
2544 //===----------------------------------------------------------------------===//
2545 /// LowerFormalArguments - transform physical registers into virtual registers
2546 /// and generate load operations for arguments places on the stack.
2548 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2549 CallingConv::ID CallConv,
2551 const SmallVectorImpl<ISD::InputArg> &Ins,
2552 SDLoc DL, SelectionDAG &DAG,
2553 SmallVectorImpl<SDValue> &InVals)
2555 MachineFunction &MF = DAG.getMachineFunction();
2556 MachineFrameInfo *MFI = MF.getFrameInfo();
2557 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2559 MipsFI->setVarArgsFrameIndex(0);
2561 // Used with vargs to acumulate store chains.
2562 std::vector<SDValue> OutChains;
2564 // Assign locations to all of the incoming arguments.
2565 SmallVector<CCValAssign, 16> ArgLocs;
2566 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2567 getTargetMachine(), ArgLocs, *DAG.getContext());
2568 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2569 Function::const_arg_iterator FuncArg =
2570 DAG.getMachineFunction().getFunction()->arg_begin();
2571 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat;
2573 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2574 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2575 MipsCCInfo.hasByValArg());
2577 unsigned CurArgIdx = 0;
2578 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2580 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2581 CCValAssign &VA = ArgLocs[i];
2582 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2583 CurArgIdx = Ins[i].OrigArgIndex;
2584 EVT ValVT = VA.getValVT();
2585 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2586 bool IsRegLoc = VA.isRegLoc();
2588 if (Flags.isByVal()) {
2589 assert(Flags.getByValSize() &&
2590 "ByVal args of size 0 should have been ignored by front-end.");
2591 assert(ByValArg != MipsCCInfo.byval_end());
2592 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2593 MipsCCInfo, *ByValArg);
2598 // Arguments stored on registers
2600 EVT RegVT = VA.getLocVT();
2601 unsigned ArgReg = VA.getLocReg();
2602 const TargetRegisterClass *RC;
2604 if (RegVT == MVT::i32)
2605 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2606 &Mips::GPR32RegClass;
2607 else if (RegVT == MVT::i64)
2608 RC = &Mips::GPR64RegClass;
2609 else if (RegVT == MVT::f32)
2610 RC = &Mips::FGR32RegClass;
2611 else if (RegVT == MVT::f64)
2612 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass :
2613 &Mips::AFGR64RegClass;
2615 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2617 // Transform the arguments stored on
2618 // physical registers into virtual ones
2619 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2620 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2622 // If this is an 8 or 16-bit value, it has been passed promoted
2623 // to 32 bits. Insert an assert[sz]ext to capture this, then
2624 // truncate to the right size.
2625 if (VA.getLocInfo() != CCValAssign::Full) {
2626 unsigned Opcode = 0;
2627 if (VA.getLocInfo() == CCValAssign::SExt)
2628 Opcode = ISD::AssertSext;
2629 else if (VA.getLocInfo() == CCValAssign::ZExt)
2630 Opcode = ISD::AssertZext;
2632 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2633 DAG.getValueType(ValVT));
2634 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2637 // Handle floating point arguments passed in integer registers and
2638 // long double arguments passed in floating point registers.
2639 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2640 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2641 (RegVT == MVT::f64 && ValVT == MVT::i64))
2642 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2643 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2644 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2645 getNextIntArgReg(ArgReg), RC);
2646 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2647 if (!Subtarget->isLittle())
2648 std::swap(ArgValue, ArgValue2);
2649 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2650 ArgValue, ArgValue2);
2653 InVals.push_back(ArgValue);
2654 } else { // VA.isRegLoc()
2657 assert(VA.isMemLoc());
2659 // The stack pointer offset is relative to the caller stack frame.
2660 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2661 VA.getLocMemOffset(), true);
2663 // Create load nodes to retrieve arguments from the stack
2664 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2665 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
2666 MachinePointerInfo::getFixedStack(FI),
2667 false, false, false, 0));
2671 // The mips ABIs for returning structs by value requires that we copy
2672 // the sret argument into $v0 for the return. Save the argument into
2673 // a virtual register so that we can access it from the return points.
2674 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2675 unsigned Reg = MipsFI->getSRetReturnReg();
2677 Reg = MF.getRegInfo().
2678 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
2679 MipsFI->setSRetReturnReg(Reg);
2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
2682 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2686 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2688 // All stores are grouped in one node to allow the matching between
2689 // the size of Ins and InVals. This only happens when on varg functions
2690 if (!OutChains.empty()) {
2691 OutChains.push_back(Chain);
2692 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2693 &OutChains[0], OutChains.size());
2699 //===----------------------------------------------------------------------===//
2700 // Return Value Calling Convention Implementation
2701 //===----------------------------------------------------------------------===//
2704 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2705 MachineFunction &MF, bool IsVarArg,
2706 const SmallVectorImpl<ISD::OutputArg> &Outs,
2707 LLVMContext &Context) const {
2708 SmallVector<CCValAssign, 16> RVLocs;
2709 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2711 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2715 MipsTargetLowering::LowerReturn(SDValue Chain,
2716 CallingConv::ID CallConv, bool IsVarArg,
2717 const SmallVectorImpl<ISD::OutputArg> &Outs,
2718 const SmallVectorImpl<SDValue> &OutVals,
2719 SDLoc DL, SelectionDAG &DAG) const {
2720 // CCValAssign - represent the assignment of
2721 // the return value to a location
2722 SmallVector<CCValAssign, 16> RVLocs;
2723 MachineFunction &MF = DAG.getMachineFunction();
2725 // CCState - Info about the registers and stack slot.
2726 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2728 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2730 // Analyze return values.
2731 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat,
2732 MF.getFunction()->getReturnType());
2735 SmallVector<SDValue, 4> RetOps(1, Chain);
2737 // Copy the result values into the output registers.
2738 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2739 SDValue Val = OutVals[i];
2740 CCValAssign &VA = RVLocs[i];
2741 assert(VA.isRegLoc() && "Can only return in registers!");
2743 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2744 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2746 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2748 // Guarantee that all emitted copies are stuck together with flags.
2749 Flag = Chain.getValue(1);
2750 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2753 // The mips ABIs for returning structs by value requires that we copy
2754 // the sret argument into $v0 for the return. We saved the argument into
2755 // a virtual register in the entry block, so now we copy the value out
2757 if (MF.getFunction()->hasStructRetAttr()) {
2758 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2759 unsigned Reg = MipsFI->getSRetReturnReg();
2762 llvm_unreachable("sret virtual register not created in the entry block");
2763 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2764 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2766 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2767 Flag = Chain.getValue(1);
2768 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2771 RetOps[0] = Chain; // Update chain.
2773 // Add the flag if we have it.
2775 RetOps.push_back(Flag);
2777 // Return on Mips is always a "jr $ra"
2778 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
2781 //===----------------------------------------------------------------------===//
2782 // Mips Inline Assembly Support
2783 //===----------------------------------------------------------------------===//
2785 /// getConstraintType - Given a constraint letter, return the type of
2786 /// constraint it is for this target.
2787 MipsTargetLowering::ConstraintType MipsTargetLowering::
2788 getConstraintType(const std::string &Constraint) const
2790 // Mips specific constrainy
2791 // GCC config/mips/constraints.md
2793 // 'd' : An address register. Equivalent to r
2794 // unless generating MIPS16 code.
2795 // 'y' : Equivalent to r; retained for
2796 // backwards compatibility.
2797 // 'c' : A register suitable for use in an indirect
2798 // jump. This will always be $25 for -mabicalls.
2799 // 'l' : The lo register. 1 word storage.
2800 // 'x' : The hilo register pair. Double word storage.
2801 if (Constraint.size() == 1) {
2802 switch (Constraint[0]) {
2810 return C_RegisterClass;
2815 return TargetLowering::getConstraintType(Constraint);
2818 /// Examine constraint type and operand type and determine a weight value.
2819 /// This object must already have been set up with the operand type
2820 /// and the current alternative constraint selected.
2821 TargetLowering::ConstraintWeight
2822 MipsTargetLowering::getSingleConstraintMatchWeight(
2823 AsmOperandInfo &info, const char *constraint) const {
2824 ConstraintWeight weight = CW_Invalid;
2825 Value *CallOperandVal = info.CallOperandVal;
2826 // If we don't have a value, we can't do a match,
2827 // but allow it at the lowest weight.
2828 if (CallOperandVal == NULL)
2830 Type *type = CallOperandVal->getType();
2831 // Look at the constraint type.
2832 switch (*constraint) {
2834 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2838 if (type->isIntegerTy())
2839 weight = CW_Register;
2842 if (type->isFloatTy())
2843 weight = CW_Register;
2845 case 'c': // $25 for indirect jumps
2846 case 'l': // lo register
2847 case 'x': // hilo register pair
2848 if (type->isIntegerTy())
2849 weight = CW_SpecificReg;
2851 case 'I': // signed 16 bit immediate
2852 case 'J': // integer zero
2853 case 'K': // unsigned 16 bit immediate
2854 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2855 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2856 case 'O': // signed 15 bit immediate (+- 16383)
2857 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2858 if (isa<ConstantInt>(CallOperandVal))
2859 weight = CW_Constant;
2868 /// This is a helper function to parse a physical register string and split it
2869 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
2870 /// that is returned indicates whether parsing was successful. The second flag
2871 /// is true if the numeric part exists.
2872 static std::pair<bool, bool>
2873 parsePhysicalReg(const StringRef &C, std::string &Prefix,
2874 unsigned long long &Reg) {
2875 if (C.front() != '{' || C.back() != '}')
2876 return std::make_pair(false, false);
2878 // Search for the first numeric character.
2879 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
2880 I = std::find_if(B, E, std::ptr_fun(isdigit));
2882 Prefix.assign(B, I - B);
2884 // The second flag is set to false if no numeric characters were found.
2886 return std::make_pair(true, false);
2888 // Parse the numeric characters.
2889 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
2893 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
2894 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
2895 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2896 const TargetRegisterClass *RC;
2898 unsigned long long Reg;
2900 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
2903 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2905 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
2906 // No numeric characters follow "hi" or "lo".
2908 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2910 RC = TRI->getRegClass(Prefix == "hi" ?
2911 Mips::HI32RegClassID : Mips::LO32RegClassID);
2912 return std::make_pair(*(RC->begin()), RC);
2916 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2918 if (Prefix == "$f") { // Parse $f0-$f31.
2919 // If the size of FP registers is 64-bit or Reg is an even number, select
2920 // the 64-bit register class. Otherwise, select the 32-bit register class.
2921 if (VT == MVT::Other)
2922 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
2924 RC= getRegClassFor(VT);
2926 if (RC == &Mips::AFGR64RegClass) {
2927 assert(Reg % 2 == 0);
2930 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7.
2931 RC = TRI->getRegClass(Mips::FCCRegClassID);
2932 } else { // Parse $0-$31.
2933 assert(Prefix == "$");
2934 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
2937 assert(Reg < RC->getNumRegs());
2938 return std::make_pair(*(RC->begin() + Reg), RC);
2941 /// Given a register class constraint, like 'r', if this corresponds directly
2942 /// to an LLVM register class, return a register of 0 and the register class
2944 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2945 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
2947 if (Constraint.size() == 1) {
2948 switch (Constraint[0]) {
2949 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2950 case 'y': // Same as 'r'. Exists for compatibility.
2952 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
2953 if (Subtarget->inMips16Mode())
2954 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2955 return std::make_pair(0U, &Mips::GPR32RegClass);
2957 if (VT == MVT::i64 && !HasMips64)
2958 return std::make_pair(0U, &Mips::GPR32RegClass);
2959 if (VT == MVT::i64 && HasMips64)
2960 return std::make_pair(0U, &Mips::GPR64RegClass);
2961 // This will generate an error message
2962 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2965 return std::make_pair(0U, &Mips::FGR32RegClass);
2966 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
2967 if (Subtarget->isFP64bit())
2968 return std::make_pair(0U, &Mips::FGR64RegClass);
2969 return std::make_pair(0U, &Mips::AFGR64RegClass);
2972 case 'c': // register suitable for indirect jump
2974 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
2975 assert(VT == MVT::i64 && "Unexpected type.");
2976 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
2977 case 'l': // register suitable for indirect jump
2979 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
2980 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
2981 case 'x': // register suitable for indirect jump
2982 // Fixme: Not triggering the use of both hi and low
2983 // This will generate an error message
2984 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2988 std::pair<unsigned, const TargetRegisterClass *> R;
2989 R = parseRegForInlineAsmConstraint(Constraint, VT);
2994 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2997 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2998 /// vector. If it is invalid, don't add anything to Ops.
2999 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3000 std::string &Constraint,
3001 std::vector<SDValue>&Ops,
3002 SelectionDAG &DAG) const {
3003 SDValue Result(0, 0);
3005 // Only support length 1 constraints for now.
3006 if (Constraint.length() > 1) return;
3008 char ConstraintLetter = Constraint[0];
3009 switch (ConstraintLetter) {
3010 default: break; // This will fall through to the generic implementation
3011 case 'I': // Signed 16 bit constant
3012 // If this fails, the parent routine will give an error
3013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3014 EVT Type = Op.getValueType();
3015 int64_t Val = C->getSExtValue();
3016 if (isInt<16>(Val)) {
3017 Result = DAG.getTargetConstant(Val, Type);
3022 case 'J': // integer zero
3023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3024 EVT Type = Op.getValueType();
3025 int64_t Val = C->getZExtValue();
3027 Result = DAG.getTargetConstant(0, Type);
3032 case 'K': // unsigned 16 bit immediate
3033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3034 EVT Type = Op.getValueType();
3035 uint64_t Val = (uint64_t)C->getZExtValue();
3036 if (isUInt<16>(Val)) {
3037 Result = DAG.getTargetConstant(Val, Type);
3042 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3044 EVT Type = Op.getValueType();
3045 int64_t Val = C->getSExtValue();
3046 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3047 Result = DAG.getTargetConstant(Val, Type);
3052 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3054 EVT Type = Op.getValueType();
3055 int64_t Val = C->getSExtValue();
3056 if ((Val >= -65535) && (Val <= -1)) {
3057 Result = DAG.getTargetConstant(Val, Type);
3062 case 'O': // signed 15 bit immediate
3063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3064 EVT Type = Op.getValueType();
3065 int64_t Val = C->getSExtValue();
3066 if ((isInt<15>(Val))) {
3067 Result = DAG.getTargetConstant(Val, Type);
3072 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3074 EVT Type = Op.getValueType();
3075 int64_t Val = C->getSExtValue();
3076 if ((Val <= 65535) && (Val >= 1)) {
3077 Result = DAG.getTargetConstant(Val, Type);
3084 if (Result.getNode()) {
3085 Ops.push_back(Result);
3089 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3093 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
3094 // No global is ever allowed as a base.
3099 case 0: // "r+i" or just "i", depending on HasBaseReg.
3102 if (!AM.HasBaseReg) // allow "r+i".
3104 return false; // disallow "r+r" or "r+r+i".
3113 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3114 // The Mips target isn't yet aware of offsets.
3118 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3120 bool IsMemset, bool ZeroMemset,
3122 MachineFunction &MF) const {
3123 if (Subtarget->hasMips64())
3129 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3130 if (VT != MVT::f32 && VT != MVT::f64)
3132 if (Imm.isNegZero())
3134 return Imm.isZero();
3137 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3139 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3141 return TargetLowering::getJumpTableEncoding();
3144 /// This function returns true if CallSym is a long double emulation routine.
3145 static bool isF128SoftLibCall(const char *CallSym) {
3146 const char *const LibCalls[] =
3147 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3148 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3149 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3150 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3151 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3152 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3153 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3154 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3157 const char * const *End = LibCalls + array_lengthof(LibCalls);
3159 // Check that LibCalls is sorted alphabetically.
3160 MipsTargetLowering::LTStr Comp;
3163 for (const char * const *I = LibCalls; I < End - 1; ++I)
3164 assert(Comp(*I, *(I + 1)));
3167 return std::binary_search(LibCalls, End, CallSym, Comp);
3170 /// This function returns true if Ty is fp128 or i128 which was originally a
3172 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3173 if (Ty->isFP128Ty())
3176 const ExternalSymbolSDNode *ES =
3177 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3179 // If the Ty is i128 and the function being called is a long double emulation
3180 // routine, then the original type is f128.
3181 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3184 MipsTargetLowering::MipsCC::SpecialCallingConvType
3185 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3186 MipsCC::SpecialCallingConvType SpecialCallingConv =
3187 MipsCC::NoSpecialCallingConv;;
3188 if (Subtarget->inMips16HardFloat()) {
3189 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3190 llvm::StringRef Sym = G->getGlobal()->getName();
3191 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3192 if (F->hasFnAttribute("__Mips16RetHelper")) {
3193 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3197 return SpecialCallingConv;
3200 MipsTargetLowering::MipsCC::MipsCC(
3201 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
3202 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3203 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
3204 SpecialCallingConv(SpecialCallingConv_){
3205 // Pre-allocate reserved argument area.
3206 CCInfo.AllocateStack(reservedArgArea(), 1);
3210 void MipsTargetLowering::MipsCC::
3211 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3212 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3213 std::vector<ArgListEntry> &FuncArgs) {
3214 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3215 "CallingConv::Fast shouldn't be used for vararg functions.");
3217 unsigned NumOpnds = Args.size();
3218 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3220 for (unsigned I = 0; I != NumOpnds; ++I) {
3221 MVT ArgVT = Args[I].VT;
3222 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3225 if (ArgFlags.isByVal()) {
3226 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3230 if (IsVarArg && !Args[I].IsFixed)
3231 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3233 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3235 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3240 dbgs() << "Call operand #" << I << " has unhandled type "
3241 << EVT(ArgVT).getEVTString();
3243 llvm_unreachable(0);
3248 void MipsTargetLowering::MipsCC::
3249 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3250 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3251 unsigned NumArgs = Args.size();
3252 llvm::CCAssignFn *FixedFn = fixedArgFn();
3253 unsigned CurArgIdx = 0;
3255 for (unsigned I = 0; I != NumArgs; ++I) {
3256 MVT ArgVT = Args[I].VT;
3257 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3258 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3259 CurArgIdx = Args[I].OrigArgIndex;
3261 if (ArgFlags.isByVal()) {
3262 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3266 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
3268 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3272 dbgs() << "Formal Arg #" << I << " has unhandled type "
3273 << EVT(ArgVT).getEVTString();
3275 llvm_unreachable(0);
3279 template<typename Ty>
3280 void MipsTargetLowering::MipsCC::
3281 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3282 const SDNode *CallNode, const Type *RetTy) const {
3285 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3286 Fn = RetCC_F128Soft;
3290 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3291 MVT VT = RetVals[I].VT;
3292 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3293 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3295 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3297 dbgs() << "Call result #" << I << " has unhandled type "
3298 << EVT(VT).getEVTString() << '\n';
3300 llvm_unreachable(0);
3305 void MipsTargetLowering::MipsCC::
3306 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3307 const SDNode *CallNode, const Type *RetTy) const {
3308 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3311 void MipsTargetLowering::MipsCC::
3312 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3313 const Type *RetTy) const {
3314 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
3318 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3320 CCValAssign::LocInfo LocInfo,
3321 ISD::ArgFlagsTy ArgFlags) {
3322 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3324 struct ByValArgInfo ByVal;
3325 unsigned RegSize = regSize();
3326 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3327 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3330 if (useRegsForByval())
3331 allocateRegs(ByVal, ByValSize, Align);
3333 // Allocate space on caller's stack.
3334 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3336 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3338 ByValArgs.push_back(ByVal);
3341 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3342 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3345 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3346 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3349 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3350 return IsO32 ? O32IntRegs : Mips64IntRegs;
3353 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3354 if (CallConv == CallingConv::Fast)
3355 return CC_Mips_FastCC;
3357 if (SpecialCallingConv == Mips16RetHelperConv)
3358 return CC_Mips16RetHelper;
3359 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
3362 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3363 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
3366 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3367 return IsO32 ? O32IntRegs : Mips64DPRegs;
3370 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3373 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3374 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3375 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3376 "Byval argument's size and alignment should be a multiple of"
3379 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3381 // If Align > RegSize, the first arg register must be even.
3382 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3383 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3387 // Mark the registers allocated.
3388 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3389 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3390 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3393 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3394 const SDNode *CallNode,
3395 bool IsSoftFloat) const {
3396 if (IsSoftFloat || IsO32)
3399 // Check if the original type was fp128.
3400 if (originalTypeIsF128(OrigTy, CallNode)) {
3401 assert(VT == MVT::i64);
3408 void MipsTargetLowering::
3409 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3410 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3411 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3412 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3413 MachineFunction &MF = DAG.getMachineFunction();
3414 MachineFrameInfo *MFI = MF.getFrameInfo();
3415 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3416 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3420 FrameObjOffset = (int)CC.reservedArgArea() -
3421 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3423 FrameObjOffset = ByVal.Address;
3425 // Create frame object.
3426 EVT PtrTy = getPointerTy();
3427 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3428 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3429 InVals.push_back(FIN);
3434 // Copy arg registers.
3435 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3436 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3438 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3439 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3440 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3441 unsigned Offset = I * CC.regSize();
3442 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3443 DAG.getConstant(Offset, PtrTy));
3444 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3445 StorePtr, MachinePointerInfo(FuncArg, Offset),
3447 OutChains.push_back(Store);
3451 // Copy byVal arg to registers and stack.
3452 void MipsTargetLowering::
3453 passByValArg(SDValue Chain, SDLoc DL,
3454 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3455 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3456 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3457 const MipsCC &CC, const ByValArgInfo &ByVal,
3458 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3459 unsigned ByValSize = Flags.getByValSize();
3460 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3461 unsigned RegSize = CC.regSize();
3462 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3463 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3465 if (ByVal.NumRegs) {
3466 const uint16_t *ArgRegs = CC.intArgRegs();
3467 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3470 // Copy words to registers.
3471 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3472 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3473 DAG.getConstant(Offset, PtrTy));
3474 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3475 MachinePointerInfo(), false, false, false,
3477 MemOpChains.push_back(LoadVal.getValue(1));
3478 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3479 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3482 // Return if the struct has been fully copied.
3483 if (ByValSize == Offset)
3486 // Copy the remainder of the byval argument with sub-word loads and shifts.
3487 if (LeftoverBytes) {
3488 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3489 "Size of the remainder should be smaller than RegSize.");
3492 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3493 Offset < ByValSize; LoadSize /= 2) {
3494 unsigned RemSize = ByValSize - Offset;
3496 if (RemSize < LoadSize)
3500 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3501 DAG.getConstant(Offset, PtrTy));
3503 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3504 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3505 false, false, Alignment);
3506 MemOpChains.push_back(LoadVal.getValue(1));
3508 // Shift the loaded value.
3512 Shamt = TotalSizeLoaded;
3514 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3516 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3517 DAG.getConstant(Shamt, MVT::i32));
3520 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3525 TotalSizeLoaded += LoadSize;
3526 Alignment = std::min(Alignment, LoadSize);
3529 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3530 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3535 // Copy remainder of byval arg to it with memcpy.
3536 unsigned MemCpySize = ByValSize - Offset;
3537 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3538 DAG.getConstant(Offset, PtrTy));
3539 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3540 DAG.getIntPtrConstant(ByVal.Address));
3541 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3542 DAG.getConstant(MemCpySize, PtrTy), Alignment,
3543 /*isVolatile=*/false, /*AlwaysInline=*/false,
3544 MachinePointerInfo(0), MachinePointerInfo(0));
3545 MemOpChains.push_back(Chain);
3549 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3550 const MipsCC &CC, SDValue Chain,
3551 SDLoc DL, SelectionDAG &DAG) const {
3552 unsigned NumRegs = CC.numIntArgRegs();
3553 const uint16_t *ArgRegs = CC.intArgRegs();
3554 const CCState &CCInfo = CC.getCCInfo();
3555 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3556 unsigned RegSize = CC.regSize();
3557 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3558 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3559 MachineFunction &MF = DAG.getMachineFunction();
3560 MachineFrameInfo *MFI = MF.getFrameInfo();
3561 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3563 // Offset of the first variable argument from stack pointer.
3567 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3570 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3572 // Record the frame index of the first variable argument
3573 // which is a value necessary to VASTART.
3574 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3575 MipsFI->setVarArgsFrameIndex(FI);
3577 // Copy the integer registers that have not been used for argument passing
3578 // to the argument register save area. For O32, the save area is allocated
3579 // in the caller's stack frame, while for N32/64, it is allocated in the
3580 // callee's stack frame.
3581 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3582 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3583 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3584 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3585 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3586 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3587 MachinePointerInfo(), false, false, 0);
3588 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3589 OutChains.push_back(Store);