1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 default : return NULL;
51 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
53 // Mips does not have i1 type, so use i32 for
54 // setcc operations results (slt, sgt, ...).
55 setSetCCResultContents(ZeroOrOneSetCCResult);
57 // JumpTable targets must use GOT when using PIC_
58 setUsesGlobalOffsetTable(true);
60 // Set up the register classes
61 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
64 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
65 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
66 setOperationAction(ISD::RET, MVT::Other, Custom);
67 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
69 // Load extented operations for i1 types must be promoted
70 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
71 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
72 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
74 // Mips does not have these NodeTypes below.
75 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
76 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
79 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
82 // Mips not supported intrinsics.
83 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
85 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
86 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
87 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
88 setOperationAction(ISD::ROTL , MVT::i32, Expand);
89 setOperationAction(ISD::ROTR , MVT::i32, Expand);
90 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
92 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
93 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
94 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
96 // We don't have line number support yet.
97 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
98 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
99 setOperationAction(ISD::LABEL, MVT::Other, Expand);
101 // Use the default for now
102 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
103 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
105 setStackPointerRegisterToSaveRestore(Mips::SP);
106 computeRegisterProperties();
111 MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
116 SDOperand MipsTargetLowering::
117 LowerOperation(SDOperand Op, SelectionDAG &DAG)
119 switch (Op.getOpcode())
121 case ISD::CALL: return LowerCALL(Op, DAG);
122 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
123 case ISD::RET: return LowerRET(Op, DAG);
124 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
125 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
126 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
131 //===----------------------------------------------------------------------===//
132 // Lower helper functions
133 //===----------------------------------------------------------------------===//
135 // AddLiveIn - This helper function adds the specified physical register to the
136 // MachineFunction as a live in value. It also creates a corresponding
137 // virtual register for it.
139 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
141 assert(RC->contains(PReg) && "Not the correct regclass!");
142 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
143 MF.getRegInfo().addLiveIn(PReg, VReg);
147 //===----------------------------------------------------------------------===//
148 // Misc Lower Operation implementation
149 //===----------------------------------------------------------------------===//
150 SDOperand MipsTargetLowering::
151 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
154 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
155 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
156 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
160 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
161 SDOperand Ops[] = { GA };
162 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
163 } else // Emit Load from Global Pointer
164 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
166 // On functions and global targets not internal linked only
167 // a load from got/GP is necessary for PIC to work.
168 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
171 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
172 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
177 SDOperand MipsTargetLowering::
178 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
180 assert(0 && "TLS not implemented for MIPS.");
181 return SDOperand(); // Not reached
184 SDOperand MipsTargetLowering::
185 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
190 MVT::ValueType PtrVT = Op.getValueType();
191 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
192 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
194 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
195 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
196 SDOperand Ops[] = { JTI };
197 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
198 } else // Emit Load from Global Pointer
199 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
201 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
202 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
207 //===----------------------------------------------------------------------===//
208 // Calling Convention Implementation
210 // The lower operations present on calling convention works on this order:
211 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
212 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
213 // LowerRET (virt regs --> phys regs)
214 // LowerCALL (phys regs --> virt regs)
216 //===----------------------------------------------------------------------===//
218 #include "MipsGenCallingConv.inc"
220 //===----------------------------------------------------------------------===//
221 // CALL Calling Convention Implementation
222 //===----------------------------------------------------------------------===//
224 /// Mips custom CALL implementation
225 SDOperand MipsTargetLowering::
226 LowerCALL(SDOperand Op, SelectionDAG &DAG)
228 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
230 // By now, only CallingConv::C implemented
231 switch (CallingConv) {
233 assert(0 && "Unsupported calling convention");
234 case CallingConv::Fast:
236 return LowerCCCCallTo(Op, DAG, CallingConv);
240 /// LowerCCCCallTo - functions arguments are copied from virtual
241 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
242 /// CALLSEQ_END are emitted.
243 /// TODO: isVarArg, isTailCall, sret.
244 SDOperand MipsTargetLowering::
245 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
247 MachineFunction &MF = DAG.getMachineFunction();
249 SDOperand Chain = Op.getOperand(0);
250 SDOperand Callee = Op.getOperand(4);
251 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
253 MachineFrameInfo *MFI = MF.getFrameInfo();
255 // Analyze operands of the call, assigning locations to each operand.
256 SmallVector<CCValAssign, 16> ArgLocs;
257 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
259 // To meet ABI, Mips must always allocate 16 bytes on
260 // the stack (even if less than 4 are used as arguments)
261 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
262 MFI->CreateFixedObject(VTsize, (VTsize*3));
264 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
266 // Get a count of how many bytes are to be pushed on the stack.
267 unsigned NumBytes = CCInfo.getNextStackOffset();
268 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
271 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
272 SmallVector<SDOperand, 8> MemOpChains;
274 int LastStackLoc = 0;
276 // Walk the register/memloc assignments, inserting copies/loads.
277 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
278 CCValAssign &VA = ArgLocs[i];
280 // Arguments start after the 5 first operands of ISD::CALL
281 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
283 // Promote the value if needed.
284 switch (VA.getLocInfo()) {
285 default: assert(0 && "Unknown loc info!");
286 case CCValAssign::Full: break;
287 case CCValAssign::SExt:
288 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
290 case CCValAssign::ZExt:
291 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
293 case CCValAssign::AExt:
294 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
298 // Arguments that can be passed on register must be kept at
301 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
305 assert(VA.isMemLoc());
307 // Create the frame index object for this incoming parameter
308 // This guarantees that when allocating Local Area the firsts
309 // 16 bytes which are alwayes reserved won't be overwritten.
310 LastStackLoc = (16 + VA.getLocMemOffset());
311 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
314 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
316 // emit ISD::STORE whichs stores the
317 // parameter value to a stack Location
318 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
321 // Transform all store nodes into one single node because
322 // all store nodes are independent of each other.
323 if (!MemOpChains.empty())
324 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
325 &MemOpChains[0], MemOpChains.size());
327 // Build a sequence of copy-to-reg nodes chained together with token
328 // chain and flag operands which copy the outgoing args into registers.
329 // The InFlag in necessary since all emited instructions must be
332 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
333 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
334 RegsToPass[i].second, InFlag);
335 InFlag = Chain.getValue(1);
338 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
339 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
340 // node so that legalize doesn't hack it.
341 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
342 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
343 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
344 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
347 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
348 // = Chain, Callee, Reg#1, Reg#2, ...
350 // Returns a chain & a flag for retval copy to use.
351 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
352 SmallVector<SDOperand, 8> Ops;
353 Ops.push_back(Chain);
354 Ops.push_back(Callee);
356 // Add argument registers to the end of the list so that they are
357 // known live into the call.
358 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
359 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
360 RegsToPass[i].second.getValueType()));
363 Ops.push_back(InFlag);
365 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
366 InFlag = Chain.getValue(1);
368 // Create a stack location to hold GP when PIC is used. This stack
369 // location is used on function prologue to save GP and also after all
370 // emited CALL's to restore GP.
371 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
372 // Function can have an arbitrary number of calls, so
373 // hold the LastStackLoc with the biggest offset.
375 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
376 if (LastStackLoc >= MipsFI->getGPStackOffset()) {
377 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
378 // Create the frame index only once. SPOffset here can be anything
379 // (this will be fixed on processFunctionBeforeFrameFinalized)
380 if (MipsFI->getGPStackOffset() == -1) {
381 FI = MFI->CreateFixedObject(4, 0);
384 MipsFI->setGPStackOffset(LastStackLoc);
388 FI = MipsFI->getGPFI();
389 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
390 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
391 Chain = GPLoad.getValue(1);
392 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
393 GPLoad, SDOperand(0,0));
396 // Create the CALLSEQ_END node.
397 Chain = DAG.getCALLSEQ_END(Chain,
398 DAG.getConstant(NumBytes, getPointerTy()),
399 DAG.getConstant(0, getPointerTy()),
401 InFlag = Chain.getValue(1);
403 // Handle result values, copying them out of physregs into vregs that we
405 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
408 /// LowerCallResult - Lower the result values of an ISD::CALL into the
409 /// appropriate copies out of appropriate physical registers. This assumes that
410 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
411 /// being lowered. Returns a SDNode with the same number of values as the
413 SDNode *MipsTargetLowering::
414 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
415 unsigned CallingConv, SelectionDAG &DAG) {
417 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
419 // Assign locations to each value returned by this call.
420 SmallVector<CCValAssign, 16> RVLocs;
421 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
423 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
424 SmallVector<SDOperand, 8> ResultVals;
426 // Copy all of the result registers out of their specified physreg.
427 for (unsigned i = 0; i != RVLocs.size(); ++i) {
428 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
429 RVLocs[i].getValVT(), InFlag).getValue(1);
430 InFlag = Chain.getValue(2);
431 ResultVals.push_back(Chain.getValue(0));
434 ResultVals.push_back(Chain);
436 // Merge everything together with a MERGE_VALUES node.
437 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
438 &ResultVals[0], ResultVals.size()).Val;
441 //===----------------------------------------------------------------------===//
442 // FORMAL_ARGUMENTS Calling Convention Implementation
443 //===----------------------------------------------------------------------===//
445 /// Mips custom FORMAL_ARGUMENTS implementation
446 SDOperand MipsTargetLowering::
447 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
449 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
453 assert(0 && "Unsupported calling convention");
455 return LowerCCCArguments(Op, DAG);
459 /// LowerCCCArguments - transform physical registers into
460 /// virtual registers and generate load operations for
461 /// arguments places on the stack.
462 /// TODO: isVarArg, sret
463 SDOperand MipsTargetLowering::
464 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
466 SDOperand Root = Op.getOperand(0);
467 MachineFunction &MF = DAG.getMachineFunction();
468 MachineFrameInfo *MFI = MF.getFrameInfo();
469 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
471 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
472 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
474 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
476 // GP holds the GOT address on PIC calls.
477 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
478 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
480 // Assign locations to all of the incoming arguments.
481 SmallVector<CCValAssign, 16> ArgLocs;
482 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
484 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
485 SmallVector<SDOperand, 8> ArgValues;
488 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
490 CCValAssign &VA = ArgLocs[i];
492 // Arguments stored on registers
494 MVT::ValueType RegVT = VA.getLocVT();
495 TargetRegisterClass *RC;
497 if (RegVT == MVT::i32)
498 RC = Mips::CPURegsRegisterClass;
500 assert(0 && "support only Mips::CPURegsRegisterClass");
502 // Transform the arguments stored on
503 // physical registers into virtual ones
504 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
505 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
507 // If this is an 8 or 16-bit value, it is really passed promoted
508 // to 32 bits. Insert an assert[sz]ext to capture this, then
509 // truncate to the right size.
510 if (VA.getLocInfo() == CCValAssign::SExt)
511 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
512 DAG.getValueType(VA.getValVT()));
513 else if (VA.getLocInfo() == CCValAssign::ZExt)
514 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
515 DAG.getValueType(VA.getValVT()));
517 if (VA.getLocInfo() != CCValAssign::Full)
518 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
520 ArgValues.push_back(ArgValue);
522 // To meet ABI, when VARARGS are passed on registers, the registers
523 // must have their values written to the caller stack frame.
526 if (StackPtr.Val == 0)
527 StackPtr = DAG.getRegister(StackReg, getPointerTy());
529 // The stack pointer offset is relative to the caller stack frame.
530 // Since the real stack size is unknown here, a negative SPOffset
531 // is used so there's a way to adjust these offsets when the stack
532 // size get known (on EliminateFrameIndex). A dummy SPOffset is
533 // used instead of a direct negative address (which is recorded to
534 // be used on emitPrologue) to avoid mis-calc of the first stack
535 // offset on PEI::calculateFrameObjectOffsets.
536 // Arguments are always 32-bit.
537 int FI = MFI->CreateFixedObject(4, 0);
538 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
539 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
541 // emit ISD::STORE whichs stores the
542 // parameter value to a stack Location
543 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
548 assert(VA.isMemLoc());
550 // The stack pointer offset is relative to the caller stack frame.
551 // Since the real stack size is unknown here, a negative SPOffset
552 // is used so there's a way to adjust these offsets when the stack
553 // size get known (on EliminateFrameIndex). A dummy SPOffset is
554 // used instead of a direct negative address (which is recorded to
555 // be used on emitPrologue) to avoid mis-calc of the first stack
556 // offset on PEI::calculateFrameObjectOffsets.
557 // Arguments are always 32-bit.
558 int FI = MFI->CreateFixedObject(4, 0);
559 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
561 // Create load nodes to retrieve arguments from the stack
562 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
563 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
566 ArgValues.push_back(Root);
568 // Return the new list of results.
569 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
570 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
573 //===----------------------------------------------------------------------===//
574 // Return Value Calling Convention Implementation
575 //===----------------------------------------------------------------------===//
577 SDOperand MipsTargetLowering::
578 LowerRET(SDOperand Op, SelectionDAG &DAG)
580 // CCValAssign - represent the assignment of
581 // the return value to a location
582 SmallVector<CCValAssign, 16> RVLocs;
583 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
584 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
586 // CCState - Info about the registers and stack slot.
587 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
589 // Analize return values of ISD::RET
590 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
592 // If this is the first return lowered for this function, add
593 // the regs to the liveout set for the function.
594 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
595 for (unsigned i = 0; i != RVLocs.size(); ++i)
596 if (RVLocs[i].isRegLoc())
597 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
600 // The chain is always operand #0
601 SDOperand Chain = Op.getOperand(0);
604 // Copy the result values into the output registers.
605 for (unsigned i = 0; i != RVLocs.size(); ++i) {
606 CCValAssign &VA = RVLocs[i];
607 assert(VA.isRegLoc() && "Can only return in registers!");
609 // ISD::RET => ret chain, (regnum1,val1), ...
610 // So i*2+1 index only the regnums
611 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
613 // guarantee that all emitted copies are
614 // stuck together, avoiding something bad
615 Flag = Chain.getValue(1);
618 // Return on Mips is always a "jr $ra"
620 return DAG.getNode(MipsISD::Ret, MVT::Other,
621 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
623 return DAG.getNode(MipsISD::Ret, MVT::Other,
624 Chain, DAG.getRegister(Mips::RA, MVT::i32));
627 //===----------------------------------------------------------------------===//
628 // Mips Inline Assembly Support
629 //===----------------------------------------------------------------------===//
631 /// getConstraintType - Given a constraint letter, return the type of
632 /// constraint it is for this target.
633 MipsTargetLowering::ConstraintType MipsTargetLowering::
634 getConstraintType(const std::string &Constraint) const
636 if (Constraint.size() == 1) {
637 // Mips specific constrainy
638 // GCC config/mips/constraints.md
640 // 'd' : An address register. Equivalent to r
641 // unless generating MIPS16 code.
642 // 'y' : Equivalent to r; retained for
643 // backwards compatibility.
645 switch (Constraint[0]) {
649 return C_RegisterClass;
653 return TargetLowering::getConstraintType(Constraint);
656 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
657 getRegForInlineAsmConstraint(const std::string &Constraint,
658 MVT::ValueType VT) const
660 if (Constraint.size() == 1) {
661 switch (Constraint[0]) {
663 return std::make_pair(0U, Mips::CPURegsRegisterClass);
667 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
670 std::vector<unsigned> MipsTargetLowering::
671 getRegClassForInlineAsmConstraint(const std::string &Constraint,
672 MVT::ValueType VT) const
674 if (Constraint.size() != 1)
675 return std::vector<unsigned>();
677 switch (Constraint[0]) {
680 // GCC Mips Constraint Letters
683 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
684 Mips::A1, Mips::A2, Mips::A3,
685 Mips::T0, Mips::T1, Mips::T2,
686 Mips::T3, Mips::T4, Mips::T5,
687 Mips::T6, Mips::T7, Mips::S0,
688 Mips::S1, Mips::S2, Mips::S3,
689 Mips::S4, Mips::S5, Mips::S6,
690 Mips::S7, Mips::T8, Mips::T9, 0);
693 return std::vector<unsigned>();